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author | Abhinav Kumar <abhinavk@codeaurora.org> | 2018-06-14 21:01:10 -0700 |
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committer | Sean Paul <seanpaul@chromium.org> | 2018-11-30 11:57:53 -0500 |
commit | 8531f0587f5c9e1a74cd9543a97617349f5e0706 (patch) | |
tree | b7887f1a8dcdd4b6086496675a691f4ea96f29a6 /tools/perf/scripts/python/stackcollapse.py | |
parent | 47e7f506ee6590ceb2efa1f08aca7f9f2ee5c1d3 (diff) |
drm/msm/dsi: configure VCO rate for 10nm PLL driver
Currenty the VCO rate in the 10nm PLL driver relies
on the parent rate which is not configured.
Configure the VCO rate to 19.2 Mhz as required by
the 10nm PLL driver.
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions