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| author | Imre Deak <imre.deak@intel.com> | 2022-06-17 14:28:07 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-07-18 15:17:41 +0300 |
| commit | c19491894d4baf2155387e48aa326e1b52d7b986 (patch) | |
| tree | 8a7ca8e5e5af9de5ba1d5417f6f686ec311ba9a4 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 81cb44274c654e49f55e6690079540b0bd177db0 (diff) | |
drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order
Starting with TGL the disabling order of HDMI transcoder clock vs. DDI
BUF has swapped, fix this. There hasn't been any issues seen related to
this, but let's follow the spec.
Reported-by: Sandeep K Lakkakula <sandeep.k.lakkakula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions