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authorAndrew Jeffery <andrew@aj.id.au>2016-12-20 17:45:34 +1030
committerLee Jones <lee.jones@linaro.org>2017-02-13 09:29:42 +0000
commit73bee1d330a80943f1d0e13d32a739b80e44a470 (patch)
tree0b1e9cfe0490dda0e7d9b6028d57921fb4150cd1 /tools/perf/scripts/python
parent28fe081612307067f8183437c8b6ef722dcaa871 (diff)
mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux drivers. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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