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-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi31
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi32
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_socdk.dtsi9
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts31
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi4
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts43
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts53
8 files changed, 201 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7327250f0bb6..6f0c02d6d664 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -718,6 +718,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index da689659131f..2c43c4d85dee 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -93,6 +93,14 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
can0: can@ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -513,10 +521,24 @@
};
};
+ fpga_bridge0: fpga_bridge@ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge@ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
fpgamgr0: fpgamgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
- 0xffb90000 0x1000>;
+ 0xffb90000 0x4>;
interrupts = <0 175 4>;
};
@@ -694,6 +716,11 @@
arm,prefetch-offset = <7>;
};
+ l3regs@0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
mmc: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
@@ -751,7 +778,7 @@
};
sdr: sdr@ffc25000 {
- compatible = "syscon";
+ compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 551c636a4f01..65904db153be 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -83,6 +83,14 @@
};
};
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
@@ -512,6 +520,15 @@
};
};
+ fpga_mgr: fpga-mgr@ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ reset-names = "fpgamgr";
+ };
+
i2c0: i2c@ffc02200 {
#address-cells = <1>;
#size-cells = <0>;
@@ -578,7 +595,7 @@
};
sdr: sdr@ffc25000 {
- compatible = "syscon";
+ compatible = "altr,sdr-ctl", "syscon";
reg = <0xffcfb100 0x80>;
};
@@ -605,6 +622,19 @@
status = "disabled";
};
+ nand: nand@ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 99 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+ status = "disabled";
+ };
+
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index eb00ae37f316..4c99c99d1752 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -145,6 +145,11 @@
compatible = "dallas,ds1339";
reg = <0x68>;
};
+
+ ltc@5c {
+ compatible = "ltc2977";
+ reg = <0x5c>;
+ };
};
&uart1 {
@@ -154,3 +159,7 @@
&usb0 {
status = "okay";
};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
new file mode 100644
index 000000000000..d14f9ccb6e10
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+&nand {
+ status = "okay";
+
+ partition@nand-boot {
+ label = "Boot and fpga data";
+ reg = <0x0 0x1C00000>;
+ };
+ partition@nand-rootfs {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x1C00000 0x6400000>;
+ };
+};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 1907cc600452..8c037297296c 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -42,3 +42,7 @@
};
};
};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index f739ead074a2..8672edf9ba4e 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -39,6 +39,29 @@
ethernet0 = &gmac1;
};
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&porta 0 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 11 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&porta 17 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&porta 18 1>;
+ };
+ };
+
regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -61,8 +84,28 @@
rxc-skew-ps = <2000>;
};
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom@51 {
compatible = "atmel,24c32";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 6306d008f01b..7ea32c81e720 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -39,6 +39,29 @@
ethernet0 = &gmac1;
};
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 15 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 14 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 13 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&portb 12 1>;
+ };
+ };
+
regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -47,6 +70,10 @@
};
};
+&can0 {
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
@@ -61,12 +88,28 @@
rxc-skew-ps = <2000>;
};
+&gpio0 {
+ status = "okay";
+};
+
&gpio1 {
status = "okay";
};
+&gpio2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom@51 {
compatible = "atmel,24c32";
@@ -120,6 +163,16 @@
};
};
+&spi0 {
+ status = "okay";
+
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&usb1 {
status = "okay";
};
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-25 15:28:43 +0000