diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a07g044.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 4d4a23367529..485ef5f0fea1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -358,6 +358,23 @@ }; }; + sbc: spi@10060000 { + compatible = "renesas,r9a07g044-rpc-if", + "renesas,rzg2l-rpc-if"; + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, + <&cpg CPG_MOD R9A07G044_SPI_CLK>; + resets = <&cpg R9A07G044_SPI_RST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -439,6 +456,78 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g044", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; + clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + resets = <&cpg R9A07G044_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g044", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; + clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + resets = <&cpg R9A07G044_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g044-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G044_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G044_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g044-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G044_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G044_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { compatible = "renesas,r9a07g044-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; |