diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_types.h | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 17 |
3 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index b267987aed06..b6b60a9c0509 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -205,6 +205,16 @@ enum { #if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0)) #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#define FAMILY_VGH 144 +#define DEVICE_ID_VGH_163F 0x163F +#define VANGOGH_A0 0x01 +#define VANGOGH_UNKNOWN 0xFF + +#ifndef ASICREV_IS_VANGOGH +#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) +#endif +#endif /* * ASIC chip ID diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 8aaa3af69202..9cf6853193f8 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -51,7 +51,12 @@ enum dce_version { DCN_VERSION_1_01, DCN_VERSION_2_0, DCN_VERSION_2_1, +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) DCN_VERSION_3_0, +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + DCN_VERSION_3_01, +#endif DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 7a06e3914c00..04dd546a143c 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -284,6 +284,18 @@ struct ext_hdmi_settings { struct i2c_reg_info reg_settings_6g[3]; }; +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +struct edp_info { + uint16_t edp_backlight_pwm_hz; + uint16_t edp_ss_percentage; + uint16_t edp_ss_rate_10hz; + uint8_t edp_pwr_on_off_delay; + uint8_t edp_pwr_on_vary_bl_to_blon; + uint8_t edp_pwr_down_bloff_to_vary_bloff; + uint8_t edp_panel_bpc; + uint8_t edp_bootup_bl_level; +}; +#endif /* V6 */ struct integrated_info { @@ -403,6 +415,11 @@ struct integrated_info { struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3]; /* V11 */ uint32_t dp_ss_control; +#if defined(CONFIG_DRM_AMD_DC_DCN3_01) + /* V2.1 */ + struct edp_info edp1_info; + struct edp_info edp2_info; +#endif }; /** |