diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 81e5a3278fda..36d158d6c5b2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1977,8 +1977,8 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; - WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); - WARN_ON(fifo_size != 511); + drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63); + drm_WARN_ON(&dev_priv->drm, fifo_size != 511); trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); @@ -3417,7 +3417,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, * level is disabled. Doing otherwise could cause underruns. */ if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { - WARN_ON(wm_lp != 1); + drm_WARN_ON(&dev_priv->drm, wm_lp != 1); results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; } else results->wm_lp_spr[wm_lp - 1] = r->spr_val; @@ -3429,7 +3429,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, const struct intel_wm_level *r = &intel_crtc->wm.active.ilk.wm[0]; - if (WARN_ON(!r->enable)) + if (drm_WARN_ON(&dev_priv->drm, !r->enable)) continue; results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; @@ -3874,7 +3874,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv, u64 total_data_bw; u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size; - WARN_ON(ddb_size == 0); + drm_WARN_ON(&dev_priv->drm, ddb_size == 0); if (INTEL_GEN(dev_priv) < 11) return ddb_size - 4; /* 4 blocks for bypass path allocation */ @@ -3917,7 +3917,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, u16 ddb_size; u32 i; - if (WARN_ON(!state) || !crtc_state->hw.active) { + if (drm_WARN_ON(&dev_priv->drm, !state) || !crtc_state->hw.active) { alloc->start = 0; alloc->end = 0; *num_active = hweight8(dev_priv->active_pipes); @@ -4002,7 +4002,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, DRM_FORMAT_MOD_LINEAR, DRM_MODE_ROTATE_0, crtc_state->pixel_rate, &wp, 0); - WARN_ON(ret); + drm_WARN_ON(&dev_priv->drm, ret); for (level = 0; level <= max_level; level++) { skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); @@ -4294,7 +4294,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); - if (WARN_ON(!state)) + if (drm_WARN_ON(&dev_priv->drm, !state)) return 0; if (!crtc_state->hw.active) { @@ -4341,7 +4341,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, if (plane_id == PLANE_CURSOR) { if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) { - WARN_ON(wm->wm[level].min_ddb_alloc != U16_MAX); + drm_WARN_ON(&dev_priv->drm, + wm->wm[level].min_ddb_alloc != U16_MAX); blocks = U32_MAX; break; } @@ -4406,7 +4407,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, alloc_size -= extra; total_data_rate -= rate; } - WARN_ON(alloc_size != 0 || total_data_rate != 0); + drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0); /* Set the actual DDB start/end points for each plane */ start = alloc->start; @@ -4420,7 +4421,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, continue; /* Gen11+ uses a separate plane for UV watermarks */ - WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]); + drm_WARN_ON(&dev_priv->drm, + INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]); /* Leave disabled planes at (0,0) */ if (total[plane_id]) { |