diff options
Diffstat (limited to 'drivers/gpu/drm/msm/edp')
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp.c | 198 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp.h | 77 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp.xml.h | 388 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp_aux.c | 265 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp_bridge.c | 111 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp_connector.c | 132 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp_ctrl.c | 1373 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/edp/edp_phy.c | 98 |
8 files changed, 0 insertions, 2642 deletions
diff --git a/drivers/gpu/drm/msm/edp/edp.c b/drivers/gpu/drm/msm/edp/edp.c deleted file mode 100644 index 106a67473af5..000000000000 --- a/drivers/gpu/drm/msm/edp/edp.c +++ /dev/null @@ -1,198 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include <linux/of_irq.h> -#include "edp.h" - -static irqreturn_t edp_irq(int irq, void *dev_id) -{ - struct msm_edp *edp = dev_id; - - /* Process eDP irq */ - return msm_edp_ctrl_irq(edp->ctrl); -} - -static void edp_destroy(struct platform_device *pdev) -{ - struct msm_edp *edp = platform_get_drvdata(pdev); - - if (!edp) - return; - - if (edp->ctrl) { - msm_edp_ctrl_destroy(edp->ctrl); - edp->ctrl = NULL; - } - - platform_set_drvdata(pdev, NULL); -} - -/* construct eDP at bind/probe time, grab all the resources. */ -static struct msm_edp *edp_init(struct platform_device *pdev) -{ - struct msm_edp *edp = NULL; - int ret; - - if (!pdev) { - pr_err("no eDP device\n"); - ret = -ENXIO; - goto fail; - } - - edp = devm_kzalloc(&pdev->dev, sizeof(*edp), GFP_KERNEL); - if (!edp) { - ret = -ENOMEM; - goto fail; - } - DBG("eDP probed=%p", edp); - - edp->pdev = pdev; - platform_set_drvdata(pdev, edp); - - ret = msm_edp_ctrl_init(edp); - if (ret) - goto fail; - - return edp; - -fail: - if (edp) - edp_destroy(pdev); - - return ERR_PTR(ret); -} - -static int edp_bind(struct device *dev, struct device *master, void *data) -{ - struct drm_device *drm = dev_get_drvdata(master); - struct msm_drm_private *priv = drm->dev_private; - struct msm_edp *edp; - - DBG(""); - edp = edp_init(to_platform_device(dev)); - if (IS_ERR(edp)) - return PTR_ERR(edp); - priv->edp = edp; - - return 0; -} - -static void edp_unbind(struct device *dev, struct device *master, void *data) -{ - struct drm_device *drm = dev_get_drvdata(master); - struct msm_drm_private *priv = drm->dev_private; - - DBG(""); - if (priv->edp) { - edp_destroy(to_platform_device(dev)); - priv->edp = NULL; - } -} - -static const struct component_ops edp_ops = { - .bind = edp_bind, - .unbind = edp_unbind, -}; - -static int edp_dev_probe(struct platform_device *pdev) -{ - DBG(""); - return component_add(&pdev->dev, &edp_ops); -} - -static int edp_dev_remove(struct platform_device *pdev) -{ - DBG(""); - component_del(&pdev->dev, &edp_ops); - return 0; -} - -static const struct of_device_id dt_match[] = { - { .compatible = "qcom,mdss-edp" }, - {} -}; - -static struct platform_driver edp_driver = { - .probe = edp_dev_probe, - .remove = edp_dev_remove, - .driver = { - .name = "msm_edp", - .of_match_table = dt_match, - }, -}; - -void __init msm_edp_register(void) -{ - DBG(""); - platform_driver_register(&edp_driver); -} - -void __exit msm_edp_unregister(void) -{ - DBG(""); - platform_driver_unregister(&edp_driver); -} - -/* Second part of initialization, the drm/kms level modeset_init */ -int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, - struct drm_encoder *encoder) -{ - struct platform_device *pdev = edp->pdev; - struct msm_drm_private *priv = dev->dev_private; - int ret; - - edp->encoder = encoder; - edp->dev = dev; - - edp->bridge = msm_edp_bridge_init(edp); - if (IS_ERR(edp->bridge)) { - ret = PTR_ERR(edp->bridge); - DRM_DEV_ERROR(dev->dev, "failed to create eDP bridge: %d\n", ret); - edp->bridge = NULL; - goto fail; - } - - edp->connector = msm_edp_connector_init(edp); - if (IS_ERR(edp->connector)) { - ret = PTR_ERR(edp->connector); - DRM_DEV_ERROR(dev->dev, "failed to create eDP connector: %d\n", ret); - edp->connector = NULL; - goto fail; - } - - edp->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (edp->irq < 0) { - ret = edp->irq; - DRM_DEV_ERROR(dev->dev, "failed to get IRQ: %d\n", ret); - goto fail; - } - - ret = devm_request_irq(&pdev->dev, edp->irq, - edp_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "edp_isr", edp); - if (ret < 0) { - DRM_DEV_ERROR(dev->dev, "failed to request IRQ%u: %d\n", - edp->irq, ret); - goto fail; - } - - priv->bridges[priv->num_bridges++] = edp->bridge; - priv->connectors[priv->num_connectors++] = edp->connector; - - return 0; - -fail: - /* bridge/connector are normally destroyed by drm */ - if (edp->bridge) { - edp_bridge_destroy(edp->bridge); - edp->bridge = NULL; - } - if (edp->connector) { - edp->connector->funcs->destroy(edp->connector); - edp->connector = NULL; - } - - return ret; -} diff --git a/drivers/gpu/drm/msm/edp/edp.h b/drivers/gpu/drm/msm/edp/edp.h deleted file mode 100644 index 8590f2ce274d..000000000000 --- a/drivers/gpu/drm/msm/edp/edp.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#ifndef __EDP_CONNECTOR_H__ -#define __EDP_CONNECTOR_H__ - -#include <linux/i2c.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <drm/drm_bridge.h> -#include <drm/drm_crtc.h> -#include <drm/drm_dp_helper.h> - -#include "msm_drv.h" - -#define edp_read(offset) msm_readl((offset)) -#define edp_write(offset, data) msm_writel((data), (offset)) - -struct edp_ctrl; -struct edp_aux; -struct edp_phy; - -struct msm_edp { - struct drm_device *dev; - struct platform_device *pdev; - - struct drm_connector *connector; - struct drm_bridge *bridge; - - /* the encoder we are hooked to (outside of eDP block) */ - struct drm_encoder *encoder; - - struct edp_ctrl *ctrl; - - int irq; -}; - -/* eDP bridge */ -struct drm_bridge *msm_edp_bridge_init(struct msm_edp *edp); -void edp_bridge_destroy(struct drm_bridge *bridge); - -/* eDP connector */ -struct drm_connector *msm_edp_connector_init(struct msm_edp *edp); - -/* AUX */ -void *msm_edp_aux_init(struct msm_edp *edp, void __iomem *regbase, struct drm_dp_aux **drm_aux); -void msm_edp_aux_destroy(struct device *dev, struct edp_aux *aux); -irqreturn_t msm_edp_aux_irq(struct edp_aux *aux, u32 isr); -void msm_edp_aux_ctrl(struct edp_aux *aux, int enable); - -/* Phy */ -bool msm_edp_phy_ready(struct edp_phy *phy); -void msm_edp_phy_ctrl(struct edp_phy *phy, int enable); -void msm_edp_phy_vm_pe_init(struct edp_phy *phy); -void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1); -void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane); -void *msm_edp_phy_init(struct device *dev, void __iomem *regbase); - -/* Ctrl */ -irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl); -void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on); -int msm_edp_ctrl_init(struct msm_edp *edp); -void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl); -bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl); -int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl, - struct drm_connector *connector, struct edid **edid); -int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl, - const struct drm_display_mode *mode, - const struct drm_display_info *info); -/* @pixel_rate is in kHz */ -bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl, - u32 pixel_rate, u32 *pm, u32 *pn); - -#endif /* __EDP_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h deleted file mode 100644 index 7907e0f5988f..000000000000 --- a/drivers/gpu/drm/msm/edp/edp.xml.h +++ /dev/null @@ -1,388 +0,0 @@ -#ifndef EDP_XML -#define EDP_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git - -The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) - -Copyright (C) 2013-2021 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - - -enum edp_color_depth { - EDP_6BIT = 0, - EDP_8BIT = 1, - EDP_10BIT = 2, - EDP_12BIT = 3, - EDP_16BIT = 4, -}; - -enum edp_component_format { - EDP_RGB = 0, - EDP_YUV422 = 1, - EDP_YUV444 = 2, -}; - -#define REG_EDP_MAINLINK_CTRL 0x00000004 -#define EDP_MAINLINK_CTRL_ENABLE 0x00000001 -#define EDP_MAINLINK_CTRL_RESET 0x00000002 - -#define REG_EDP_STATE_CTRL 0x00000008 -#define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001 -#define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002 -#define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004 -#define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008 -#define EDP_STATE_CTRL_PRBS7 0x00000010 -#define EDP_STATE_CTRL_CUSTOM_80_BIT_PATTERN 0x00000020 -#define EDP_STATE_CTRL_SEND_VIDEO 0x00000040 -#define EDP_STATE_CTRL_PUSH_IDLE 0x00000080 - -#define REG_EDP_CONFIGURATION_CTRL 0x0000000c -#define EDP_CONFIGURATION_CTRL_SYNC_CLK 0x00000001 -#define EDP_CONFIGURATION_CTRL_STATIC_MVID 0x00000002 -#define EDP_CONFIGURATION_CTRL_PROGRESSIVE 0x00000004 -#define EDP_CONFIGURATION_CTRL_LANES__MASK 0x00000030 -#define EDP_CONFIGURATION_CTRL_LANES__SHIFT 4 -static inline uint32_t EDP_CONFIGURATION_CTRL_LANES(uint32_t val) -{ - return ((val) << EDP_CONFIGURATION_CTRL_LANES__SHIFT) & EDP_CONFIGURATION_CTRL_LANES__MASK; -} -#define EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING 0x00000040 -#define EDP_CONFIGURATION_CTRL_COLOR__MASK 0x00000100 -#define EDP_CONFIGURATION_CTRL_COLOR__SHIFT 8 -static inline uint32_t EDP_CONFIGURATION_CTRL_COLOR(enum edp_color_depth val) -{ - return ((val) << EDP_CONFIGURATION_CTRL_COLOR__SHIFT) & EDP_CONFIGURATION_CTRL_COLOR__MASK; -} - -#define REG_EDP_SOFTWARE_MVID 0x00000014 - -#define REG_EDP_SOFTWARE_NVID 0x00000018 - -#define REG_EDP_TOTAL_HOR_VER 0x0000001c -#define EDP_TOTAL_HOR_VER_HORIZ__MASK 0x0000ffff -#define EDP_TOTAL_HOR_VER_HORIZ__SHIFT 0 -static inline uint32_t EDP_TOTAL_HOR_VER_HORIZ(uint32_t val) -{ - return ((val) << EDP_TOTAL_HOR_VER_HORIZ__SHIFT) & EDP_TOTAL_HOR_VER_HORIZ__MASK; -} -#define EDP_TOTAL_HOR_VER_VERT__MASK 0xffff0000 -#define EDP_TOTAL_HOR_VER_VERT__SHIFT 16 -static inline uint32_t EDP_TOTAL_HOR_VER_VERT(uint32_t val) -{ - return ((val) << EDP_TOTAL_HOR_VER_VERT__SHIFT) & EDP_TOTAL_HOR_VER_VERT__MASK; -} - -#define REG_EDP_START_HOR_VER_FROM_SYNC 0x00000020 -#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK 0x0000ffff -#define EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT 0 -static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_HORIZ(uint32_t val) -{ - return ((val) << EDP_START_HOR_VER_FROM_SYNC_HORIZ__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_HORIZ__MASK; -} -#define EDP_START_HOR_VER_FROM_SYNC_VERT__MASK 0xffff0000 -#define EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT 16 -static inline uint32_t EDP_START_HOR_VER_FROM_SYNC_VERT(uint32_t val) -{ - return ((val) << EDP_START_HOR_VER_FROM_SYNC_VERT__SHIFT) & EDP_START_HOR_VER_FROM_SYNC_VERT__MASK; -} - -#define REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY 0x00000024 -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK 0x00007fff -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT 0 -static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ(uint32_t val) -{ - return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ__MASK; -} -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC 0x00008000 -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK 0x7fff0000 -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT 16 -static inline uint32_t EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT(uint32_t val) -{ - return ((val) << EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__SHIFT) & EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT__MASK; -} -#define EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC 0x80000000 - -#define REG_EDP_ACTIVE_HOR_VER 0x00000028 -#define EDP_ACTIVE_HOR_VER_HORIZ__MASK 0x0000ffff -#define EDP_ACTIVE_HOR_VER_HORIZ__SHIFT 0 -static inline uint32_t EDP_ACTIVE_HOR_VER_HORIZ(uint32_t val) -{ - return ((val) << EDP_ACTIVE_HOR_VER_HORIZ__SHIFT) & EDP_ACTIVE_HOR_VER_HORIZ__MASK; -} -#define EDP_ACTIVE_HOR_VER_VERT__MASK 0xffff0000 -#define EDP_ACTIVE_HOR_VER_VERT__SHIFT 16 -static inline uint32_t EDP_ACTIVE_HOR_VER_VERT(uint32_t val) -{ - return ((val) << EDP_ACTIVE_HOR_VER_VERT__SHIFT) & EDP_ACTIVE_HOR_VER_VERT__MASK; -} - -#define REG_EDP_MISC1_MISC0 0x0000002c -#define EDP_MISC1_MISC0_MISC0__MASK 0x000000ff -#define EDP_MISC1_MISC0_MISC0__SHIFT 0 -static inline uint32_t EDP_MISC1_MISC0_MISC0(uint32_t val) -{ - return ((val) << EDP_MISC1_MISC0_MISC0__SHIFT) & EDP_MISC1_MISC0_MISC0__MASK; -} -#define EDP_MISC1_MISC0_SYNC 0x00000001 -#define EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK 0x00000006 -#define EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT 1 -static inline uint32_t EDP_MISC1_MISC0_COMPONENT_FORMAT(enum edp_component_format val) -{ - return ((val) << EDP_MISC1_MISC0_COMPONENT_FORMAT__SHIFT) & EDP_MISC1_MISC0_COMPONENT_FORMAT__MASK; -} -#define EDP_MISC1_MISC0_CEA 0x00000008 -#define EDP_MISC1_MISC0_BT709_5 0x00000010 -#define EDP_MISC1_MISC0_COLOR__MASK 0x000000e0 -#define EDP_MISC1_MISC0_COLOR__SHIFT 5 -static inline uint32_t EDP_MISC1_MISC0_COLOR(enum edp_color_depth val) -{ - return ((val) << EDP_MISC1_MISC0_COLOR__SHIFT) & EDP_MISC1_MISC0_COLOR__MASK; -} -#define EDP_MISC1_MISC0_MISC1__MASK 0x0000ff00 -#define EDP_MISC1_MISC0_MISC1__SHIFT 8 -static inline uint32_t EDP_MISC1_MISC0_MISC1(uint32_t val) -{ - return ((val) << EDP_MISC1_MISC0_MISC1__SHIFT) & EDP_MISC1_MISC0_MISC1__MASK; -} -#define EDP_MISC1_MISC0_INTERLACED_ODD 0x00000100 -#define EDP_MISC1_MISC0_STEREO__MASK 0x00000600 -#define EDP_MISC1_MISC0_STEREO__SHIFT 9 -static inline uint32_t EDP_MISC1_MISC0_STEREO(uint32_t val) -{ - return ((val) << EDP_MISC1_MISC0_STEREO__SHIFT) & EDP_MISC1_MISC0_STEREO__MASK; -} - -#define REG_EDP_PHY_CTRL 0x00000074 -#define EDP_PHY_CTRL_SW_RESET_PLL 0x00000001 -#define EDP_PHY_CTRL_SW_RESET 0x00000004 - -#define REG_EDP_MAINLINK_READY 0x00000084 -#define EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY 0x00000008 -#define EDP_MAINLINK_READY_TRAIN_PATTERN_2_READY 0x00000010 -#define EDP_MAINLINK_READY_TRAIN_PATTERN_3_READY 0x00000020 - -#define REG_EDP_AUX_CTRL 0x00000300 -#define EDP_AUX_CTRL_ENABLE 0x00000001 -#define EDP_AUX_CTRL_RESET 0x00000002 - -#define REG_EDP_INTERRUPT_REG_1 0x00000308 -#define EDP_INTERRUPT_REG_1_HPD 0x00000001 -#define EDP_INTERRUPT_REG_1_HPD_ACK 0x00000002 -#define EDP_INTERRUPT_REG_1_HPD_EN 0x00000004 -#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE 0x00000008 -#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_ACK 0x00000010 -#define EDP_INTERRUPT_REG_1_AUX_I2C_DONE_EN 0x00000020 -#define EDP_INTERRUPT_REG_1_WRONG_ADDR 0x00000040 -#define EDP_INTERRUPT_REG_1_WRONG_ADDR_ACK 0x00000080 -#define EDP_INTERRUPT_REG_1_WRONG_ADDR_EN 0x00000100 -#define EDP_INTERRUPT_REG_1_TIMEOUT 0x00000200 -#define EDP_INTERRUPT_REG_1_TIMEOUT_ACK 0x00000400 -#define EDP_INTERRUPT_REG_1_TIMEOUT_EN 0x00000800 -#define EDP_INTERRUPT_REG_1_NACK_DEFER 0x00001000 -#define EDP_INTERRUPT_REG_1_NACK_DEFER_ACK 0x00002000 -#define EDP_INTERRUPT_REG_1_NACK_DEFER_EN 0x00004000 -#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT 0x00008000 -#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_ACK 0x00010000 -#define EDP_INTERRUPT_REG_1_WRONG_DATA_CNT_EN 0x00020000 -#define EDP_INTERRUPT_REG_1_I2C_NACK 0x00040000 -#define EDP_INTERRUPT_REG_1_I2C_NACK_ACK 0x00080000 -#define EDP_INTERRUPT_REG_1_I2C_NACK_EN 0x00100000 -#define EDP_INTERRUPT_REG_1_I2C_DEFER 0x00200000 -#define EDP_INTERRUPT_REG_1_I2C_DEFER_ACK 0x00400000 -#define EDP_INTERRUPT_REG_1_I2C_DEFER_EN 0x00800000 -#define EDP_INTERRUPT_REG_1_PLL_UNLOCK 0x01000000 -#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_ACK 0x02000000 -#define EDP_INTERRUPT_REG_1_PLL_UNLOCK_EN 0x04000000 -#define EDP_INTERRUPT_REG_1_AUX_ERROR 0x08000000 -#define EDP_INTERRUPT_REG_1_AUX_ERROR_ACK 0x10000000 -#define EDP_INTERRUPT_REG_1_AUX_ERROR_EN 0x20000000 - -#define REG_EDP_INTERRUPT_REG_2 0x0000030c -#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO 0x00000001 -#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_ACK 0x00000002 -#define EDP_INTERRUPT_REG_2_READY_FOR_VIDEO_EN 0x00000004 -#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT 0x00000008 -#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_ACK 0x00000010 -#define EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT_EN 0x00000020 -#define EDP_INTERRUPT_REG_2_FRAME_END 0x00000200 -#define EDP_INTERRUPT_REG_2_FRAME_END_ACK 0x00000080 -#define EDP_INTERRUPT_REG_2_FRAME_END_EN 0x00000100 -#define EDP_INTERRUPT_REG_2_CRC_UPDATED 0x00000200 -#define EDP_INTERRUPT_REG_2_CRC_UPDATED_ACK 0x00000400 -#define EDP_INTERRUPT_REG_2_CRC_UPDATED_EN 0x00000800 - -#define REG_EDP_INTERRUPT_TRANS_NUM 0x00000310 - -#define REG_EDP_AUX_DATA 0x00000314 -#define EDP_AUX_DATA_READ 0x00000001 -#define EDP_AUX_DATA_DATA__MASK 0x0000ff00 -#define EDP_AUX_DATA_DATA__SHIFT 8 -static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val) -{ - return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK; -} -#define EDP_AUX_DATA_INDEX__MASK 0x00ff0000 -#define EDP_AUX_DATA_INDEX__SHIFT 16 -static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val) -{ - return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK; -} -#define EDP_AUX_DATA_INDEX_WRITE 0x80000000 - -#define REG_EDP_AUX_TRANS_CTRL 0x00000318 -#define EDP_AUX_TRANS_CTRL_I2C 0x00000100 -#define EDP_AUX_TRANS_CTRL_GO 0x00000200 - -#define REG_EDP_AUX_STATUS 0x00000324 - -static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } - -static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } - -#define REG_EDP_PHY_GLB_VM_CFG0 0x00000510 - -#define REG_EDP_PHY_GLB_VM_CFG1 0x00000514 - -#define REG_EDP_PHY_GLB_MISC9 0x00000518 - -#define REG_EDP_PHY_GLB_CFG 0x00000528 - -#define REG_EDP_PHY_GLB_PD_CTL 0x0000052c - -#define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598 - -#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000 - -#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 - -#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 - -#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c - -#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010 - -#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 - -#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018 - -#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c - -#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020 -#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 -#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 -#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 -#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 - -#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 - -#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 - -#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c - -#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030 - -#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034 - -#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038 - -#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c - -#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040 - -#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044 - -#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048 - -#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c - -#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050 - -#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054 - -#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058 - -#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c - -#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060 - -#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064 - -#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068 -#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094 - -#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098 - -#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c - -#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 - - -#endif /* EDP_XML */ diff --git a/drivers/gpu/drm/msm/edp/edp_aux.c b/drivers/gpu/drm/msm/edp/edp_aux.c deleted file mode 100644 index e3d85c622cfb..000000000000 --- a/drivers/gpu/drm/msm/edp/edp_aux.c +++ /dev/null @@ -1,265 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "edp.h" -#include "edp.xml.h" - -#define AUX_CMD_FIFO_LEN 144 -#define AUX_CMD_NATIVE_MAX 16 -#define AUX_CMD_I2C_MAX 128 - -#define EDP_INTR_AUX_I2C_ERR \ - (EDP_INTERRUPT_REG_1_WRONG_ADDR | EDP_INTERRUPT_REG_1_TIMEOUT | \ - EDP_INTERRUPT_REG_1_NACK_DEFER | EDP_INTERRUPT_REG_1_WRONG_DATA_CNT | \ - EDP_INTERRUPT_REG_1_I2C_NACK | EDP_INTERRUPT_REG_1_I2C_DEFER) -#define EDP_INTR_TRANS_STATUS \ - (EDP_INTERRUPT_REG_1_AUX_I2C_DONE | EDP_INTR_AUX_I2C_ERR) - -struct edp_aux { - void __iomem *base; - bool msg_err; - - struct completion msg_comp; - - /* To prevent the message transaction routine from reentry. */ - struct mutex msg_mutex; - - struct drm_dp_aux drm_aux; -}; -#define to_edp_aux(x) container_of(x, struct edp_aux, drm_aux) - -static int edp_msg_fifo_tx(struct edp_aux *aux, struct drm_dp_aux_msg *msg) -{ - u32 data[4]; - u32 reg, len; - bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); - bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); - u8 *msgdata = msg->buffer; - int i; - - if (read) - len = 4; - else - len = msg->size + 4; - - /* - * cmd fifo only has depth of 144 bytes - */ - if (len > AUX_CMD_FIFO_LEN) - return -EINVAL; - - /* Pack cmd and write to HW */ - data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */ - if (read) - data[0] |= BIT(4); /* R/W */ - - data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */ - data[2] = msg->address & 0xff; /* addr[7:0] */ - data[3] = (msg->size - 1) & 0xff; /* len[7:0] */ - - for (i = 0; i < len; i++) { - reg = (i < 4) ? data[i] : msgdata[i - 4]; - reg = EDP_AUX_DATA_DATA(reg); /* index = 0, write */ - if (i == 0) - reg |= EDP_AUX_DATA_INDEX_WRITE; - edp_write(aux->base + REG_EDP_AUX_DATA, reg); - } - - reg = 0; /* Transaction number is always 1 */ - if (!native) /* i2c */ - reg |= EDP_AUX_TRANS_CTRL_I2C; - - reg |= EDP_AUX_TRANS_CTRL_GO; - edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, reg); - - return 0; -} - -static int edp_msg_fifo_rx(struct edp_aux *aux, struct drm_dp_aux_msg *msg) -{ - u32 data; - u8 *dp; - int i; - u32 len = msg->size; - - edp_write(aux->base + REG_EDP_AUX_DATA, - EDP_AUX_DATA_INDEX_WRITE | EDP_AUX_DATA_READ); /* index = 0 */ - - dp = msg->buffer; - - /* discard first byte */ - data = edp_read(aux->base + REG_EDP_AUX_DATA); - for (i = 0; i < len; i++) { - data = edp_read(aux->base + REG_EDP_AUX_DATA); - dp[i] = (u8)((data >> 8) & 0xff); - } - - return 0; -} - -/* - * This function does the real job to process an AUX transaction. - * It will call msm_edp_aux_ctrl() function to reset the AUX channel, - * if the waiting is timeout. - * The caller who triggers the transaction should avoid the - * msm_edp_aux_ctrl() running concurrently in other threads, i.e. - * start transaction only when AUX channel is fully enabled. - */ -static ssize_t edp_aux_transfer(struct drm_dp_aux *drm_aux, - struct drm_dp_aux_msg *msg) -{ - struct edp_aux *aux = to_edp_aux(drm_aux); - ssize_t ret; - unsigned long time_left; - bool native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); - bool read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); - - /* Ignore address only message */ - if ((msg->size == 0) || (msg->buffer == NULL)) { - msg->reply = native ? - DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; - return msg->size; - } - - /* msg sanity check */ - if ((native && (msg->size > AUX_CMD_NATIVE_MAX)) || - (msg->size > AUX_CMD_I2C_MAX)) { - pr_err("%s: invalid msg: size(%zu), request(%x)\n", - __func__, msg->size, msg->request); - return -EINVAL; - } - - mutex_lock(&aux->msg_mutex); - - aux->msg_err = false; - reinit_completion(&aux->msg_comp); - - ret = edp_msg_fifo_tx(aux, msg); - if (ret < 0) - goto unlock_exit; - - DBG("wait_for_completion"); - time_left = wait_for_completion_timeout(&aux->msg_comp, - msecs_to_jiffies(300)); - if (!time_left) { - /* - * Clear GO and reset AUX channel - * to cancel the current transaction. - */ - edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); - msm_edp_aux_ctrl(aux, 1); - pr_err("%s: aux timeout,\n", __func__); - ret = -ETIMEDOUT; - goto unlock_exit; - } - DBG("completion"); - - if (!aux->msg_err) { - if (read) { - ret = edp_msg_fifo_rx(aux, msg); - if (ret < 0) - goto unlock_exit; - } - - msg->reply = native ? - DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; - } else { - /* Reply defer to retry */ - msg->reply = native ? - DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER; - /* - * The sleep time in caller is not long enough to make sure - * our H/W completes transactions. Add more defer time here. - */ - msleep(100); - } - - /* Return requested size for success or retry */ - ret = msg->size; - -unlock_exit: - mutex_unlock(&aux->msg_mutex); - return ret; -} - -void *msm_edp_aux_init(struct msm_edp *edp, void __iomem *regbase, struct drm_dp_aux **drm_aux) -{ - struct device *dev = &edp->pdev->dev; - struct edp_aux *aux = NULL; - int ret; - - DBG(""); - aux = devm_kzalloc(dev, sizeof(*aux), GFP_KERNEL); - if (!aux) - return NULL; - - aux->base = regbase; - mutex_init(&aux->msg_mutex); - init_completion(&aux->msg_comp); - - aux->drm_aux.name = "msm_edp_aux"; - aux->drm_aux.dev = dev; - aux->drm_aux.drm_dev = edp->dev; - aux->drm_aux.transfer = edp_aux_transfer; - ret = drm_dp_aux_register(&aux->drm_aux); - if (ret) { - pr_err("%s: failed to register drm aux: %d\n", __func__, ret); - mutex_destroy(&aux->msg_mutex); - } - - if (drm_aux && aux) - *drm_aux = &aux->drm_aux; - - return aux; -} - -void msm_edp_aux_destroy(struct device *dev, struct edp_aux *aux) -{ - if (aux) { - drm_dp_aux_unregister(&aux->drm_aux); - mutex_destroy(&aux->msg_mutex); - } -} - -irqreturn_t msm_edp_aux_irq(struct edp_aux *aux, u32 isr) -{ - if (isr & EDP_INTR_TRANS_STATUS) { - DBG("isr=%x", isr); - edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); - - if (isr & EDP_INTR_AUX_I2C_ERR) - aux->msg_err = true; - else - aux->msg_err = false; - - complete(&aux->msg_comp); - } - - return IRQ_HANDLED; -} - -void msm_edp_aux_ctrl(struct edp_aux *aux, int enable) -{ - u32 data; - - DBG("enable=%d", enable); - data = edp_read(aux->base + REG_EDP_AUX_CTRL); - - if (enable) { - data |= EDP_AUX_CTRL_RESET; - edp_write(aux->base + REG_EDP_AUX_CTRL, data); - /* Make sure full reset */ - wmb(); - usleep_range(500, 1000); - - data &= ~EDP_AUX_CTRL_RESET; - data |= EDP_AUX_CTRL_ENABLE; - edp_write(aux->base + REG_EDP_AUX_CTRL, data); - } else { - data &= ~EDP_AUX_CTRL_ENABLE; - edp_write(aux->base + REG_EDP_AUX_CTRL, data); - } -} - diff --git a/drivers/gpu/drm/msm/edp/edp_bridge.c b/drivers/gpu/drm/msm/edp/edp_bridge.c deleted file mode 100644 index c69a37e0c708..000000000000 --- a/drivers/gpu/drm/msm/edp/edp_bridge.c +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "edp.h" - -struct edp_bridge { - struct drm_bridge base; - struct msm_edp *edp; -}; -#define to_edp_bridge(x) container_of(x, struct edp_bridge, base) - -void edp_bridge_destroy(struct drm_bridge *bridge) -{ -} - -static void edp_bridge_pre_enable(struct drm_bridge *bridge) -{ - struct edp_bridge *edp_bridge = to_edp_bridge(bridge); - struct msm_edp *edp = edp_bridge->edp; - - DBG(""); - msm_edp_ctrl_power(edp->ctrl, true); -} - -static void edp_bridge_enable(struct drm_bridge *bridge) -{ - DBG(""); -} - -static void edp_bridge_disable(struct drm_bridge *bridge) -{ - DBG(""); -} - -static void edp_bridge_post_disable(struct drm_bridge *bridge) -{ - struct edp_bridge *edp_bridge = to_edp_bridge(bridge); - struct msm_edp *edp = edp_bridge->edp; - - DBG(""); - msm_edp_ctrl_power(edp->ctrl, false); -} - -static void edp_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct drm_device *dev = bridge->dev; - struct drm_connector *connector; - struct edp_bridge *edp_bridge = to_edp_bridge(bridge); - struct msm_edp *edp = edp_bridge->edp; - - DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode)); - - list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct drm_encoder *encoder = connector->encoder; - struct drm_bridge *first_bridge; - - if (!connector->encoder) - continue; - - first_bridge = drm_bridge_chain_get_first_bridge(encoder); - if (bridge == first_bridge) { - msm_edp_ctrl_timing_cfg(edp->ctrl, - adjusted_mode, &connector->display_info); - break; - } - } -} - -static const struct drm_bridge_funcs edp_bridge_funcs = { - .pre_enable = edp_bridge_pre_enable, - .enable = edp_bridge_enable, - .disable = edp_bridge_disable, - .post_disable = edp_bridge_post_disable, - .mode_set = edp_bridge_mode_set, -}; - -/* initialize bridge */ -struct drm_bridge *msm_edp_bridge_init(struct msm_edp *edp) -{ - struct drm_bridge *bridge = NULL; - struct edp_bridge *edp_bridge; - int ret; - - edp_bridge = devm_kzalloc(edp->dev->dev, - sizeof(*edp_bridge), GFP_KERNEL); - if (!edp_bridge) { - ret = -ENOMEM; - goto fail; - } - - edp_bridge->edp = edp; - - bridge = &edp_bridge->base; - bridge->funcs = &edp_bridge_funcs; - - ret = drm_bridge_attach(edp->encoder, bridge, NULL, 0); - if (ret) - goto fail; - - return bridge; - -fail: - if (bridge) - edp_bridge_destroy(bridge); - - return ERR_PTR(ret); -} diff --git a/drivers/gpu/drm/msm/edp/edp_connector.c b/drivers/gpu/drm/msm/edp/edp_connector.c deleted file mode 100644 index 73cb5fd97a5a..000000000000 --- a/drivers/gpu/drm/msm/edp/edp_connector.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "drm/drm_edid.h" -#include "msm_kms.h" -#include "edp.h" - -struct edp_connector { - struct drm_connector base; - struct msm_edp *edp; -}; -#define to_edp_connector(x) container_of(x, struct edp_connector, base) - -static enum drm_connector_status edp_connector_detect( - struct drm_connector *connector, bool force) -{ - struct edp_connector *edp_connector = to_edp_connector(connector); - struct msm_edp *edp = edp_connector->edp; - - DBG(""); - return msm_edp_ctrl_panel_connected(edp->ctrl) ? - connector_status_connected : connector_status_disconnected; -} - -static void edp_connector_destroy(struct drm_connector *connector) -{ - struct edp_connector *edp_connector = to_edp_connector(connector); - - DBG(""); - - drm_connector_cleanup(connector); - - kfree(edp_connector); -} - -static int edp_connector_get_modes(struct drm_connector *connector) -{ - struct edp_connector *edp_connector = to_edp_connector(connector); - struct msm_edp *edp = edp_connector->edp; - - struct edid *drm_edid = NULL; - int ret = 0; - - DBG(""); - ret = msm_edp_ctrl_get_panel_info(edp->ctrl, connector, &drm_edid); - if (ret) - return ret; - - drm_connector_update_edid_property(connector, drm_edid); - if (drm_edid) - ret = drm_add_edid_modes(connector, drm_edid); - - return ret; -} - -static int edp_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct edp_connector *edp_connector = to_edp_connector(connector); - struct msm_edp *edp = edp_connector->edp; - struct msm_drm_private *priv = connector->dev->dev_private; - struct msm_kms *kms = priv->kms; - long actual, requested; - - requested = 1000 * mode->clock; - actual = kms->funcs->round_pixclk(kms, - requested, edp_connector->edp->encoder); - - DBG("requested=%ld, actual=%ld", requested, actual); - if (actual != requested) - return MODE_CLOCK_RANGE; - - if (!msm_edp_ctrl_pixel_clock_valid( - edp->ctrl, mode->clock, NULL, NULL)) - return MODE_CLOCK_RANGE; - - /* Invalidate all modes if color format is not supported */ - if (connector->display_info.bpc > 8) - return MODE_BAD; - - return MODE_OK; -} - -static const struct drm_connector_funcs edp_connector_funcs = { - .detect = edp_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = edp_connector_destroy, - .reset = drm_atomic_helper_connector_reset, - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -}; - -static const struct drm_connector_helper_funcs edp_connector_helper_funcs = { - .get_modes = edp_connector_get_modes, - .mode_valid = edp_connector_mode_valid, -}; - -/* initialize connector */ -struct drm_connector *msm_edp_connector_init(struct msm_edp *edp) -{ - struct drm_connector *connector = NULL; - struct edp_connector *edp_connector; - int ret; - - edp_connector = kzalloc(sizeof(*edp_connector), GFP_KERNEL); - if (!edp_connector) - return ERR_PTR(-ENOMEM); - - edp_connector->edp = edp; - - connector = &edp_connector->base; - - ret = drm_connector_init(edp->dev, connector, &edp_connector_funcs, - DRM_MODE_CONNECTOR_eDP); - if (ret) - return ERR_PTR(ret); - - drm_connector_helper_add(connector, &edp_connector_helper_funcs); - - /* We don't support HPD, so only poll status until connected. */ - connector->polled = DRM_CONNECTOR_POLL_CONNECT; - - /* Display driver doesn't support interlace now. */ - connector->interlace_allowed = false; - connector->doublescan_allowed = false; - - drm_connector_attach_encoder(connector, edp->encoder); - - return connector; -} diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c deleted file mode 100644 index a68a4a1867c1..000000000000 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ /dev/null @@ -1,1373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include <linux/clk.h> -#include <linux/gpio/consumer.h> -#include <linux/regulator/consumer.h> -#include <drm/drm_crtc.h> -#include <drm/drm_dp_helper.h> -#include <drm/drm_edid.h> - -#include "edp.h" -#include "edp.xml.h" - -#define VDDA_UA_ON_LOAD 100000 /* uA units */ -#define VDDA_UA_OFF_LOAD 100 /* uA units */ - -#define DPCD_LINK_VOLTAGE_MAX 4 -#define DPCD_LINK_PRE_EMPHASIS_MAX 4 - -#define EDP_LINK_BW_MAX DP_LINK_BW_2_7 - -/* Link training return value */ -#define EDP_TRAIN_FAIL -1 -#define EDP_TRAIN_SUCCESS 0 -#define EDP_TRAIN_RECONFIG 1 - -#define EDP_CLK_MASK_AHB BIT(0) -#define EDP_CLK_MASK_AUX BIT(1) -#define EDP_CLK_MASK_LINK BIT(2) -#define EDP_CLK_MASK_PIXEL BIT(3) -#define EDP_CLK_MASK_MDP_CORE BIT(4) -#define EDP_CLK_MASK_LINK_CHAN (EDP_CLK_MASK_LINK | EDP_CLK_MASK_PIXEL) -#define EDP_CLK_MASK_AUX_CHAN \ - (EDP_CLK_MASK_AHB | EDP_CLK_MASK_AUX | EDP_CLK_MASK_MDP_CORE) -#define EDP_CLK_MASK_ALL (EDP_CLK_MASK_AUX_CHAN | EDP_CLK_MASK_LINK_CHAN) - -#define EDP_BACKLIGHT_MAX 255 - -#define EDP_INTR_STATUS1 \ - (EDP_INTERRUPT_REG_1_HPD | EDP_INTERRUPT_REG_1_AUX_I2C_DONE | \ - EDP_INTERRUPT_REG_1_WRONG_ADDR | EDP_INTERRUPT_REG_1_TIMEOUT | \ - EDP_INTERRUPT_REG_1_NACK_DEFER | EDP_INTERRUPT_REG_1_WRONG_DATA_CNT | \ - EDP_INTERRUPT_REG_1_I2C_NACK | EDP_INTERRUPT_REG_1_I2C_DEFER | \ - EDP_INTERRUPT_REG_1_PLL_UNLOCK | EDP_INTERRUPT_REG_1_AUX_ERROR) -#define EDP_INTR_MASK1 (EDP_INTR_STATUS1 << 2) -#define EDP_INTR_STATUS2 \ - (EDP_INTERRUPT_REG_2_READY_FOR_VIDEO | \ - EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT | \ - EDP_INTERRUPT_REG_2_FRAME_END | EDP_INTERRUPT_REG_2_CRC_UPDATED) -#define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2) - -struct edp_ctrl { - struct platform_device *pdev; - - void __iomem *base; - - /* regulators */ - struct regulator *vdda_vreg; /* 1.8 V */ - struct regulator *lvl_vreg; - - /* clocks */ - struct clk *aux_clk; - struct clk *pixel_clk; - struct clk *ahb_clk; - struct clk *link_clk; - struct clk *mdp_core_clk; - - /* gpios */ - struct gpio_desc *panel_en_gpio; - struct gpio_desc *panel_hpd_gpio; - - /* completion and mutex */ - struct completion idle_comp; - struct mutex dev_mutex; /* To protect device power status */ - - /* work queue */ - struct work_struct on_work; - struct work_struct off_work; - struct workqueue_struct *workqueue; - - /* Interrupt register lock */ - spinlock_t irq_lock; - - bool edp_connected; - bool power_on; - - /* edid raw data */ - struct edid *edid; - - struct drm_dp_aux *drm_aux; - - /* dpcd raw data */ - u8 dpcd[DP_RECEIVER_CAP_SIZE]; - - /* Link status */ - u8 link_rate; - u8 lane_cnt; - u8 v_level; - u8 p_level; - - /* Timing status */ - u8 interlaced; - u32 pixel_rate; /* in kHz */ - u32 color_depth; - - struct edp_aux *aux; - struct edp_phy *phy; -}; - -struct edp_pixel_clk_div { - u32 rate; /* in kHz */ - u32 m; - u32 n; -}; - -#define EDP_PIXEL_CLK_NUM 8 -static const struct edp_pixel_clk_div clk_divs[2][EDP_PIXEL_CLK_NUM] = { - { /* Link clock = 162MHz, source clock = 810MHz */ - {119000, 31, 211}, /* WSXGA+ 1680x1050@60Hz CVT */ - {130250, 32, 199}, /* UXGA 1600x1200@60Hz CVT */ - {148500, 11, 60}, /* FHD 1920x1080@60Hz */ - {154000, 50, 263}, /* WUXGA 1920x1200@60Hz CVT */ - {209250, 31, 120}, /* QXGA 2048x1536@60Hz CVT */ - {268500, 119, 359}, /* WQXGA 2560x1600@60Hz CVT */ - {138530, 33, 193}, /* AUO B116HAN03.0 Panel */ - {141400, 48, 275}, /* AUO B133HTN01.2 Panel */ - }, - { /* Link clock = 270MHz, source clock = 675MHz */ - {119000, 52, 295}, /* WSXGA+ 1680x1050@60Hz CVT */ - {130250, 11, 57}, /* UXGA 1600x1200@60Hz CVT */ - {148500, 11, 50}, /* FHD 1920x1080@60Hz */ - {154000, 47, 206}, /* WUXGA 1920x1200@60Hz CVT */ - {209250, 31, 100}, /* QXGA 2048x1536@60Hz CVT */ - {268500, 107, 269}, /* WQXGA 2560x1600@60Hz CVT */ - {138530, 63, 307}, /* AUO B116HAN03.0 Panel */ - {141400, 53, 253}, /* AUO B133HTN01.2 Panel */ - }, -}; - -static int edp_clk_init(struct edp_ctrl *ctrl) -{ - struct platform_device *pdev = ctrl->pdev; - int ret; - - ctrl->aux_clk = msm_clk_get(pdev, "core"); - if (IS_ERR(ctrl->aux_clk)) { - ret = PTR_ERR(ctrl->aux_clk); - pr_err("%s: Can't find core clock, %d\n", __func__, ret); - ctrl->aux_clk = NULL; - return ret; - } - - ctrl->pixel_clk = msm_clk_get(pdev, "pixel"); - if (IS_ERR(ctrl->pixel_clk)) { - ret = PTR_ERR(ctrl->pixel_clk); - pr_err("%s: Can't find pixel clock, %d\n", __func__, ret); - ctrl->pixel_clk = NULL; - return ret; - } - - ctrl->ahb_clk = msm_clk_get(pdev, "iface"); - if (IS_ERR(ctrl->ahb_clk)) { - ret = PTR_ERR(ctrl->ahb_clk); - pr_err("%s: Can't find iface clock, %d\n", __func__, ret); - ctrl->ahb_clk = NULL; - return ret; - } - - ctrl->link_clk = msm_clk_get(pdev, "link"); - if (IS_ERR(ctrl->link_clk)) { - ret = PTR_ERR(ctrl->link_clk); - pr_err("%s: Can't find link clock, %d\n", __func__, ret); - ctrl->link_clk = NULL; - return ret; - } - - /* need mdp core clock to receive irq */ - ctrl->mdp_core_clk = msm_clk_get(pdev, "mdp_core"); - if (IS_ERR(ctrl->mdp_core_clk)) { - ret = PTR_ERR(ctrl->mdp_core_clk); - pr_err("%s: Can't find mdp_core clock, %d\n", __func__, ret); - ctrl->mdp_core_clk = NULL; - return ret; - } - - return 0; -} - -static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) -{ - int ret; - - DBG("mask=%x", clk_mask); - /* ahb_clk should be enabled first */ - if (clk_mask & EDP_CLK_MASK_AHB) { - ret = clk_prepare_enable(ctrl->ahb_clk); - if (ret) { - pr_err("%s: Failed to enable ahb clk\n", __func__); - goto f0; - } - } - if (clk_mask & EDP_CLK_MASK_AUX) { - ret = clk_set_rate(ctrl->aux_clk, 19200000); - if (ret) { - pr_err("%s: Failed to set rate aux clk\n", __func__); - goto f1; - } - ret = clk_prepare_enable(ctrl->aux_clk); - if (ret) { - pr_err("%s: Failed to enable aux clk\n", __func__); - goto f1; - } - } - /* Need to set rate and enable link_clk prior to pixel_clk */ - if (clk_mask & EDP_CLK_MASK_LINK) { - DBG("edp->link_clk, set_rate %ld", - (unsigned long)ctrl->link_rate * 27000000); - ret = clk_set_rate(ctrl->link_clk, - (unsigned long)ctrl->link_rate * 27000000); - if (ret) { - pr_err("%s: Failed to set rate to link clk\n", - __func__); - goto f2; - } - - ret = clk_prepare_enable(ctrl->link_clk); - if (ret) { - pr_err("%s: Failed to enable link clk\n", __func__); - goto f2; - } - } - if (clk_mask & EDP_CLK_MASK_PIXEL) { - DBG("edp->pixel_clk, set_rate %ld", - (unsigned long)ctrl->pixel_rate * 1000); - ret = clk_set_rate(ctrl->pixel_clk, - (unsigned long)ctrl->pixel_rate * 1000); - if (ret) { - pr_err("%s: Failed to set rate to pixel clk\n", - __func__); - goto f3; - } - - ret = clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - pr_err("%s: Failed to enable pixel clk\n", __func__); - goto f3; - } - } - if (clk_mask & EDP_CLK_MASK_MDP_CORE) { - ret = clk_prepare_enable(ctrl->mdp_core_clk); - if (ret) { - pr_err("%s: Failed to enable mdp core clk\n", __func__); - goto f4; - } - } - - return 0; - -f4: - if (clk_mask & EDP_CLK_MASK_PIXEL) - clk_disable_unprepare(ctrl->pixel_clk); -f3: - if (clk_mask & EDP_CLK_MASK_LINK) - clk_disable_unprepare(ctrl->link_clk); -f2: - if (clk_mask & EDP_CLK_MASK_AUX) - clk_disable_unprepare(ctrl->aux_clk); -f1: - if (clk_mask & EDP_CLK_MASK_AHB) - clk_disable_unprepare(ctrl->ahb_clk); -f0: - return ret; -} - -static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) -{ - if (clk_mask & EDP_CLK_MASK_MDP_CORE) - clk_disable_unprepare(ctrl->mdp_core_clk); - if (clk_mask & EDP_CLK_MASK_PIXEL) - clk_disable_unprepare(ctrl->pixel_clk); - if (clk_mask & EDP_CLK_MASK_LINK) - clk_disable_unprepare(ctrl->link_clk); - if (clk_mask & EDP_CLK_MASK_AUX) - clk_disable_unprepare(ctrl->aux_clk); - if (clk_mask & EDP_CLK_MASK_AHB) - clk_disable_unprepare(ctrl->ahb_clk); -} - -static int edp_regulator_init(struct edp_ctrl *ctrl) -{ - struct device *dev = &ctrl->pdev->dev; - int ret; - - DBG(""); - ctrl->vdda_vreg = devm_regulator_get(dev, "vdda"); - ret = PTR_ERR_OR_ZERO(ctrl->vdda_vreg); - if (ret) { - pr_err("%s: Could not get vdda reg, ret = %d\n", __func__, - ret); - ctrl->vdda_vreg = NULL; - return ret; - } - ctrl->lvl_vreg = devm_regulator_get(dev, "lvl-vdd"); - ret = PTR_ERR_OR_ZERO(ctrl->lvl_vreg); - if (ret) { - pr_err("%s: Could not get lvl-vdd reg, ret = %d\n", __func__, - ret); - ctrl->lvl_vreg = NULL; - return ret; - } - - return 0; -} - -static int edp_regulator_enable(struct edp_ctrl *ctrl) -{ - int ret; - - ret = regulator_set_load(ctrl->vdda_vreg, VDDA_UA_ON_LOAD); - if (ret < 0) { - pr_err("%s: vdda_vreg set regulator mode failed.\n", __func__); - goto vdda_set_fail; - } - - ret = regulator_enable(ctrl->vdda_vreg); - if (ret) { - pr_err("%s: Failed to enable vdda_vreg regulator.\n", __func__); - goto vdda_enable_fail; - } - - ret = regulator_enable(ctrl->lvl_vreg); - if (ret) { - pr_err("Failed to enable lvl-vdd reg regulator, %d", ret); - goto lvl_enable_fail; - } - - DBG("exit"); - return 0; - -lvl_enable_fail: - regulator_disable(ctrl->vdda_vreg); -vdda_enable_fail: - regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); -vdda_set_fail: - return ret; -} - -static void edp_regulator_disable(struct edp_ctrl *ctrl) -{ - regulator_disable(ctrl->lvl_vreg); - regulator_disable(ctrl->vdda_vreg); - regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); -} - -static int edp_gpio_config(struct edp_ctrl *ctrl) -{ - struct device *dev = &ctrl->pdev->dev; - int ret; - - ctrl->panel_hpd_gpio = devm_gpiod_get(dev, "panel-hpd", GPIOD_IN); - if (IS_ERR(ctrl->panel_hpd_gpio)) { - ret = PTR_ERR(ctrl->panel_hpd_gpio); - ctrl->panel_hpd_gpio = NULL; - pr_err("%s: cannot get panel-hpd-gpios, %d\n", __func__, ret); - return ret; - } - - ctrl->panel_en_gpio = devm_gpiod_get(dev, "panel-en", GPIOD_OUT_LOW); - if (IS_ERR(ctrl->panel_en_gpio)) { - ret = PTR_ERR(ctrl->panel_en_gpio); - ctrl->panel_en_gpio = NULL; - pr_err("%s: cannot get panel-en-gpios, %d\n", __func__, ret); - return ret; - } - - DBG("gpio on"); - - return 0; -} - -static void edp_ctrl_irq_enable(struct edp_ctrl *ctrl, int enable) -{ - unsigned long flags; - - DBG("%d", enable); - spin_lock_irqsave(&ctrl->irq_lock, flags); - if (enable) { - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); - } else { - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); - } - spin_unlock_irqrestore(&ctrl->irq_lock, flags); - DBG("exit"); -} - -static void edp_fill_link_cfg(struct edp_ctrl *ctrl) -{ - u32 prate; - u32 lrate; - u32 bpp; - u8 max_lane = drm_dp_max_lane_count(ctrl->dpcd); - u8 lane; - - prate = ctrl->pixel_rate; - bpp = ctrl->color_depth * 3; - - /* - * By default, use the maximum link rate and minimum lane count, - * so that we can do rate down shift during link training. - */ - ctrl->link_rate = ctrl->dpcd[DP_MAX_LINK_RATE]; - - prate *= bpp; - prate /= 8; /* in kByte */ - - lrate = 270000; /* in kHz */ - lrate *= ctrl->link_rate; - lrate /= 10; /* in kByte, 10 bits --> 8 bits */ - - for (lane = 1; lane <= max_lane; lane <<= 1) { - if (lrate >= prate) - break; - lrate <<= 1; - } - - ctrl->lane_cnt = lane; - DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); -} - -static void edp_config_ctrl(struct edp_ctrl *ctrl) -{ - u32 data; - enum edp_color_depth depth; - - data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1); - - if (drm_dp_enhanced_frame_cap(ctrl->dpcd)) - data |= EDP_CONFIGURATION_CTRL_ENHANCED_FRAMING; - - depth = EDP_6BIT; - if (ctrl->color_depth == 8) - depth = EDP_8BIT; - - data |= EDP_CONFIGURATION_CTRL_COLOR(depth); - - if (!ctrl->interlaced) /* progressive */ - data |= EDP_CONFIGURATION_CTRL_PROGRESSIVE; - - data |= (EDP_CONFIGURATION_CTRL_SYNC_CLK | - EDP_CONFIGURATION_CTRL_STATIC_MVID); - - edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); -} - -static void edp_state_ctrl(struct edp_ctrl *ctrl, u32 state) -{ - edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); - /* Make sure H/W status is set */ - wmb(); -} - -static int edp_lane_set_write(struct edp_ctrl *ctrl, - u8 voltage_level, u8 pre_emphasis_level) -{ - int i; - u8 buf[4]; - - if (voltage_level >= DPCD_LINK_VOLTAGE_MAX) - voltage_level |= 0x04; - - if (pre_emphasis_level >= DPCD_LINK_PRE_EMPHASIS_MAX) - pre_emphasis_level |= 0x04; - - pre_emphasis_level <<= 3; - - for (i = 0; i < 4; i++) - buf[i] = voltage_level | pre_emphasis_level; - - DBG("%s: p|v=0x%x", __func__, voltage_level | pre_emphasis_level); - if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { - pr_err("%s: Set sw/pe to panel failed\n", __func__); - return -ENOLINK; - } - - return 0; -} - -static int edp_train_pattern_set_write(struct edp_ctrl *ctrl, u8 pattern) -{ - u8 p = pattern; - - DBG("pattern=%x", p); - if (drm_dp_dpcd_write(ctrl->drm_aux, - DP_TRAINING_PATTERN_SET, &p, 1) < 1) { - pr_err("%s: Set training pattern to panel failed\n", __func__); - return -ENOLINK; - } - - return 0; -} - -static void edp_sink_train_set_adjust(struct edp_ctrl *ctrl, - const u8 *link_status) -{ - int i; - u8 max = 0; - u8 data; - - /* use the max level across lanes */ - for (i = 0; i < ctrl->lane_cnt; i++) { - data = drm_dp_get_adjust_request_voltage(link_status, i); - DBG("lane=%d req_voltage_swing=0x%x", i, data); - if (max < data) - max = data; - } - - ctrl->v_level = max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; - - /* use the max level across lanes */ - max = 0; - for (i = 0; i < ctrl->lane_cnt; i++) { - data = drm_dp_get_adjust_request_pre_emphasis(link_status, i); - DBG("lane=%d req_pre_emphasis=0x%x", i, data); - if (max < data) - max = data; - } - - ctrl->p_level = max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; - DBG("v_level=%d, p_level=%d", ctrl->v_level, ctrl->p_level); -} - -static void edp_host_train_set(struct edp_ctrl *ctrl, u32 train) -{ - int cnt = 10; - u32 data; - u32 shift = train - 1; - - DBG("train=%d", train); - - edp_state_ctrl(ctrl, EDP_STATE_CTRL_TRAIN_PATTERN_1 << shift); - while (--cnt) { - data = edp_read(ctrl->base + REG_EDP_MAINLINK_READY); - if (data & (EDP_MAINLINK_READY_TRAIN_PATTERN_1_READY << shift)) - break; - } - - if (cnt == 0) - pr_err("%s: set link_train=%d failed\n", __func__, train); -} - -static const u8 vm_pre_emphasis[4][4] = { - {0x03, 0x06, 0x09, 0x0C}, /* pe0, 0 db */ - {0x03, 0x06, 0x09, 0xFF}, /* pe1, 3.5 db */ - {0x03, 0x06, 0xFF, 0xFF}, /* pe2, 6.0 db */ - {0x03, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ -}; - -/* voltage swing, 0.2v and 1.0v are not support */ -static const u8 vm_voltage_swing[4][4] = { - {0x14, 0x18, 0x1A, 0x1E}, /* sw0, 0.4v */ - {0x18, 0x1A, 0x1E, 0xFF}, /* sw1, 0.6 v */ - {0x1A, 0x1E, 0xFF, 0xFF}, /* sw1, 0.8 v */ - {0x1E, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ -}; - -static int edp_voltage_pre_emphasise_set(struct edp_ctrl *ctrl) -{ - u32 value0; - u32 value1; - - DBG("v=%d p=%d", ctrl->v_level, ctrl->p_level); - - value0 = vm_pre_emphasis[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; - value1 = vm_voltage_swing[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; - - /* Configure host and panel only if both values are allowed */ - if (value0 != 0xFF && value1 != 0xFF) { - msm_edp_phy_vm_pe_cfg(ctrl->phy, value0, value1); - return edp_lane_set_write(ctrl, ctrl->v_level, ctrl->p_level); - } - - return -EINVAL; -} - -static int edp_start_link_train_1(struct edp_ctrl *ctrl) -{ - u8 link_status[DP_LINK_STATUS_SIZE]; - u8 old_v_level; - int tries; - int ret; - int rlen; - - DBG(""); - - edp_host_train_set(ctrl, DP_TRAINING_PATTERN_1); - ret = edp_voltage_pre_emphasise_set(ctrl); - if (ret) - return ret; - ret = edp_train_pattern_set_write(ctrl, - DP_TRAINING_PATTERN_1 | DP_RECOVERED_CLOCK_OUT_EN); - if (ret) - return ret; - - tries = 0; - old_v_level = ctrl->v_level; - while (1) { - drm_dp_link_train_clock_recovery_delay(ctrl->drm_aux, ctrl->dpcd); - - rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); - if (rlen < DP_LINK_STATUS_SIZE) { - pr_err("%s: read link status failed\n", __func__); - return -ENOLINK; - } - if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { - ret = 0; - break; - } - - if (ctrl->v_level == DPCD_LINK_VOLTAGE_MAX) { - ret = -1; - break; - } - - if (old_v_level == ctrl->v_level) { - tries++; - if (tries >= 5) { - ret = -1; - break; - } - } else { - tries = 0; - old_v_level = ctrl->v_level; - } - - edp_sink_train_set_adjust(ctrl, link_status); - ret = edp_voltage_pre_emphasise_set(ctrl); - if (ret) - return ret; - } - - return ret; -} - -static int edp_start_link_train_2(struct edp_ctrl *ctrl) -{ - u8 link_status[DP_LINK_STATUS_SIZE]; - int tries = 0; - int ret; - int rlen; - - DBG(""); - - edp_host_train_set(ctrl, DP_TRAINING_PATTERN_2); - ret = edp_voltage_pre_emphasise_set(ctrl); - if (ret) - return ret; - - ret = edp_train_pattern_set_write(ctrl, - DP_TRAINING_PATTERN_2 | DP_RECOVERED_CLOCK_OUT_EN); - if (ret) - return ret; - - while (1) { - drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); - - rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); - if (rlen < DP_LINK_STATUS_SIZE) { - pr_err("%s: read link status failed\n", __func__); - return -ENOLINK; - } - if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) { - ret = 0; - break; - } - - tries++; - if (tries > 10) { - ret = -1; - break; - } - - edp_sink_train_set_adjust(ctrl, link_status); - ret = edp_voltage_pre_emphasise_set(ctrl); - if (ret) - return ret; - } - - return ret; -} - -static int edp_link_rate_down_shift(struct edp_ctrl *ctrl) -{ - u32 prate, lrate, bpp; - u8 rate, lane, max_lane; - int changed = 0; - - rate = ctrl->link_rate; - lane = ctrl->lane_cnt; - max_lane = drm_dp_max_lane_count(ctrl->dpcd); - - bpp = ctrl->color_depth * 3; - prate = ctrl->pixel_rate; - prate *= bpp; - prate /= 8; /* in kByte */ - - if (rate > DP_LINK_BW_1_62 && rate <= EDP_LINK_BW_MAX) { - rate -= 4; /* reduce rate */ - changed++; - } - - if (changed) { - if (lane >= 1 && lane < max_lane) - lane <<= 1; /* increase lane */ - - lrate = 270000; /* in kHz */ - lrate *= rate; - lrate /= 10; /* kByte, 10 bits --> 8 bits */ - lrate *= lane; - - DBG("new lrate=%u prate=%u(kHz) rate=%d lane=%d p=%u b=%d", - lrate, prate, rate, lane, - ctrl->pixel_rate, - bpp); - - if (lrate > prate) { - ctrl->link_rate = rate; - ctrl->lane_cnt = lane; - DBG("new rate=%d %d", rate, lane); - return 0; - } - } - - return -EINVAL; -} - -static int edp_clear_training_pattern(struct edp_ctrl *ctrl) -{ - int ret; - - ret = edp_train_pattern_set_write(ctrl, 0); - - drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); - - return ret; -} - -static int edp_do_link_train(struct edp_ctrl *ctrl) -{ - u8 values[2]; - int ret; - - DBG(""); - /* - * Set the current link rate and lane cnt to panel. They may have been - * adjusted and the values are different from them in DPCD CAP - */ - values[0] = ctrl->lane_cnt; - values[1] = ctrl->link_rate; - - if (drm_dp_enhanced_frame_cap(ctrl->dpcd)) - values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; - - if (drm_dp_dpcd_write(ctrl->drm_aux, DP_LINK_BW_SET, values, - sizeof(values)) < 0) - return EDP_TRAIN_FAIL; - - ctrl->v_level = 0; /* start from default level */ - ctrl->p_level = 0; - - edp_state_ctrl(ctrl, 0); - if (edp_clear_training_pattern(ctrl)) - return EDP_TRAIN_FAIL; - - ret = edp_start_link_train_1(ctrl); - if (ret < 0) { - if (edp_link_rate_down_shift(ctrl) == 0) { - DBG("link reconfig"); - ret = EDP_TRAIN_RECONFIG; - goto clear; - } else { - pr_err("%s: Training 1 failed", __func__); - ret = EDP_TRAIN_FAIL; - goto clear; - } - } - DBG("Training 1 completed successfully"); - - edp_state_ctrl(ctrl, 0); - if (edp_clear_training_pattern(ctrl)) - return EDP_TRAIN_FAIL; - - ret = edp_start_link_train_2(ctrl); - if (ret < 0) { - if (edp_link_rate_down_shift(ctrl) == 0) { - DBG("link reconfig"); - ret = EDP_TRAIN_RECONFIG; - goto clear; - } else { - pr_err("%s: Training 2 failed", __func__); - ret = EDP_TRAIN_FAIL; - goto clear; - } - } - DBG("Training 2 completed successfully"); - - edp_state_ctrl(ctrl, EDP_STATE_CTRL_SEND_VIDEO); -clear: - edp_clear_training_pattern(ctrl); - - return ret; -} - -static void edp_clock_synchrous(struct edp_ctrl *ctrl, int sync) -{ - u32 data; - enum edp_color_depth depth; - - data = edp_read(ctrl->base + REG_EDP_MISC1_MISC0); - - if (sync) - data |= EDP_MISC1_MISC0_SYNC; - else - data &= ~EDP_MISC1_MISC0_SYNC; - - /* only legacy rgb mode supported */ - depth = EDP_6BIT; /* Default */ - if (ctrl->color_depth == 8) - depth = EDP_8BIT; - else if (ctrl->color_depth == 10) - depth = EDP_10BIT; - else if (ctrl->color_depth == 12) - depth = EDP_12BIT; - else if (ctrl->color_depth == 16) - depth = EDP_16BIT; - - data |= EDP_MISC1_MISC0_COLOR(depth); - - edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); -} - -static int edp_sw_mvid_nvid(struct edp_ctrl *ctrl, u32 m, u32 n) -{ - u32 n_multi, m_multi = 5; - - if (ctrl->link_rate == DP_LINK_BW_1_62) { - n_multi = 1; - } else if (ctrl->link_rate == DP_LINK_BW_2_7) { - n_multi = 2; - } else { - pr_err("%s: Invalid link rate, %d\n", __func__, - ctrl->link_rate); - return -EINVAL; - } - - edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); - edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); - - return 0; -} - -static void edp_mainlink_ctrl(struct edp_ctrl *ctrl, int enable) -{ - u32 data = 0; - - edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); - /* Make sure fully reset */ - wmb(); - usleep_range(500, 1000); - - if (enable) - data |= EDP_MAINLINK_CTRL_ENABLE; - - edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, data); -} - -static void edp_ctrl_phy_aux_enable(struct edp_ctrl *ctrl, int enable) -{ - if (enable) { - edp_regulator_enable(ctrl); - edp_clk_enable(ctrl, EDP_CLK_MASK_AUX_CHAN); - msm_edp_phy_ctrl(ctrl->phy, 1); - msm_edp_aux_ctrl(ctrl->aux, 1); - gpiod_set_value(ctrl->panel_en_gpio, 1); - } else { - gpiod_set_value(ctrl->panel_en_gpio, 0); - msm_edp_aux_ctrl(ctrl->aux, 0); - msm_edp_phy_ctrl(ctrl->phy, 0); - edp_clk_disable(ctrl, EDP_CLK_MASK_AUX_CHAN); - edp_regulator_disable(ctrl); - } -} - -static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, int enable) -{ - u32 m, n; - - if (enable) { - /* Enable link channel clocks */ - edp_clk_enable(ctrl, EDP_CLK_MASK_LINK_CHAN); - - msm_edp_phy_lane_power_ctrl(ctrl->phy, true, ctrl->lane_cnt); - - msm_edp_phy_vm_pe_init(ctrl->phy); - - /* Make sure phy is programed */ - wmb(); - msm_edp_phy_ready(ctrl->phy); - - edp_config_ctrl(ctrl); - msm_edp_ctrl_pixel_clock_valid(ctrl, ctrl->pixel_rate, &m, &n); - edp_sw_mvid_nvid(ctrl, m, n); - edp_mainlink_ctrl(ctrl, 1); - } else { - edp_mainlink_ctrl(ctrl, 0); - - msm_edp_phy_lane_power_ctrl(ctrl->phy, false, 0); - edp_clk_disable(ctrl, EDP_CLK_MASK_LINK_CHAN); - } -} - -static int edp_ctrl_training(struct edp_ctrl *ctrl) -{ - int ret; - - /* Do link training only when power is on */ - if (!ctrl->power_on) - return -EINVAL; - -train_start: - ret = edp_do_link_train(ctrl); - if (ret == EDP_TRAIN_RECONFIG) { - /* Re-configure main link */ - edp_ctrl_irq_enable(ctrl, 0); - edp_ctrl_link_enable(ctrl, 0); - msm_edp_phy_ctrl(ctrl->phy, 0); - - /* Make sure link is fully disabled */ - wmb(); - usleep_range(500, 1000); - - msm_edp_phy_ctrl(ctrl->phy, 1); - edp_ctrl_link_enable(ctrl, 1); - edp_ctrl_irq_enable(ctrl, 1); - goto train_start; - } - - return ret; -} - -static void edp_ctrl_on_worker(struct work_struct *work) -{ - struct edp_ctrl *ctrl = container_of( - work, struct edp_ctrl, on_work); - u8 value; - int ret; - - mutex_lock(&ctrl->dev_mutex); - - if (ctrl->power_on) { - DBG("already on"); - goto unlock_ret; - } - - edp_ctrl_phy_aux_enable(ctrl, 1); - edp_ctrl_link_enable(ctrl, 1); - - edp_ctrl_irq_enable(ctrl, 1); - - /* DP_SET_POWER register is only available on DPCD v1.1 and later */ - if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) { - ret = drm_dp_dpcd_readb(ctrl->drm_aux, DP_SET_POWER, &value); - if (ret < 0) - goto fail; - - value &= ~DP_SET_POWER_MASK; - value |= DP_SET_POWER_D0; - - ret = drm_dp_dpcd_writeb(ctrl->drm_aux, DP_SET_POWER, value); - if (ret < 0) - goto fail; - - /* - * According to the DP 1.1 specification, a "Sink Device must - * exit the power saving state within 1 ms" (Section 2.5.3.1, - * Table 5-52, "Sink Control Field" (register 0x600). - */ - usleep_range(1000, 2000); - } - - ctrl->power_on = true; - - /* Start link training */ - ret = edp_ctrl_training(ctrl); - if (ret != EDP_TRAIN_SUCCESS) - goto fail; - - DBG("DONE"); - goto unlock_ret; - -fail: - edp_ctrl_irq_enable(ctrl, 0); - edp_ctrl_link_enable(ctrl, 0); - edp_ctrl_phy_aux_enable(ctrl, 0); - ctrl->power_on = false; -unlock_ret: - mutex_unlock(&ctrl->dev_mutex); -} - -static void edp_ctrl_off_worker(struct work_struct *work) -{ - struct edp_ctrl *ctrl = container_of( - work, struct edp_ctrl, off_work); - unsigned long time_left; - - mutex_lock(&ctrl->dev_mutex); - - if (!ctrl->power_on) { - DBG("already off"); - goto unlock_ret; - } - - reinit_completion(&ctrl->idle_comp); - edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); - - time_left = wait_for_completion_timeout(&ctrl->idle_comp, - msecs_to_jiffies(500)); - if (!time_left) - DBG("%s: idle pattern timedout\n", __func__); - - edp_state_ctrl(ctrl, 0); - - /* DP_SET_POWER register is only available on DPCD v1.1 and later */ - if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) { - u8 value; - int ret; - - ret = drm_dp_dpcd_readb(ctrl->drm_aux, DP_SET_POWER, &value); - if (ret > 0) { - value &= ~DP_SET_POWER_MASK; - value |= DP_SET_POWER_D3; - - drm_dp_dpcd_writeb(ctrl->drm_aux, DP_SET_POWER, value); - } - } - - edp_ctrl_irq_enable(ctrl, 0); - - edp_ctrl_link_enable(ctrl, 0); - - edp_ctrl_phy_aux_enable(ctrl, 0); - - ctrl->power_on = false; - -unlock_ret: - mutex_unlock(&ctrl->dev_mutex); -} - -irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl) -{ - u32 isr1, isr2, mask1, mask2; - u32 ack; - - DBG(""); - spin_lock(&ctrl->irq_lock); - isr1 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_1); - isr2 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_2); - - mask1 = isr1 & EDP_INTR_MASK1; - mask2 = isr2 & EDP_INTR_MASK2; - - isr1 &= ~mask1; /* remove masks bit */ - isr2 &= ~mask2; - - DBG("isr=%x mask=%x isr2=%x mask2=%x", - isr1, mask1, isr2, mask2); - - ack = isr1 & EDP_INTR_STATUS1; - ack <<= 1; /* ack bits */ - ack |= mask1; - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, ack); - - ack = isr2 & EDP_INTR_STATUS2; - ack <<= 1; /* ack bits */ - ack |= mask2; - edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, ack); - spin_unlock(&ctrl->irq_lock); - - if (isr1 & EDP_INTERRUPT_REG_1_HPD) - DBG("edp_hpd"); - - if (isr2 & EDP_INTERRUPT_REG_2_READY_FOR_VIDEO) - DBG("edp_video_ready"); - - if (isr2 & EDP_INTERRUPT_REG_2_IDLE_PATTERNs_SENT) { - DBG("idle_patterns_sent"); - complete(&ctrl->idle_comp); - } - - msm_edp_aux_irq(ctrl->aux, isr1); - - return IRQ_HANDLED; -} - -void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on) -{ - if (on) - queue_work(ctrl->workqueue, &ctrl->on_work); - else - queue_work(ctrl->workqueue, &ctrl->off_work); -} - -int msm_edp_ctrl_init(struct msm_edp *edp) -{ - struct edp_ctrl *ctrl = NULL; - struct device *dev; - int ret; - - if (!edp) { - pr_err("%s: edp is NULL!\n", __func__); - return -EINVAL; - } - - dev = &edp->pdev->dev; - ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) - return -ENOMEM; - - edp->ctrl = ctrl; - ctrl->pdev = edp->pdev; - - ctrl->base = msm_ioremap(ctrl->pdev, "edp", "eDP"); - if (IS_ERR(ctrl->base)) - return PTR_ERR(ctrl->base); - - /* Get regulator, clock, gpio, pwm */ - ret = edp_regulator_init(ctrl); - if (ret) { - pr_err("%s:regulator init fail\n", __func__); - return ret; - } - ret = edp_clk_init(ctrl); - if (ret) { - pr_err("%s:clk init fail\n", __func__); - return ret; - } - ret = edp_gpio_config(ctrl); - if (ret) { - pr_err("%s:failed to configure GPIOs: %d", __func__, ret); - return ret; - } - - /* Init aux and phy */ - ctrl->aux = msm_edp_aux_init(edp, ctrl->base, &ctrl->drm_aux); - if (!ctrl->aux || !ctrl->drm_aux) { - pr_err("%s:failed to init aux\n", __func__); - return -ENOMEM; - } - - ctrl->phy = msm_edp_phy_init(dev, ctrl->base); - if (!ctrl->phy) { - pr_err("%s:failed to init phy\n", __func__); - ret = -ENOMEM; - goto err_destory_aux; - } - - spin_lock_init(&ctrl->irq_lock); - mutex_init(&ctrl->dev_mutex); - init_completion(&ctrl->idle_comp); - - /* setup workqueue */ - ctrl->workqueue = alloc_ordered_workqueue("edp_drm_work", 0); - INIT_WORK(&ctrl->on_work, edp_ctrl_on_worker); - INIT_WORK(&ctrl->off_work, edp_ctrl_off_worker); - - return 0; - -err_destory_aux: - msm_edp_aux_destroy(dev, ctrl->aux); - ctrl->aux = NULL; - return ret; -} - -void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl) -{ - if (!ctrl) - return; - - if (ctrl->workqueue) { - destroy_workqueue(ctrl->workqueue); - ctrl->workqueue = NULL; - } - - if (ctrl->aux) { - msm_edp_aux_destroy(&ctrl->pdev->dev, ctrl->aux); - ctrl->aux = NULL; - } - - kfree(ctrl->edid); - ctrl->edid = NULL; - - mutex_destroy(&ctrl->dev_mutex); -} - -bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl) -{ - mutex_lock(&ctrl->dev_mutex); - DBG("connect status = %d", ctrl->edp_connected); - if (ctrl->edp_connected) { - mutex_unlock(&ctrl->dev_mutex); - return true; - } - - if (!ctrl->power_on) { - edp_ctrl_phy_aux_enable(ctrl, 1); - edp_ctrl_irq_enable(ctrl, 1); - } - - if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, - DP_RECEIVER_CAP_SIZE) < DP_RECEIVER_CAP_SIZE) { - pr_err("%s: AUX channel is NOT ready\n", __func__); - memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); - } else { - ctrl->edp_connected = true; - } - - if (!ctrl->power_on) { - edp_ctrl_irq_enable(ctrl, 0); - edp_ctrl_phy_aux_enable(ctrl, 0); - } - - DBG("exit: connect status=%d", ctrl->edp_connected); - - mutex_unlock(&ctrl->dev_mutex); - - return ctrl->edp_connected; -} - -int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl, - struct drm_connector *connector, struct edid **edid) -{ - mutex_lock(&ctrl->dev_mutex); - - if (ctrl->edid) { - if (edid) { - DBG("Just return edid buffer"); - *edid = ctrl->edid; - } - goto unlock_ret; - } - - if (!ctrl->power_on) { - edp_ctrl_phy_aux_enable(ctrl, 1); - edp_ctrl_irq_enable(ctrl, 1); - } - - /* Initialize link rate as panel max link rate */ - ctrl->link_rate = ctrl->dpcd[DP_MAX_LINK_RATE]; - - ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc); - if (!ctrl->edid) { - pr_err("%s: edid read fail\n", __func__); - goto disable_ret; - } - - if (edid) - *edid = ctrl->edid; - -disable_ret: - if (!ctrl->power_on) { - edp_ctrl_irq_enable(ctrl, 0); - edp_ctrl_phy_aux_enable(ctrl, 0); - } -unlock_ret: - mutex_unlock(&ctrl->dev_mutex); - return 0; -} - -int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl, - const struct drm_display_mode *mode, - const struct drm_display_info *info) -{ - u32 hstart_from_sync, vstart_from_sync; - u32 data; - int ret = 0; - - mutex_lock(&ctrl->dev_mutex); - /* - * Need to keep color depth, pixel rate and - * interlaced information in ctrl context - */ - ctrl->color_depth = info->bpc; - ctrl->pixel_rate = mode->clock; - ctrl->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); - - /* Fill initial link config based on passed in timing */ - edp_fill_link_cfg(ctrl); - - if (edp_clk_enable(ctrl, EDP_CLK_MASK_AHB)) { - pr_err("%s, fail to prepare enable ahb clk\n", __func__); - ret = -EINVAL; - goto unlock_ret; - } - edp_clock_synchrous(ctrl, 1); - - /* Configure eDP timing to HW */ - edp_write(ctrl->base + REG_EDP_TOTAL_HOR_VER, - EDP_TOTAL_HOR_VER_HORIZ(mode->htotal) | - EDP_TOTAL_HOR_VER_VERT(mode->vtotal)); - - vstart_from_sync = mode->vtotal - mode->vsync_start; - hstart_from_sync = mode->htotal - mode->hsync_start; - edp_write(ctrl->base + REG_EDP_START_HOR_VER_FROM_SYNC, - EDP_START_HOR_VER_FROM_SYNC_HORIZ(hstart_from_sync) | - EDP_START_HOR_VER_FROM_SYNC_VERT(vstart_from_sync)); - - data = EDP_HSYNC_VSYNC_WIDTH_POLARITY_VERT( - mode->vsync_end - mode->vsync_start); - data |= EDP_HSYNC_VSYNC_WIDTH_POLARITY_HORIZ( - mode->hsync_end - mode->hsync_start); - if (mode->flags & DRM_MODE_FLAG_NVSYNC) - data |= EDP_HSYNC_VSYNC_WIDTH_POLARITY_NVSYNC; - if (mode->flags & DRM_MODE_FLAG_NHSYNC) - data |= EDP_HSYNC_VSYNC_WIDTH_POLARITY_NHSYNC; - edp_write(ctrl->base + REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY, data); - - edp_write(ctrl->base + REG_EDP_ACTIVE_HOR_VER, - EDP_ACTIVE_HOR_VER_HORIZ(mode->hdisplay) | - EDP_ACTIVE_HOR_VER_VERT(mode->vdisplay)); - - edp_clk_disable(ctrl, EDP_CLK_MASK_AHB); - -unlock_ret: - mutex_unlock(&ctrl->dev_mutex); - return ret; -} - -bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl, - u32 pixel_rate, u32 *pm, u32 *pn) -{ - const struct edp_pixel_clk_div *divs; - u32 err = 1; /* 1% error tolerance */ - u32 clk_err; - int i; - - if (ctrl->link_rate == DP_LINK_BW_1_62) { - divs = clk_divs[0]; - } else if (ctrl->link_rate == DP_LINK_BW_2_7) { - divs = clk_divs[1]; - } else { - pr_err("%s: Invalid link rate,%d\n", __func__, ctrl->link_rate); - return false; - } - - for (i = 0; i < EDP_PIXEL_CLK_NUM; i++) { - clk_err = abs(divs[i].rate - pixel_rate); - if ((divs[i].rate * err / 100) >= clk_err) { - if (pm) - *pm = divs[i].m; - if (pn) - *pn = divs[i].n; - return true; - } - } - - DBG("pixel clock %d(kHz) not supported", pixel_rate); - - return false; -} - diff --git a/drivers/gpu/drm/msm/edp/edp_phy.c b/drivers/gpu/drm/msm/edp/edp_phy.c deleted file mode 100644 index fcaf7b7ecdd2..000000000000 --- a/drivers/gpu/drm/msm/edp/edp_phy.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "edp.h" -#include "edp.xml.h" - -#define EDP_MAX_LANE 4 - -struct edp_phy { - void __iomem *base; -}; - -bool msm_edp_phy_ready(struct edp_phy *phy) -{ - u32 status; - int cnt = 100; - - while (--cnt) { - status = edp_read(phy->base + - REG_EDP_PHY_GLB_PHY_STATUS); - if (status & 0x01) - break; - usleep_range(500, 1000); - } - - if (cnt == 0) { - pr_err("%s: PHY NOT ready\n", __func__); - return false; - } else { - return true; - } -} - -void msm_edp_phy_ctrl(struct edp_phy *phy, int enable) -{ - DBG("enable=%d", enable); - if (enable) { - /* Reset */ - edp_write(phy->base + REG_EDP_PHY_CTRL, - EDP_PHY_CTRL_SW_RESET | EDP_PHY_CTRL_SW_RESET_PLL); - /* Make sure fully reset */ - wmb(); - usleep_range(500, 1000); - edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); - edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); - edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); - } else { - edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); - } -} - -/* voltage mode and pre emphasis cfg */ -void msm_edp_phy_vm_pe_init(struct edp_phy *phy) -{ - edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); - edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64); - edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c); -} - -void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1) -{ - edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0); - edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1); -} - -void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane) -{ - u32 i; - u32 data; - - if (up) - data = 0; /* power up */ - else - data = 0x7; /* power down */ - - for (i = 0; i < max_lane; i++) - edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); - - /* power down unused lane */ - data = 0x7; /* power down */ - for (i = max_lane; i < EDP_MAX_LANE; i++) - edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data); -} - -void *msm_edp_phy_init(struct device *dev, void __iomem *regbase) -{ - struct edp_phy *phy = NULL; - - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) - return NULL; - - phy->base = regbase; - return phy; -} - |