diff options
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 9a3546f8b42b..947d6e4a01f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -212,22 +212,22 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) *flags |= AMD_CG_SUPPORT_BIF_LS; } -static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); } -static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); } -static u32 get_pcie_index_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); } -static u32 get_pcie_data_offset(struct amdgpu_device *adev) +static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); } @@ -248,10 +248,10 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { }; const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { - .get_hdp_flush_req_offset = get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = get_hdp_flush_done_offset, - .get_pcie_index_offset = get_pcie_index_offset, - .get_pcie_data_offset = get_pcie_data_offset, + .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, }; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index ce869f37a382..851f58e0b9d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -182,22 +182,22 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } -static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); } -static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); } -static u32 get_pcie_index_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); } -static u32 get_pcie_data_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); } @@ -218,9 +218,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { }; const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { - .get_hdp_flush_req_offset = get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = get_hdp_flush_done_offset, - .get_pcie_index_offset = get_pcie_index_offset, - .get_pcie_data_offset = get_pcie_data_offset, + .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, }; |