diff options
Diffstat (limited to 'drivers/pinctrl/sh-pfc/pfc-sh73a0.c')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 172 |
1 files changed, 76 insertions, 96 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c index 31f7d0e04aaa..7e278a97e411 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c @@ -31,32 +31,32 @@ #include "core.h" #include "sh_pfc.h" -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ - PORT_10(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ - PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ - PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ - PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ - PORT_1(fn, pfx##118, sfx), \ - PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ - PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ - PORT_10(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ - PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ - PORT_1(fn, pfx##164, sfx), \ - PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ - PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ - PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ - PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ - PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ - PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ - PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ - PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ - PORT_1(fn, pfx##282, sfx), \ - PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ - PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \ + PORT_10(100, fn, pfx##10, sfx), \ + PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \ + PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \ + PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \ + PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \ + PORT_1(118, fn, pfx##118, sfx), \ + PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \ + PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \ + PORT_10(150, fn, pfx##15, sfx), \ + PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \ + PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \ + PORT_1(164, fn, pfx##164, sfx), \ + PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \ + PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \ + PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \ + PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \ + PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \ + PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \ + PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \ + PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \ + PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \ + PORT_1(282, fn, pfx##282, sfx), \ + PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \ + PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx) enum { PINMUX_RESERVED = 0, @@ -466,12 +466,9 @@ enum { PINMUX_MARK_END, }; -#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) - -static const pinmux_enum_t pinmux_data[] = { +static const u16 pinmux_data[] = { /* specify valid pin states for each pin in GPIO mode */ - PINMUX_DATA_GP_ALL(), + PINMUX_DATA_ALL(), /* Table 25-1 (Function 0-7) */ PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), @@ -1160,13 +1157,6 @@ static const pinmux_enum_t pinmux_data[] = { PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), }; -#define SH73A0_PIN(pin, cfgs) \ - { \ - .name = __stringify(PORT##pin), \ - .enum_id = PORT##pin##_DATA, \ - .configs = cfgs, \ - } - #define __I (SH_PFC_PIN_CFG_INPUT) #define __O (SH_PFC_PIN_CFG_OUTPUT) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT) @@ -1174,14 +1164,20 @@ static const pinmux_enum_t pinmux_data[] = { #define __PU (SH_PFC_PIN_CFG_PULL_UP) #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP) -#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD) -#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU) -#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD) -#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO) -#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD) -#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU) -#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD) -#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O) +#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD) +#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU) +#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD) +#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO) +#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD) +#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU) +#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) +#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) + +/* Pin numbers for pins without a corresponding GPIO port number are computed + * from the row and column numbers with a 1000 offset to avoid collisions with + * GPIO port numbers. + */ +#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) static struct sh_pfc_pin pinmux_pins[] = { /* Table 25-1 (I/O and Pull U/D) */ @@ -1454,21 +1450,11 @@ static struct sh_pfc_pin pinmux_pins[] = { SH73A0_PIN_O(307), SH73A0_PIN_I_PU(308), SH73A0_PIN_O(309), -}; -static const struct pinmux_range pinmux_ranges[] = { - {.begin = 0, .end = 118,}, - {.begin = 128, .end = 164,}, - {.begin = 192, .end = 282,}, - {.begin = 288, .end = 309,}, + /* Pins not associated with a GPIO port */ + SH_PFC_PIN_NAMED(6, 26, F26), }; -/* Pin numbers for pins without a corresponding GPIO port number are computed - * from the row and column numbers with a 1000 offset to avoid collisions with - * GPIO port numbers. - */ -#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) - /* - BSC -------------------------------------------------------------------- */ static const unsigned int bsc_data_0_7_pins[] = { /* D[0:7] */ @@ -3674,43 +3660,39 @@ static const struct pinmux_data_reg pinmux_data_regs[] = { { }, }; -/* External IRQ pins mapped at IRQPIN_BASE */ -#define EXT_IRQ16L(n) irq_pin(n) -#define EXT_IRQ16H(n) irq_pin(n) - static const struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), 9), - PINMUX_IRQ(EXT_IRQ16L(1), 10), - PINMUX_IRQ(EXT_IRQ16L(0), 11), - PINMUX_IRQ(EXT_IRQ16H(18), 13), - PINMUX_IRQ(EXT_IRQ16H(20), 14), - PINMUX_IRQ(EXT_IRQ16H(21), 15), - PINMUX_IRQ(EXT_IRQ16H(31), 26), - PINMUX_IRQ(EXT_IRQ16H(30), 27), - PINMUX_IRQ(EXT_IRQ16H(29), 28), - PINMUX_IRQ(EXT_IRQ16H(22), 40), - PINMUX_IRQ(EXT_IRQ16H(23), 53), - PINMUX_IRQ(EXT_IRQ16L(10), 54), - PINMUX_IRQ(EXT_IRQ16L(9), 56), - PINMUX_IRQ(EXT_IRQ16H(26), 115), - PINMUX_IRQ(EXT_IRQ16H(27), 116), - PINMUX_IRQ(EXT_IRQ16H(28), 117), - PINMUX_IRQ(EXT_IRQ16H(24), 118), - PINMUX_IRQ(EXT_IRQ16L(6), 147), - PINMUX_IRQ(EXT_IRQ16L(2), 149), - PINMUX_IRQ(EXT_IRQ16L(7), 150), - PINMUX_IRQ(EXT_IRQ16L(12), 156), - PINMUX_IRQ(EXT_IRQ16L(4), 159), - PINMUX_IRQ(EXT_IRQ16H(25), 164), - PINMUX_IRQ(EXT_IRQ16L(8), 223), - PINMUX_IRQ(EXT_IRQ16L(3), 224), - PINMUX_IRQ(EXT_IRQ16L(5), 227), - PINMUX_IRQ(EXT_IRQ16H(17), 234), - PINMUX_IRQ(EXT_IRQ16L(11), 238), - PINMUX_IRQ(EXT_IRQ16L(13), 239), - PINMUX_IRQ(EXT_IRQ16H(16), 249), - PINMUX_IRQ(EXT_IRQ16L(14), 251), - PINMUX_IRQ(EXT_IRQ16L(9), 308), + PINMUX_IRQ(irq_pin(19), 9), + PINMUX_IRQ(irq_pin(1), 10), + PINMUX_IRQ(irq_pin(0), 11), + PINMUX_IRQ(irq_pin(18), 13), + PINMUX_IRQ(irq_pin(20), 14), + PINMUX_IRQ(irq_pin(21), 15), + PINMUX_IRQ(irq_pin(31), 26), + PINMUX_IRQ(irq_pin(30), 27), + PINMUX_IRQ(irq_pin(29), 28), + PINMUX_IRQ(irq_pin(22), 40), + PINMUX_IRQ(irq_pin(23), 53), + PINMUX_IRQ(irq_pin(10), 54), + PINMUX_IRQ(irq_pin(9), 56), + PINMUX_IRQ(irq_pin(26), 115), + PINMUX_IRQ(irq_pin(27), 116), + PINMUX_IRQ(irq_pin(28), 117), + PINMUX_IRQ(irq_pin(24), 118), + PINMUX_IRQ(irq_pin(6), 147), + PINMUX_IRQ(irq_pin(2), 149), + PINMUX_IRQ(irq_pin(7), 150), + PINMUX_IRQ(irq_pin(12), 156), + PINMUX_IRQ(irq_pin(4), 159), + PINMUX_IRQ(irq_pin(25), 164), + PINMUX_IRQ(irq_pin(8), 223), + PINMUX_IRQ(irq_pin(3), 224), + PINMUX_IRQ(irq_pin(5), 227), + PINMUX_IRQ(irq_pin(17), 234), + PINMUX_IRQ(irq_pin(11), 238), + PINMUX_IRQ(irq_pin(13), 239), + PINMUX_IRQ(irq_pin(16), 249), + PINMUX_IRQ(irq_pin(14), 251), + PINMUX_IRQ(irq_pin(9), 308), }; /* ----------------------------------------------------------------------------- @@ -3905,8 +3887,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .ranges = pinmux_ranges, - .nr_ranges = ARRAY_SIZE(pinmux_ranges), .groups = pinmux_groups, .nr_groups = ARRAY_SIZE(pinmux_groups), .functions = pinmux_functions, |