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path: root/arch/riscv/configs
AgeCommit message (Expand)Author
2019-07-01riscv: defconfig: enable SOC_SIFIVELoys Ollivier
2019-07-01RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERSAnup Patel
2019-06-26RISC-V: defconfig: enable MMC & SPI for RISC-VAtish Patra
2019-06-11RISC-V: defconfig: enable clocks, serial consoleKevin Hilman
2019-04-09RISC-V: Add separate defconfig for 32bit systemsAnup Patel
2019-01-23RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=yPalmer Dabbelt
2019-01-23RISC-V: defconfig: Enable Generic PCIE by defaultAlistair Francis
2019-01-23RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}Palmer Dabbelt
2018-12-17RISC-V: defconfig: Enable RISC-V SBI earlycon supportAnup Patel
2018-11-12RISC-V: defconfig: Enable printk timestampsAnup Patel
2018-11-01RISC-V: refresh defconfigAnup Patel
2018-08-13irqchip: add a SiFive PLIC driverChristoph Hellwig
2018-06-11RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfigPalmer Dabbelt
2018-04-02RISC-V: Enable module support in defconfigZong Li
2018-01-07RISC-V: Add a basic defconfigKarsten Merker
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt