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path: root/drivers/clk
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2016-12-14clk: samsung: set SPI0 ioclk and slck as ignore unusedHoegeun Kwon
There is no one who handles the ioclk and sclk for the SPI0 bus, in order to be able to use the SPI 0 bus, set them as ignore unused by using the CLK_IGNORE_UNUSED flag in the gate declaration. The Exynos5433 SoC needs to have all the clocks enabled, they get all disabled even if one of them is disabled. Change-Id: I57a625f20c40b4d76046da1a8caf5976454dda1b Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
2016-12-14clk: exynos542x: add IGNORE_UNUSED flag to aclk432_scaler clockMarek Szyprowski
This keeping this clock enabled is needed for proper GSCL power domain on/off sequence, so add this flag to avoid core disabling it on boot. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Change-Id: I8b2e39c3a76fd194104eb21066d33b2f0a5a8289
2016-12-14clk: exynos5433: use CLK_IGNORE_UNUSED for the SPI3 related clockJaehoon Chung
The SPI 3 bus uses two clocks, a bus clock and an input clock. Do not disable the clocks when unused in order to allow access to the SPI 3 device. Change-Id: I5fbc360e4b0ed2043b0bf1f2dd251f3e913082f3 Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
2016-12-14clk: exynos5420: Set ID for aclk333 gate clockJavier Martinez Canillas
The aclk333 clock needs to be ungated during the MFC power domain switch, so set the clock ID to allow the Exynos power domain logic to lookup this clock if is defined in the MFC PD device tree node. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> [backport of mainline commit 34cba900375ec1751a87d3655ad03b9a5b022362] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Change-Id: I34cba900375ec1751a87d3655ad03b9a5b022362
2016-12-14clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLLChanwoo Choi
This patch add the clock id of EPLL to handle it on devicetree file and the rate tables. EPLL is used as root clock of ASS (Audio Subsystem). Change-Id: Iefcbd5ea4cb911a3b5d75888286926773a98af54 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5422: add missing parent GSCL block clocksMarek Szyprowski
This patch adds clocks, which are required for preserving parent clock configuration on GSCALLER power domain on/off. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2016-12-14clk: samsung: exynos5422: fix MFC clock hierarchy parentMarek Szyprowski
Proper source for MFC block is mout_user_aclk333 (in datasheet named USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2016-12-14clk: samsung: exynos3250: Add MMC2 clockChanwoo Choi
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Change-Id: Ib0c194e09f6ed171ba1a84a35a96f651b615666f Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos3250: Add UART2 clockChanwoo Choi
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Change-Id: I5b013ed835a3985659f956b2bd3e64dbeeca7369 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5800: fix cpu clock configuration dataBartlomiej Zolnierkiewicz
Fix cpu clock configuration data for Exynos5800 (it uses higher PCLK_DBG divider values than Exynos5420 and supports additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: samsung: exynos5420: add cpu clock configuration data and instantiate ↵Thomas Abraham
cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5420. Changes by Bartlomiej: - split Exynos5420 support from the original patches - moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: samsung: exynos5250: add cpu clock configuration data and instantiate ↵Thomas Abraham
cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Changes by Bartlomiej: - split Exynos5250 support from the original patch - moved E5250_CPU_DIV[0,1]() macros to clk-exynos5250.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: samsung: exynos4x12: add cpu clock configuration data and instantiate ↵Bartlomiej Zolnierkiewicz
cpu clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4x12. Based on the earlier work by Thomas Abraham. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu ↵Thomas Abraham
clock With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: samsung: add infrastructure to register cpu clocksThomas Abraham
The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Changes by Bartlomiej: - fixed issue with setting lower dividers before the parent clock speed was lowered (the issue resulted in lockup on Exynos4210 SoC based Origen board when "ondemand" cpufreq governor was stress tested) - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change() problem by moving cfg_data search outside of the spin locked area - removed leftover kfree() in exynos_register_cpu_clock() that could result in dereferencing the NULL pointer on error - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers - added missing "last chance" checks to wait_until_divider_stable() and wait_until_mux_stable() (needed in case that IRQ handling took long time to proceed and resulted in function printing incorrect error message about timeout) - moved E4210_CPU_DIV[0,1]() macros just before their only users, this resulted in moving them from patch #2 to patch #3/6 ("clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock") - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV() macros for now - added my Copyrights to drivers/clk/samsung/clk-cpu.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock supportBartlomiej Zolnierkiewicz
This flag is needed to fix the issue with wrong dividers being setup by Common Clock Framework when using the new Exynos cpu clock support. The issue happens because clk_core_set_rate_nolock() calls clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have a chance to run. In case of Exynos cpu clock support pre/post clock notifiers are registered for mout_apll clock which is a parent of armclk cpu clock and dividers are modified in both pre and post clock notifier. This results in wrong dividers values being later programmed by clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES flag is added and it is set for mout_apll clock later so the correct divider values are re-calculated after both pre and post clock notifiers had run. For example when using "performance" governor on Exynos4210 Origen board the cpufreq-dt driver requests to change the frequency from 1000MHz to 1200MHz and after the change state of the relevant clocks is following: Without use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 300000000 div_hpm rate: 300000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 300000000 div_pclk_dbg rate: 150000000 sclk_apll rate: 1200000000 sclk_apll_div_2 rate: 600000000 With use of CLK_GET_RATE_NOCACHE flag: fout_apll rate: 1200000000 fout_apll_div_2 rate: 600000000 mout_clkout_cpu rate: 600000000 div_clkout_cpu rate: 600000000 clkout_cpu rate: 600000000 mout_apll rate: 1200000000 armclk rate: 1200000000 mout_hpm rate: 1200000000 div_copy rate: 200000000 div_hpm rate: 200000000 mout_core rate: 1200000000 div_core rate: 1200000000 div_core2 rate: 1200000000 arm_clk_div_2 rate: 600000000 div_corem0 rate: 300000000 div_corem1 rate: 150000000 div_periph rate: 300000000 div_atb rate: 240000000 div_pclk_dbg rate: 120000000 sclk_apll rate: 150000000 sclk_apll_div_2 rate: 75000000 Without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board. This issue was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags" patch) but usage of these flags is not sufficient to fix the issue observed. Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
2016-12-14clk: exynos5433: Fix mout_aclk_cam1*_user clocks definitionSylwester Nawrocki
Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: Drop RO registers from the save/restore listsSylwester Nawrocki
Change-Id: I3c2885a3f85d3f7fdc33d56892161ad37828000c Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: add CLK_IGNORE_UNUSED to all camera clocksMarek Szyprowski
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2016-12-14clk: samsung: exynos5433: Add ISP/CAM IP gate clocksSylwester Nawrocki
clk: samsung: exynos5433: Add CLK_ISP_SPIx gate clocks clk: samsung: exynos5433: Add more clock definitions for gate clocks clk: samsung: exynos5433: Fix CAM0_NR_CLK macro definition value Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: Change *RXBYTEECLKHS0_* clock rates to 188 MHzSylwester Nawrocki
Values taken from the Android kernel. Change-Id: Ia8606b729018f24987a2c5e2ad693ab52bf3497d Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocksMarek Szyprowski
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2016-12-14clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocksSylwester Nawrocki
This corrects bit offsets in the MUX_SEL_CAM04 gate control register. Change-Id: I96305b941b3bcd3eed083b6b08d501c4e4509dda Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock namesSylwester Nawrocki
Change-Id: I83ae4420ce171c58271d0a0222ef9bae3def831a Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-12-14clk: samsung: exynos5433: Add pm_domain notification when domain is avaiable.Jonghwa Lee
Not to postpone the registration of notifier block undefinedly, it registers pm_domain notification at once when the pm_domain is available. It checks new pm_domain creation until it founds corresponding one. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk/samsung: added pclk_decon clockAndrzej Hajda
This gate clock is partially documented. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
2016-12-14clk: exynos5433: add defines for HDMI-PHY output clocksAndrzej Hajda
HDMI driver must re-parent respective muxes during HDMI-PHY on/off to HDMI-PHY output clocks. To reference those clocks their defines should be added. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
2016-12-14local/clk: exynos5433: Fix ERR_PTR dereference when parsing power domainsKrzysztof Kozlowski
Fix dereference of an ERR_PTR returned by of_genpd_get_from_provider() when DTS specifies clocks for a power domain, like: pd_disp: disp-power-domain@105c4080 { clocks = <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, <&cmu_disp CLK_FIXED_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>; }; OOPS: Unable to handle kernel NULL pointer dereference at virtual address 0000025a Call trace: do_raw_spin_lock+0x10/0x18c _raw_spin_lock_irqsave+0x24/0x38 atomic_notifier_chain_register+0x14/0x74 exynos_pd_notifier_register+0x4c/0x54 exynos5433_suspend_init+0x40/0x240 do_one_initcall+0x88/0x1ac kernel_init_freeable+0x1bc/0x264 kernel_init+0xc/0xdc Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-12-14clk: samsung: exynos5433: Add power domain notifier to g3d cmuJonghwa Lee
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks.Jonghwa Lee
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: exynos5433: Add power domain notifier to diplay cmu.Jonghwa Lee
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: exynos5433: Add power domain notifier for restoring clock registers.Jonghwa Lee
In EXYNOS5433, when power domain turns off, correspoding cmu block also is powered down. Therefore, save and restore cmu's registers whenever power domain's status is changing. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14local/clk: add gate_pcie and gate_pcie_phy and set CLK_INGNORE_UNUSEDJaehoon Chung
This patch is workaround for pcie. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-12-14LOCAL / clk: samsung: exynos5433: enable ignore unused flagInha Song
This patch enable ignore unused flags for control SFR_LPASS_* registers. Signed-off-by: Inha Song <ideal.song@samsung.com>
2016-12-14clk: samsung: exynos5433: Add suspend_prepare/unprepare callback.Jonghwa Lee
This patch adds exynos5433 CMU's suspend_prepare/unprepare callback. Exynos5433 has clocks to be controlled before entering suspend. There're two types of clocks, one is a clock which has to be turned on at suspend, and another is a clock which has to be set parent clock to specified one. It can be defined at device tree with properties, 'suspend-on-clks' and 'suspend-reparent-clks'. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: samsung: Introduce supend_prepare/unprepare callback.Jonghwa Lee
To manage the chip dependent clock control for suspend, this patch introduce additional suspend callback at the level of entering suspend. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14LOCAL / RFC / clk: Provide an always-on clock domain frameworkLee Jones
Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover is to restart the board(s). This driver takes references to clocks which are required to be always-on in order to prevent the common clk framework from trying to turn them off during the clk_disabled_unused() procedure. Signed-off-by: Lee Jones <lee.jones@linaro.org>
2016-12-14clk: exynos5433: Add 'CLK_IGNORE_UNUSED' flag to clocks occuring hang at resumeJonghwa Lee
Add 'CLK_IGNORE_UNUSED' flag to th clocks which make hang at wake-up. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleepJonghwa Lee
Some clocks are required being unmasked during suspend-to-ram. Otherwise, PMU will stuck and power line never down. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: exynos5433: Add 'CLK_IGNORE_UNUSED' flag to clocks for sercure monitor callJonghwa Lee
This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for operation of secure monitor call (smc). System will hang when it executes 'smc' with one of those clock is gated. All related clocks must be enabled. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
2016-12-14clk: samsung: exynos5433: add DIV_CPIF to store it when the board is being ↵Hyungwon Hwang
suspended This register must be stored when the device is suspended, and must be restored when it is back. This patch adds the register to the list of storing registers. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
2016-12-14LOCAL / clk: s2mps11: Avoid deadlock issue between regmap and CCFChanwoo Choi
This patch avoids the deadlock issue between regmap framework and common clock framework by remaining the always on state for S2MPS11 clocks without any i2c operation. It is workaround solution to avoid the deadlock issue. [ 2833.400071] INFO: task swapper/0:1 blocked for more than 120 seconds. [ 2833.400211] Not tainted 4.0.0-00337-gee47844-dirty #4 [ 2833.400328] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 2833.400489] swapper/0 D ffffffc000086e0c 0 1 0 0x00000000 [ 2833.404602] Call trace: [ 2833.407042] [<ffffffc000086e0c>] __switch_to+0x74/0x8c [ 2833.412251] [<ffffffc00089842c>] __schedule+0x21c/0x6d0 [ 2833.417363] [<ffffffc000898910>] schedule+0x30/0x8c [ 2833.422253] [<ffffffc00089c234>] schedule_timeout+0x14c/0x204 [ 2833.427953] [<ffffffc0008993ec>] wait_for_common+0xa0/0x148 [ 2833.433533] [<ffffffc0008994a4>] wait_for_completion+0x10/0x1c [ 2833.439324] [<ffffffc0000ae90c>] flush_workqueue+0x108/0x568 [ 2833.444992] [<ffffffc000447fc4>] deferred_probe_initcall+0x54/0x88 [ 2833.451151] [<ffffffc0000828d4>] do_one_initcall+0x88/0x1a0 [ 2833.456685] [<ffffffc000d62b34>] kernel_init_freeable+0x1bc/0x260 [ 2833.462783] [<ffffffc000893350>] kernel_init+0xc/0xd8 [ 2833.467793] INFO: task kworker/u16:0:6 blocked for more than 120 seconds. [ 2833.474586] Not tainted 4.0.0-00337-gee47844-dirty #4 [ 2833.480138] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 2833.487928] kworker/u16:0 D ffffffc000086e0c 0 6 2 0x00000000 [ 2833.494967] Workqueue: deferwq deferred_probe_work_func [ 2833.500166] Call trace: [ 2833.502602] [<ffffffc000086e0c>] __switch_to+0x74/0x8c [ 2833.507721] [<ffffffc00089842c>] __schedule+0x21c/0x6d0 [ 2833.512950] [<ffffffc000898910>] schedule+0x30/0x8c [ 2833.517791] [<ffffffc000898cd8>] schedule_preempt_disabled+0x10/0x24 [ 2833.524151] [<ffffffc00089b0f4>] __mutex_lock_slowpath+0x148/0x368 [ 2833.530310] [<ffffffc00089b324>] mutex_lock+0x10/0x30 [ 2833.535328] [<ffffffc00045bd14>] regmap_lock_mutex+0x8/0x14 [ 2833.540906] [<ffffffc00045e844>] regmap_update_bits+0x24/0x60 [ 2833.546611] [<ffffffc0005c6800>] s2mps11_clk_prepare+0x20/0x2c [ 2833.552450] [<ffffffc0005c21bc>] clk_core_prepare+0x50/0x84 [ 2833.557979] [<ffffffc0005c220c>] clk_prepare+0x1c/0x48 [ 2833.563125] [<ffffffc000633084>] tm2_late_probe+0x54/0xc0 [ 2833.568658] [<ffffffc00061ae50>] snd_soc_register_card+0xe48/0xf3c [ 2833.574844] [<ffffffc000627644>] devm_snd_soc_register_card+0x38/0x8c [ 2833.581262] [<ffffffc0006332a8>] tm2_wm5110_probe+0x1b8/0x28c [ 2833.587147] [<ffffffc000449f6c>] platform_drv_probe+0x48/0xb8 [ 2833.592897] [<ffffffc000448290>] driver_probe_device+0x8c/0x244 [ 2833.598776] [<ffffffc00044848c>] __device_attach+0x44/0x54 [ 2856.015428] [<ffffffc0004466c4>] bus_for_each_drv+0x50/0x94 [ 2856.020961] [<ffffffc0004481b8>] device_attach+0x9c/0xcc [ 2856.026213] [<ffffffc0004477c8>] bus_probe_device+0x8c/0xb4 [ 2856.031786] [<ffffffc000447c28>] deferred_probe_work_func+0x70/0xa8 [ 2856.038019] [<ffffffc0000b0b78>] process_one_work+0x158/0x424 [ 2856.043761] [<ffffffc0000b16ec>] worker_thread+0x140/0x474 [ 2856.049216] [<ffffffc0000b5f44>] kthread+0xd8/0xf0 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5433: Remove CLK_DIVIDER_READ_ONLY flag from div_aclk_g3dChanwoo Choi
This patch removes the CLK_DIVIDER_READ_ONLY flag from div_aclk_g3d clock because of supporting the propagation of the G3D clocks. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5433: add flags for g3d clockJoonyoung Shim
Need missing CLK_SET_RATE_PARENT and CLK_DIVIDER_READ_ONLY for devfreq of g3d clock. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
2016-12-14clk: divider: fix to set parent rate from CLK_DIVIDER_READ_ONLY flagJoonyoung Shim
The round_rate callback function will returns alway same parent clk rate of divider with CLK_DIVIDER_READ_ONLY flag. If be used CLK_SET_RATE_PARENT flag with CLK_DIVIDER_READ_ONLY flag, then never change parent clk rate anymore. From this case, this patch allows to change parent clk rate. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
2016-12-14clk: divider: don't set_rate with CLK_DIVIDER_READ_ONLY flagJoonyoung Shim
Even if use CLK_DIVIDER_READ_ONLY flag, divider setting can be changed by set_rate callback. Don't change divider setting from set_rate callback of divider with CLK_DIVIDER_READ_ONLY flag. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
2016-12-14clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for ↵Chanwoo Choi
Cortex-A57 core This patch adds CLK_SET_RATE_PARENT flag to support DVFS feature of Cortex-A57 Core (big core) because 'sclk_atlas' leaf clock is used to change the CPU frequency of Cortex-A57 core in arm_big_little.c driver. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT flag for aclk_g3d to ↵Chanwoo Choi
support GPU DVFS This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock to support GPU DVFS feature. The MALI driver uses the 'aclk_g3d' clock for DVFS feature. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for ↵Chanwoo Choi
Cortex-A53 core This patch adds CLK_SET_RATE_PARENT flag to support DVFS feature of Cortex-A53 Core (LITTLE core) because 'sclk_apollo' leaf clock is used to change the CPU frequency of Cortex-A53 core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-12-14clk: Show clock rate instead of return valueChanwoo Choi
This patch shows the current clock rate instead of return value when clk_set_rate() return fail because log message means the clock rate. Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-12 09:17:21 +0000