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path: root/drivers/clk
AgeCommit message (Expand)Author
2022-05-10clk: samsung: exynosautov9: add cmu_peris clock supportChanho Park
2022-05-10clk: samsung: exynosautov9: add cmu_core clock supportChanho Park
2022-05-10clk: samsung: add top clock support for Exynos Auto v9 SoCChanho Park
2022-05-07ARM: pxa: move clk register definitions to driverArnd Bergmann
2022-05-07ARM: pxa: move smemc register access from clk to platformArnd Bergmann
2022-05-07cpufreq: pxa3: move clk register access to clk driverArnd Bergmann
2022-05-06clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara
2022-05-06clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara
2022-05-06clk: tegra: Update kerneldoc to match prototypesThierry Reding
2022-05-06clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy
2022-05-06clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy
2022-05-05clk: qcom: gcc-msm8976: Add modem resetAdam Skladowski
2022-05-05clk: qcom: gcc-msm8976: Set floor ops for SDCCAdam Skladowski
2022-05-05clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das
2022-05-04clk: tegra: Replace .round_rate() with .determine_rate()Rajkumar Kasirajan
2022-05-04clk: tegra: Register clocks from root to leafTimo Alho
2022-05-04clk: tegra: Add missing reset deassertionDiogo Ivo
2022-05-03clk: rockchip: Mark hclk_vo as critical on rk3568Sascha Hauer
2022-05-02Merge 5.18-rc5 into driver-core-nextGreg Kroah-Hartman
2022-05-02clk: imx8mp: add clkout1/2 supportLucas Stach
2022-05-02clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageMiaoqian Lin
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda
2022-04-28clk: qcom: smd: Update MSM8976 RPM clocks.Adam Skladowski
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das
2022-04-28clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal
2022-04-26clk: en7523: fix wrong pointer check in en7523_clk_probe()Yang Yingliang