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path: root/drivers/clk
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2016-09-16clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai
The PLLs have a "lock" bit in their configuration registers which indicate if the PLL has locked on to the requested clock rate. We check this bit in the .set_rate op. The PLL cannot lock on if it's not running, which might be a false positive (warning). Set the CLK_SET_RATE_UNGATE flag for all PLLs so whenever clk_set_rate is called on them, they get enabled and the "lock" check is really checking the PLL. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai
The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks to generate their dot clocks. To be able to generate a full range of possible clock rates, the parent PLL clock rates should also be changed. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Handle clk synchronous mode for video clocksGabriel Fernandez
This patch configures the semi-synchronous mode of the video clocks of clkgenD2. Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Add clock propagation for audio clocksGabriel Fernandez
This patch allows fine tuning of the quads FS for audio clocks accuracy. Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Add fs660c32 synthesizer algorithmGabriel Fernandez
Use an algorithm instead of a table to compute clocks for fs660c32 synthesizer. During a video playback we need to adjust audio & video frequencies. A table can't cover all HDMI resolutions and audio adjustment. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Simplify clock binding of STiH4xx platformsGabriel Fernandez
This patch reworks the clock binding to avoid too much detail in DT. Now we have only compatible string per type of clock (remark from Rob https://lkml.org/lkml/2016/5/25/492) Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16drivers: clk: st: Remove stih415-416 clock supportGabriel Fernandez
STiH415 and STiH416 platforms are no longer used. these platforms will be deprecated for the next kernel. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: at91: Migrate to clk_hw based registration and OF APIsStephen Boyd
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: bcm2835: Migrate to clk_hw based registration and OF APIsStephen Boyd
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Eric Anholt <eric@anholt.net> Cc: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
2016-09-14clk: iproc: Make clocks visible optionsJon Mason
Make the clocks visible options that can be selected by anyone. This avoids the problems of: 1) Select is a reverse dependency and is hard for people to understand and can sometimes be a pain to track down 2) Build coverage goes down because configs are hidden 3) Code bloat Patch suggested by Stephen Boyd Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: xgene: Add PMD clockHoan Tran
Add X-Gene PMD clock support. PMD clock is implemented for a single register field. Output rate = parent_rate * (denominator - scale) / denominator with - denominator = bitmask of register field + 1 - scale = values of register field For example, for bitmask is 0x7, denominator will be 8 and scale will be computed and programmed accordingly. Signed-off-by: Hoan Tran <hotran@apm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: zx: register ZX296718 clocksJun Nie
The ZX296718 clocks are statically listed and registered. More clock will be added later. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: zx: reform pll config info to ease code extensionJun Nie
Add power down bit and pll lock bit in pll config structure to ease new SoC support. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk-kona-setup: Use kmalloc_array() in parent_process()Markus Elfring
A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kmalloc_array". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Alex Elder <elder@linaro.org> [sboyd@codeaurora.org: Save a line] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14ARM: clk-imx35: annotate clk enum with number valuesUwe Kleine-König
This helps to decode error messages like: [ 0.000000] i.MX clk 82: register failed with -17 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14ARM: clk-imx35: fix name for ckil clkUwe Kleine-König
This fixes [ 0.000000] i.MX clk 82: register failed with -17 because the name is duplicated. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc") Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: gxbb: expose i2c clocksJerome Brunet
I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose USB clocksMartin Blumenstingl
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose spifc clockJerome Brunet
SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose MPLL2 clock for use by DTMartin Blumenstingl
This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: meson: fix CLKID_GCLK_VENCI_INT typoArnd Bergmann
The addition of many gate clocks added two entries in an array for the same value: drivers/clk/meson/meson8b.c:479:10: error: initialized field overwritten [-Werror=override-init] [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw, This was clearly an accident, and since all other identifiers are listed in the order in which they are defined, I'm changing the first one to CLKID_GCLK_VENCI_INT0, making it all consistent again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14clk: mmp: add missing header dependenciesBaoyou Xie
We get 1 warning when building kernel with W=1: drivers/clk/mmp/clk-mmp2.c:75:13: warning: no previous prototype for 'mmp2_clk_init' [-Wmissing-prototypes] In fact, this function is declared in linux/clk/mmp.h, so this patch add missing header dependencies. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14Merge tag 'clk-renesas-for-v4.9-tag3' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas clk driver updates from Geert Uytterhoeven: - External crystal selection for RZ/A1, - CMT clocks for R-Car H3 and M3-W, - RAVB and Thermal clocks for R-Car M3-W. * tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add CMT clocks clk: renesas: r8a7795: Add CMT clocks clk: renesas: r8a7796: Add RAVB clock clk: renesas: r8a7796: Add THS/TSC clock clk: renesas: rz: Select EXTAL vs USB clock
2016-09-14meson: clk: Use builtin_platform_driver to simplify the codeWei Yongjun
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14Merge tag 'sunxi-clk-for-4.9' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock driver changes from Maxime Ripard: Four more SoCs converted to the new clock framework (A31, A31s, A23 and A33). * tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: Add hardware dependency clk: sunxi-ng: Add A23 CCU clk: sunxi-ng: Add A33 CCU support clk: sunxi-ng: Add N-class clocks support clk: sunxi-ng: mux: Add mux table macro clk: sunxi-ng: div: Allow to set a maximum clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure clk: sunxi-ng: div: Add mux table macros clk: sunxi-ng: Add A31/A31s clocks clk: sunxi-ng: mux: Add clk notifier functions clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents clk: sunxi-ng: mux: Add support for mux tables clk: sunxi-ng: mux: Rename mux macro to be consistent clk: sunxi-ng: nkm: Add mux to support multiple parents clk: sunxi-ng: mux: Increase fixed pre-divider div size
2016-09-14Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd
clk-next Pull samsung clk driver updates from Sylwester Nawrocki: In addition to a few clean up and code consolidation patches this includes: - addition of sound subsystem related clocks for Exynos5410 SoC (EPLL, PDMA) and support for "samsung,exynos5410-audss-clock" compatible in the clk-exynos-audss driver, - addition of DRAM controller related clocks for exynos5420, - MAINTAINERS update adding Chanwoo Choi as the Samsung SoC clock drivers co-maintainer. * tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Add support for EPLL on exynos5410 clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanup clk: samsung: clk-exynos-audss: Add exynos5410 compatible clk: samsung: clk-exynos-audss: controller variant handling rework clk: samsung: Use common registration function for pll2550x clk: samsung: exynos5410: Expose the peripheral DMA gate clocks clk: samsung: exynos5420: Add clocks for CMU_CDREX domain clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify code clk: samsung: exynos5260: Move struct samsung_cmu_info to init section MAINTAINERS: Add myself as Samsung SoC clock drivers co-maintainer clk: samsung: exynos5410: Add clock IDs for PDMA and EPLL clocks clk: samsung: Add clock IDs for the CMU_CDREX (DRAM Express Controller)
2016-09-14Merge tag 'amlogic-dt64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late Pull "Amlogic 64-bit DT changes for v4.9" from Kevin Hilman: - add watchdog, reset, IR remote, PWM - add secure monitor and eFuse - add always-on (AO) domain clock and reset * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: amlogic: gxbb: Enable NVMEM documentation: Add nvmem bindings documentation ARM64: dts: amlogic: gxbb: Enable secure monitor documentation: Add secure monitor bindings documentation ARM64: dts: meson-gxbb: Add PWM pinctrl nodes ARM64: dts: meson-gxbb: Enable the the IR decoder on supported boards ARM64: dts: meson-gxbb: Add Infrared Remote Controller decoder dt-bindings: media: meson-ir: Add Meson8b and GXBB compatible strings ARM64: dts: amlogic: add the input pin for the IR remote ARM64: dts: meson-gxbb: Add GXBB AO Clock and Reset node clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe() clk: meson: Add GXBB AO Clock and Reset controller driver dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings ARM64: DTS: meson-gxbb: switch ethernet to real clock ARM64: dts: amlogic: meson-gxbb: Add watchdog node
2016-09-12clk: renesas: r8a7796: Add CMT clocksBui Duc Phuc
This patch adds CMT module clocks for r8a7796 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12clk: renesas: r8a7795: Add CMT clocksBui Duc Phuc
This patch adds CMT module clocks for r8a7795 SoC. Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12clk: renesas: r8a7796: Add RAVB clockLaurent Pinchart
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-10clk: sunxi-ng: Add hardware dependencyJean Delvare
The sunxi-ng clock driver is useless for other architectures. Signed-off-by: Jean Delvare <jdelvare@suse.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-10clk: sunxi-ng: Add A23 CCUMaxime Ripard
Add support for the clock unit found in the A23. Due to the similarities with the A33, it also shares its clock IDs to allow sharing the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10clk: sunxi-ng: Add A33 CCU supportMaxime Ripard
This commit introduces the clocks found in the Allwinner A33 CCU. Since this SoC is very similar to the A23, and we share a significant share of the DTSI, the clock IDs that are going to be used will also be shared with the A23, hence the name of the various header files. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10clk: sunxi-ng: Add N-class clocks supportMaxime Ripard
Add support for the class with a single factor, N, being a multiplier. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10clk: sunxi-ng: mux: Add mux table macroMaxime Ripard
Add a new macro to declare muxes based on a table and a gate. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10clk: sunxi-ng: div: Allow to set a maximumMaxime Ripard
Some dividers might have a maximum value that is lower than the width of the register. Add a field to _ccu_div to handle those case properly. If the field is set to 0, the code will assume that the maximum value is the maximum one that can be used with the field register width. Otherwise, we'll use whatever value has been set. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structureMaxime Ripard
The internal _ccu_div structure is meant to be embedded into other structures to combine the various dividers and to form the clock classes support. Start to document those structures by using kerneldoc. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-09-10clk: sunxi-ng: div: Add mux table macrosMaxime Ripard
Add some macros to ease the declaration of clocks that are using them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-09clk: rk808: Pass the right pointer as the get_hw contextTomeu Vizoso
Right now we are passing a pointer to a pointer to the structure that will be used to fetch the clk hw, which gets casted later to a pointer to the structure, thus getting garbage in the hw structs. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Fixes: a8b6e85db6a6 ("clk: rk808: Migrate to clk_hw based OF and registration APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-09clk: samsung: Add support for EPLL on exynos5410Sylwester Nawrocki
This patch adds code instantiating the EPLL, which is used as the audio subsystem's root clock. The requirement to specify the external root clock in clocks property is documented. Having the consumer 'clocks' property ensures proper initialization order by explicitly specifying dependencies in DT. It prevents situations when the SoC's clock controller driver has initialized, the external oscillator clock is not yet registered and setting clock frequencies through assigned-clock-rates property doesn't work properly due to unknown external oscillator frequency. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-09-09clk: samsung: clk-exynos-audss: Whitespace and debug trace cleanupSylwester Nawrocki
There is no need to log probe() completion in normal conditions so the "setup completed" log is removed. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: clk-exynos-audss: Add exynos5410 compatibleSylwester Nawrocki
Exynos5410 Audio Subsystem Clock Controller, comparing to the already supported IP block revisions, has additionally an I2S_MST divider so a new compatible string is added. It is not clear from the Exynos5410 User's Manual released on 2012.03.09 where in the clock tree the I2S_MST clock divider can be found exactly so this clock is left unimplemented for now. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: clk-exynos-audss: controller variant handling reworkSylwester Nawrocki
Then variant handling is reworked to make the code simpler when more variants are added. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: Use common registration function for pll2550xSylwester Nawrocki
There is no such significant differences in pll2550x PLL type to justify a separate registration function. This patch adapts exynos5440 driver to use the common function and removes samsung_clk_register_pll2550x(). Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
2016-09-09clk: samsung: exynos5410: Expose the peripheral DMA gate clocksSylwester Nawrocki
These clocks are needed in order to use the PL330 peripheral DMA controllers. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: exynos5420: Add clocks for CMU_CDREX domainChanwoo Choi
This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus. There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source group. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: exynos5410: Use samsung_cmu_register_one() to simplify codeChanwoo Choi
This patch uses the samsung_cmu_register_one() to simplify code and move the pll/mux/div/gate data to initconst section. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-09clk: samsung: exynos5260: Move struct samsung_cmu_info to init sectionChanwoo Choi
This patch moves the samsung_cmu_info struct instances to initconst section, this decreases the kernel image size by 784 bytes, which makes zImage smaller by 480 bytes. The patch increases .init.rodata section size by 780 bytes but decreases .init.text section size by 1564 bytes. Size of the drivers/clk/samsung/clk-exynos5260.o object file is 29100 bytes without the patch and 28316 after applying the patch. The section size differences are as below: 15c15 < 3 .init.text 000006b8 00000000 00000000 00000034 2**2 --- > 3 .init.text 0000009c 00000000 00000000 00000034 2**2 25c25 < 8 .init.rodata 00003f6c 00000000 00000000 00002f20 2**2 --- > 8 .init.rodata 00004278 00000000 00000000 00002904 2**2 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2016-09-08Merge branch 'clk-fixes' into clk-nextStephen Boyd
* clk-fixes: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
2016-09-08Merge tag 'sunxi-clk-fixes-for-4.8' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Clock Fixes for the Allwinner SoCs, 4.8 Edition The usual bunch of fixes to the our clock drivers, mostly targetted to the brand new sunxi-ng drivers. * tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 00:33:24 +0000