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path: root/drivers/gpu/drm
AgeCommit message (Expand)Author
2013-10-11drm/i915: Fix VLV frame counter registersVille Syrjälä
2013-10-11drm/i915/vlv: add doc names to sideband fileJesse Barnes
2013-10-11drm/i915: don't save/restore CACHE_MODE_0 on gen7+Jesse Barnes
2013-10-11drm/i915: Fix pipe off timeout handling for pre-gen4Ville Syrjälä
2013-10-11drm/i915: increase the SWSCI DSLP default timeout to 50msPaulo Zanoni
2013-10-10drm/i915: Avoid tweaking RPS before it is enabledChris Wilson
2013-10-10drm/i915: tell the user KMS is required for gen6+Jani Nikula
2013-10-10drm/i915: Educate users in dmesg about reporting gpu hangsDaniel Vetter
2013-10-10drm/i915: Finish enabling rps before use by sysfs or debugfsTom O'Rourke
2013-10-10drm/i915: Capture the initial error-state when kicking stuck ringsChris Wilson
2013-10-10drm/i915: Rename primary_disabled to primary_enabledVille Syrjälä
2013-10-10drm/i915: Populate primary_disabled in intel_modeset_readout_hw_state()Ville Syrjälä
2013-10-10drm/i915: don't leak dp_connector at intel_ddi_initPaulo Zanoni
2013-10-10drm/i915/dp: update training set in a burst write with training pattern setJani Nikula
2013-10-10drm/i915: Do PCH and uncore init earlierBen Widawsky
2013-10-10drm/i915: wait for IPS_ENABLE when enabling IPSPaulo Zanoni
2013-10-10drm/i915: Keep intel_drv.h tidyDaniel Vetter
2013-10-10drm/i915: Remove gen specific checks in MMIOBen Widawsky
2013-10-10drm/i915: Create GEN specific write MMIOBen Widawsky
2013-10-10drm/i915: Create GEN specific read MMIOBen Widawsky
2013-10-10drm/i915: Extract common MMIO linesBen Widawsky
2013-10-10drm/i915: Create MMIO virtual functionsBen Widawsky
2013-10-10drm/i915: Move edram detection early_sanitizeBen Widawsky
2013-10-10drm/i915: Prevent using uninitialized MMIO funcsBen Widawsky
2013-10-10drm/i915: rip out gen2 reset codeDaniel Vetter
2013-10-10drm/i915: check that the i965g/gm 4G limit is really obeyedDaniel Vetter
2013-10-10drm/i915: Undo the PIPEA quirk for i845Chris Wilson
2013-10-10drm/i915: Use the real cpu max frequency for ring scalingBen Widawsky
2013-10-10drm/i915: Flush primary plane changes in sprite codeVille Syrjälä
2013-10-10drm/i915: WARN if primary plane state doesn't match expectationsVille Syrjälä
2013-10-10drm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_pri...Ville Syrjälä
2013-10-10drm/i915: Rename intel_flush_display_plane to intel_flush_primary_planeVille Syrjälä
2013-10-10drm/i915: Enable/disable IPS when primary is enabled/disabledVille Syrjälä
2013-10-10drm/i915: Do the fbc vs. primary plane enable/disable in the right orderVille Syrjälä
2013-10-10drm/i915: Save user requested plane coordinates only on successVille Syrjälä
2013-10-10drm/i915: Do a bit of cleanup in the sprite codeVille Syrjälä
2013-10-10drm/i915: Kill a goto from sprite disable codeVille Syrjälä
2013-10-10drm/i915: Reduce the time we hold struct mutex in sprite update_plane codeVille Syrjälä
2013-10-10drm/i915: Allow sprites to be configured on a disabled pipeVille Syrjälä
2013-10-10drm/i915: Set primary_disabled in intel_{enable, disable}_planeVille Syrjälä
2013-10-10drm/i915/dp: promote clock recovery failures to DRM_ERRORJani Nikula
2013-10-10drm/i915: Fix VGA_DISP_DISABLE checkVille Syrjälä
2013-10-10drm/i915: Use intel_PLL_is_valid() in vlv_find_best_dpll()Ville Syrjälä
2013-10-10drm/i915: Don't lie about findind suitable PLL settings on VLVVille Syrjälä
2013-10-10drm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the sameVille Syrjälä
2013-10-10drm/i915: Remove unused dot_limit from VLV PLL limitsVille Syrjälä
2013-10-10drm/i915: Remove the unused p and m limits for VLVVille Syrjälä
2013-10-10drm/i915: Respect p2 divider minimum limit on VLVVille Syrjälä
2013-10-10drm/i915: Allow p1 divider 2 on VLVVille Syrjälä
2013-10-10drm/i915: Clarify VLV PLL p1 limitsVille Syrjälä
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