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path: root/drivers/gpu
AgeCommit message (Expand)Author
2015-11-17drm/i915: Serialise updates to GGTT with access through GGTT on BraswellChris Wilson
2015-11-17drm/i915: force link training when requested by SinkShubhangi Shrivastava
2015-11-17drm/i915: Cleanup test data during long/short hotplugShubhangi Shrivastava
2015-11-17drm/i915/skl: Correct other-pipe watermark update condition check (v2)Kumar, Mahesh
2015-11-16drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä
2015-11-16drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]Ville Syrjälä
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä
2015-11-16drm/i915: Replace the aux ddc name switch statement with kasprintf()Ville Syrjälä
2015-11-16drm/i915: Replace aux_ch_ctl_reg check with port checkVille Syrjälä
2015-11-13drm/i915/skl: Update DDI translation tables for SKLjim.bride@linux.intel.com
2015-11-13drm/i915: Fix SKL i_boost levelAnder Conselvan de Oliveira
2015-11-12drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6Animesh Manna
2015-11-12drm/i915/gen9: flush DMC fw loading work during system suspendImre Deak
2015-11-12drm/i915/gen9: Use flush_work to synchronize with dmc loaderAnimesh Manna
2015-11-12drm/i915: Use request_firmware and our own async workDaniel Vetter
2015-11-12drm/i915/gen9: extract parse_csr_fwDaniel Vetter
2015-11-12drm/i915/gen9: Use dev_priv in csr functionsDaniel Vetter
2015-11-12drm/i915/gen9: Don't try to load garbage dmc firmware on resumeDaniel Vetter
2015-11-12drm/i915/gen9: Simplify csr loading failure printing.Daniel Vetter
2015-11-12drm/i915/gen9: Align line continuations in intel_csr.c.Daniel Vetter
2015-11-12drm/i915/gen9: Remove csr.state, csr_lock and related code.Daniel Vetter
2015-11-12drm/i915/gen9: move assert_csr_loaded into intel_rpm.cDaniel Vetter
2015-11-12drm/i915: use correct power domain for csr loadingDaniel Vetter
2015-11-12drm/i915/gen9: csr_init after runtime pm enableAnimesh Manna
2015-11-12drm/i915: refactor stepping info retrievalJani Nikula
2015-11-12drm/i915: constify bxt stepping infoJani Nikula
2015-11-12drm/i915: fix indentation on skl stepping infoJani Nikula
2015-11-12drm/i915: Remove redundant check in i915_gem_obj_to_vmaTvrtko Ursulin
2015-11-11drm/i915: Clean up LVDS register handling harderLukas Wunner
2015-11-11drm/i915: Move the fbdev async_schedule() into intel_fbdev.cVille Syrjälä
2015-11-11drm/i915: Do fbdev fini first during unloadVille Syrjälä
2015-11-11drm/i915: Kill intel_runtime_pm_disable()Ville Syrjälä
2015-11-10drm/i915: Setup DDI clk for MST on SKLVille Syrjälä
2015-11-10drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()Ville Syrjälä
2015-11-10drm/i915: Use intel_dp->DP in eDP PLL setupVille Syrjälä
2015-11-10drm/i915: Clean up eDP PLL state assertsVille Syrjälä
2015-11-10drm/i915: Remove ILK-A eDP PLL workaround notesVille Syrjälä
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä
2015-11-10drm/i915: Hide underruns from eDP PLL and port enable on ILKVille Syrjälä
2015-11-10drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä
2015-11-10drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder()Ville Syrjälä
2015-11-10drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPTVille Syrjälä
2015-11-10drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabledVille Syrjälä
2015-11-10drm/i915: Enable PCH FIFO underruns later on HSW+Ville Syrjälä
2015-11-10drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVBVille Syrjälä
2015-11-10drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTLVille Syrjälä
2015-11-10drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config...Ville Syrjälä
2015-11-10drm/i915: remove in_dbg_master check from intel_fbc.cPaulo Zanoni
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