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path: root/drivers/net/wireless/ath/ath10k/hw.h
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2017-01-19ath10k: dump Copy Engine registers during firmware crashMohammed Shafi Shajakhan
Dump Copy Engine source and destination ring addresses. This is useful information to debug firmware crashes, assertes or hangs over long run assessing the Copy Engine Register status. This also enables dumping CE register status in debugfs Crash Dump file. Screenshot: ath10k_pci 0000:02:00.0: simulating hard firmware crash ath10k_pci 0000:02:00.0: firmware crashed! (uuid 84901ff5-d33c-456e-93ee-0165dea643cf) ath10k_pci 0000:02:00.0: qca988x hw2.0 target 0x4100016c chip_id 0x043202ff sub 0000:0000 ath10k_pci 0000:02:00.0: kconfig debug 1 debugfs 1 tracing 1 dfs 1 testmode 1 ath10k_pci 0000:02:00.0: firmware ver 10.2.4.70.59-2 api 5 features no-p2p,raw-mode,mfp,allows-mesh-bcast crc32 4159f498 ath10k_pci 0000:02:00.0: board_file api 1 bmi_id N/A crc32 bebc7c08 ath10k_pci 0000:02:00.0: htt-ver 2.1 wmi-op 5 htt-op 2 cal otp max-sta 128 raw 0 hwcrypto 1 ath10k_pci 0000:02:00.0: firmware register dump: ath10k_pci 0000:02:00.0: [00]: 0x4100016C 0x00000000 0x009A0F2A 0x00000000 ath10k_pci 0000:02:00.0: [04]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [08]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [12]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [16]: 0x00000000 0x00000000 0x00000000 0x009A0F2A ath10k_pci 0000:02:00.0: [20]: 0x00000000 0x00401930 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [24]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [28]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [32]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [36]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [40]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [44]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [48]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [52]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: [56]: 0x00000000 0x00000000 0x00000000 0x00000000 ath10k_pci 0000:02:00.0: Copy Engine register dump: ath10k_pci 0000:02:00.0: [00]: 0x00057400 7 7 3 3 ath10k_pci 0000:02:00.0: [01]: 0x00057800 18 18 85 86 ath10k_pci 0000:02:00.0: [02]: 0x00057c00 49 49 48 49 ath10k_pci 0000:02:00.0: [03]: 0x00058000 16 16 17 16 ath10k_pci 0000:02:00.0: [04]: 0x00058400 4 4 44 4 ath10k_pci 0000:02:00.0: [05]: 0x00058800 12 12 11 12 ath10k_pci 0000:02:00.0: [06]: 0x00058c00 3 3 3 3 ath10k_pci 0000:02:00.0: [07]: 0x00059000 0 0 0 0 ieee80211 phy0: Hardware restart was requested ath10k_pci 0000:02:00.0: device successfully recovered Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> [kvalo@qca.qualcomm.com: simplify the implementation] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-12-29ath10k: decrease num of peers supportBartosz Markowski
The correct number for QCA9377 chip is 33 VDEVs. This impacts also QCA6174 chip and it's max VDEV number. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-10-04ath10k: allow setting coverage classBenjamin Berg
Unfortunately ath10k does not generally allow modifying the coverage class with the stock firmware and Qualcomm has so far refused to implement this feature so that it can be properly supported in ath10k. If we however know the registers that need to be modified for proper operation with a higher coverage class, then we can do these modifications from the driver. This is a hack and might cause subtle problems but as it's not enabled by default (only when user space changes the coverage class explicitly) it should not cause new problems for existing setups. But still this should be considered as an experimental feature and used with caution. This patch implements the support for first generation cards (QCA9880, QCA9887 and so on) which are based on a core that is similar to ath9k. The registers are modified in place and need to be re-written every time the firmware sets them. To achieve this the register status is verified after certain WMI events from the firmware. The coverage class may not be modified temporarily right after the card re-initializes the registers. This is for example the case during scanning. Thanks to Sebastian Gottschall <s.gottschall@dd-wrt.com> for initially working on a userspace support for this. This patch wouldn't have been possible without this documentation. Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Simon Wunderlich <sw@simonwunderlich.de> Signed-off-by: Mathias Kretschmer <mathias.kretschmer@fit.fraunhofer.de> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-27ath10k: fix rfc1042 header retrieval in QCA4019 with eth decap modeVasanthakumar Thiagarajan
Chipset from QCA99X0 onwards (QCA99X0, QCA9984, QCA4019 & future) rx_hdr_status is not padded to align in 4-byte boundary. Define a new hw_params field to handle different alignment behaviour between different hw. This patch fixes improper retrieval of rfc1042 header with QCA4019. This patch along with "ath10k: Properly remove padding from the start of rx payload" will fix traffic failure in ethernet decap mode for QCA4019. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-27ath10k: spelling and miscellaneous neateningJoe Perches
Correct some trivial comment typos. Remove unnecessary parentheses in a long line. Signed-off-by: Joe Perches <joe@perches.com> [kvalo@qca.qualcomm.com: drop the change for return] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-13ath10k: remove 4-addr padding related hw_param configurationVasanthakumar Thiagarajan
hw_4addr_pad was added to handle different types of padding in 4-address rx frame. But this padding is not very specific to 4-address, it can happen even with three address + ethernet decap mode. Since the padding information can be obtained through Rx desc for QCA99X0 and newer chips, this hw_param is not needed any more. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-13ath10k: properly remove padding from the start of rx payloadVasanthakumar Thiagarajan
In QCA99X0 (QCA99X0, QCA9984, QCA9888 and QCA4019) family chips, hw adds padding at the begining of the rx payload to make L3 header 4-byte aligned. In the chips doing this type of padding, the number of bytes padded will be indicated through msdu_end:info1. Define a hw_rx_desc_ops wrapper to retrieve the number of padded bytes and use this while doing undecap. This should fix padding related issues with ethernt decap format with QCA99X0, QCA9984, QCA9888 and QCA4019 hw. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-13ath10k: add provision for Rx descriptor abstractionVasanthakumar Thiagarajan
There are slight differences in Rx hw descriptor information among different chips. So far driver does not use those new information for any functionalities, but there is one important information which is available from QCA99X0 onwards to indicate the number of bytes that hw padded at the begining of the rx payload and this information is needed to undecap the rx packet. Add an abstraction for Rx desc to make use of the new desc information available. The callback that this patch defines to retrieve the padding bytes will be used in follow-up patch. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [Rename operations to hw_ops for other purposes] Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-09-13ath10k: move ath10k_hw_params definition to hw.hVasanthakumar Thiagarajan
This is to prepare for rx descriptor abstraction where we'll be dereferencing ath10k_hw_params member in hw.h. Moreover hw.h looks more suitable to house ath10k_hw_params definition than core.h Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-07-08ath10k: enable support for QCA9888Anilkumar Kolli
QCA9888 shares the same configuration with QCA99X0 with NSS=2. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-07-08ath10k: remove unused member in ath10k_hw_regsAnilkumar Kolli
rtc_state_cold_reset_mask is unused in ath10k_hw_regs. instead fixed delays are used. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-07-08ath10k: simplify pktlog htt event processingAshok Raj Nagarajan
It is expected that all pktlog events for 10.4 firmware based solutions should come through CE8 where as in case of 10.2 firmware based solutions, it should come through one of the HTT events (HTT_T2H_MSG_TYPE_PKTLOG). But from experiments with 10.4 based solutions, it is observed that pktlog event for ATH_PKTLOG_TYPE_TX_MSDU_ID is coming through HTT pktlog event. Currently, we always parse with 10.2 pktlog header which will lead to pktlog decoding issues (payload length mismatch exceptions) For trace points, it is required to provide only the payload size. So fixing this by simplifying the payload size calculation without the use of ath10k pktlog headers. While there, remove the unused ath10k pktlog headers. Signed-off-by: Ashok Raj Nagarajan <arnagara@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-14ath10k: fix cycle counter wraparound handling for QCA4019Vasanthakumar Thiagarajan
In QCA4019, cycle counter wraparound is not tied to rx clear counter. Each counter would wraparound individually and after wraparound the respective counter will be reset to 0x7fffffff while other counter still running unaffected. Define a new wraparound type for this behaviour and handle it separately so that rx clear counter wraparound is also handled just like cycle counter. With this type of wraparound we can accurately compute and report channel active/busy time when any of the counter overflows. Fixes: ee9ca147c59 ("ath10k: Fix survey reporting with QCA4019") Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-14ath10k: define an enum to enable cycle counter wraparound logicVasanthakumar Thiagarajan
QCA988X hw implements a different cycle counter wraparound behaviour when compared to QCA4019. To properly handle different wraparound logic for these chipsets replace already available bool hw_params member, has_shifted_cc_wraparound, with an enum which could be extended to handle different wraparound behaviour. This patch keeps the existing logic functionally same and a prepares cycle counter wraparound handling to extend for other chips. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [kvalo@qca.qualcomm.com: change also QCA9887 wrap type] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-14ath10k: fix CCK h/w rates for QCA99X0 and newer chipsetsMohammed Shafi Shajakhan
CCK hardware table mapping from QCA99X0 onwards got revised. The CCK hardware rate values are in a proper order wrt. to rate and preamble as below ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, ATH10K_HW_RATE_REV2_CCK_LP_2M = 2, ATH10K_HW_RATE_REV2_CCK_LP_5_5M = 3, ATH10K_HW_RATE_REV2_CCK_LP_11M = 4, ATH10K_HW_RATE_REV2_CCK_SP_2M = 5, ATH10K_HW_RATE_REV2_CCK_SP_5_5M = 6, ATH10K_HW_RATE_REV2_CCK_SP_11M = 7, This results in reporting of rx frames (with CCK rates) totally wrong for QCA99X0, QCA4019. Fix this by having separate CCK rate table for these chipsets with rev2 suffix and registering the correct rate mapping to mac80211 based on the new hw_param (introduced) 'cck_rate_map_rev2' which shall be true for any newchipsets from QCA99X0 onwards Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-07ath10k: add board data download from targetSven Eckelmann
The QCA9887 stores its calibration data (board.bin) inside the EEPROM of the target. This has to be downloaded manually to allow the device to initialize correctly. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> [kvalo@qca.qualcomm.com: handle -EOPNOTSUPP and s/fetch_board_data/fetch_cal_eeprom] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-07ath10k: add QCA9887 chipset supportSven Eckelmann
Add the hardware name, revision, firmware names and update the pci_id table. QA9887 HW1.0 is supposed to be similar to QCA988X HW2.0 . Details about he firmware interface are currently unknown. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> [kvalo@qca.qualcomm.com: add a warning about experimental support] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-24ath10k: enable support for QCA9984Vasanthakumar Thiagarajan
QCA9984 shares the same configuration with QCA99X0. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-04-20ath10k: remove deprecated firmware API 1 supportKalle Valo
This has ben deprecated years ago, I haven't heard anyone using it since and most likely it won't even work anymore. So just remove all of it. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-03-23ath10k: move cal data len to hw_paramsRaja Mani
ath10k_download_cal_dt() compares obtained cal data content length against QCA988X_CAL_DATA_LEN (2116 bytes). It was written by keeping qca988x in mind. In fact, cal data length is more chip specific. To make ath10k_download_cal_dt() more generic and reusable for other chipsets (like qca4019), cal data length is moved to hw_params. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-03-06ath10k: change htt tx desc/qcache peer limit configMichal Kazior
The number of HTT Tx descriptors and qcache peer limit aren't hw-specific. In fact they are firmware specific and should not be placed in hw_params. The QCA4019 limits were submitted with the peer flow control firmware only and to my understanding there's no non-peer-flow-ctrl QCA4019 firmware. However QCA99X0 is planned to run firmware supporting the feature as well. Therefore this patch enables QCA99X0 to use 2500 tx descriptors whenever possible instead of just 1424. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-03-03ath10k: reduce number of peers to support peer stats featureAnilkumar Kolli
To enable per peer stats feature we are reducing the number of peers. Firmware has introduced tx stats feature. We have memory limitation in firmware to add these additional bytes. These are the new variables introduced in the firmware. ======== ======================= Variable Bytes required/per rate ======== ======================= TX success packets 1 TX failed packets 1 Retry packets 1 Success bytes 2 TX failed bytes 2 Retry bytes 2 Tx duration 4 Rate 1 Bw and AMPDU flags 1 Total 16 (because of allocation in word pattern) Firmware sends these tx_stats in pktlog. If we consider 4 feedbacks at a time, Frimware need about ~1K memory for coding and 8192 bytes required / per rate [ 4*16*128(peers)]. To accommodate this firmware needs to reduce 10 peers. This fixes a firmware crash with firmware-5.bin_10.2.4.70.22-2. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-02-02ath10k: populate qca4019 fw specific wmi init paramsRaja Mani
Some of the parameter like tx/rx chain mask, number of htt tx desc, qcache active peer count, etc goes via wmi init cmd to qca4019 firmware are different. To make use of 10.4 gen_init function for qca4019, change wmi service ready handler and 10.4 wmi init functions to adapt qca4019 specific init values. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-02-02ath10k: add qca4019 hw paramsRaja Mani
Add a new entry in hw_params_list for qca4019 with list of it's own details. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-01-28ath10k: expose hif ops for ahbRaja Mani
Like how pci.c exposes hif ops for the bus specific operation, expose similar hif ops table for ahb with all required functions linked to it. Many ath10k_pci_* functions are reused here in hif ops table. If something is not sharable, new functions are added for ahb and linked to hif ops table. Finally, make ath10k_ahb_probe/remove() to perform what is expected out of it. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-01-28ath10k: include qca4019 register map tableRaja Mani
New register table is added for qca4019 to tell about it's register mapping details. Nothing much other than this. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-01-28ath10k: add basic skeleton to support ahbRaja Mani
qca4019 uses ahb instead of pci where it slightly differs in device enumeration, clock control, reset control, etc. Good thing is that ahb also uses copy engine for the data transaction. So, the most of the stuff implemented in pci.c/ce.c are reusable in ahb case too. Device enumeration in ahb case comes through platform driver/device model. All resource details like irq, memory map, clocks, etc for qca4019 can be fetched from of_node of platform device. Simply flow would look like, device tree => platform device (kernel) => platform driver (ath10k) Device tree entry will have all qca4019 resource details and the same info will be passed to kernel. Kernel will prepare new platform device for that entry and expose DT info to of_node in platform device. Later, ath10k would register platform driver with unique compatible name and then kernels binds to corresponding compatible entry & calls ath10k ahb probe functions. From there onwards, ath10k will take control of it and move forward. New bool flag CONFIG_ATH10K_AHB is added in Kconfig to conditionally enable ahb support in ath10k. On enabling this flag, ath10k_pci.ko will have ahb support. This patch adds only basic skeleton and few macros to support ahb in the context of qca4019. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-12-08Merge tag 'wireless-drivers-next-for-davem-2015-12-07' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Vallo says: ==================== brcfmac * support bcm4359 which can operate in two bands concurrently * disable runtime pm for USB avoiding issues * use generic pm callback in PCIe driver * support wowlan wake indication reporting * add beamforming support * unified handling of firmware files ath10k * support Manegement Frame Protection (MFP) * add thermal throttling support for 10.4 firmware * add support for pktlog in QCA99X0 * add debugfs file to enable Bluetooth coexistence feature * use firmware's native mesh interface type instead of raw mode iwlwifi * BT coex improvements * D3 operation bugfixes * rate control improvements * firmware debugging infra improvements * ground work for multi Rx * various security fixes ==================== Conflicts: drivers/net/wireless/ath/ath10k/pci.c The conflict resolution at: http://article.gmane.org/gmane.linux.kernel.next/37391 by Stephen Rothwell was used. Signed-off-by: David S. Miller <davem@davemloft.net>
2015-11-23ath10k: adjust the RX packet pad offset at QCA99X0 4addr modeYanbo Li
The QCA99X0 4 addresses RX packets pad 2 bytes at the beginning of MSDU instead the end of ieee80211 header to keep alignment. The currently RX data path can't parse the header correctly in this case. This patch fixes it for QCA99X0. Signed-off-by: Yanbo Li <yanbol@qca.qualcomm.com> [kvalo@qca.qualcomm.com: checkpatch fixes and naming changes] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-11-12ath10k: add QCA9377 hw1.0 supportBartosz Markowski
Add new BMI target version and chip id revision. Register it on supported chips list. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-11-12ath10k: introduce dev_id to hw_paramsBartosz Markowski
A follow up patch introducing a QCA9377 hw1.0 support will need this device identification helper for an explicit distinction of HWs, as apparently both QCA6174 hw3.0 and QCA9377 share the same BMI target version (0x0502000x). For the QCA9377 hw1.1 previously added we were just lucky we did not overlap with the same chip_id_rev. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-11-12ath10k: fix the currently supported QCA9377 target version nameBartosz Markowski
When introducing the original QCA9377 support, the chip target version was wrongly picked. The chip advertising itself with bmi target value equal to 0x05020001 is in fact a 1.1 revision. I realized this once I got a real 1.1 hw to play with. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-11-04ath10k: add support for pktlog in QCA99X0Vivek Natarajan
This patch adds pktlog support for 10.4 fw versions. Signed-off-by: Vivek Natarajan <nataraja@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-10-29ath10k: add QCA9377 chipset supportBartosz Markowski
Add the hardware name, revision and update the pci_id table. Currently there're two HW ref. designs available I'm aware of, with 1.0.2 and 1.1 chip revisions. I've access and been using the first one so far and this patch cover only it. QCA9377 inherits most of the stuff (e.g. fw interfaces) from QCA61x4 design, so the integration was pretty straightforward. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-10-29ath10k: add FW API support to test modeAlan Liu
Add WMI-TLV and FW API support in ath10k testmode. Ath10k can get right wmi command format from UTF image to communicate UTF firmware. Signed-off-by: Alan Liu <alanliu@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-10-27Merge tag 'wireless-drivers-next-for-davem-2015-10-27' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Valo says: ==================== here's a bigger pull request for 4.4. The diffstat looks scary as we created a new directory realtek for all realtek drivers. In the future I'm planning to create similar directories for all vendors, currently we just have ath, mediatek and realtek. This change has been in linux-next for a couple of weeks so it should be safe, but of course you never know. There's also a new driver rtl8xxxu for few realtek USB devices. This just made it to the last linux-next build. Otherwise there's nothing really special, more info below. If time permits, and it's ok for you, I'm hoping to send you a one more pull request this week. brcmfmac * using netdev carrier state * add and rework some cfg80211 callbacks mainly for AP mode * use devcoredump when triggered by firmware event realtek * create new directory drivers/net/wireless/realtek/ for all realtek drivers, not visible to users (no kconfig changes etc) * add rtl8xxxu, a new mac80211 driver for RTL8723AU, RTL8188CU, RTL8188RU, RTL8191CU, RTL8192CU and hopefully more in the future ath10k * add board 2 API support for automatically choosing correct board file * data path optimisations * disable PCI power save for qca988x and QCA99x0 due to interop reasons wil6210 * BlockAckReq support * firmware crashdump using devcoredump * capture all frames with sniffer ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-20Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Conflicts: drivers/net/usb/asix_common.c net/ipv4/inet_connection_sock.c net/switchdev/switchdev.c In the inet_connection_sock.c case the request socket hashing scheme is completely different in net-next. The other two conflicts were overlapping changes. Signed-off-by: David S. Miller <davem@davemloft.net>
2015-10-14ath10k: add board 2 API supportManikanta Pubbisetty
QCA6174 needs different board files based on board type. To make it easier to distribute multiple board files and automatically choose correct board file create a simple TLV file format following the same principles as with FW IEs. The file is named board-2.bin and contain multiple board files. Each board file then can have multiple names. ath10k searches for file board-N.bin (where N is the interface version number for the board file, just like we for firmware files) in /lib/firmware/*, for example for qca99x0 it will try to find it here: /lib/firmware/ath10k/QCA99X0/hw2.0/board-2.bin If ath10k doesn't find board-2.bin then it will fallback to the old board.bin file. This patch adds a simple name scheme using pci device id which for now will be used by qca6174: bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x This removes the old method of having subsystem ids in ar->spec_board_id and using that in the board file name. Signed-off-by: Manikanta Pubbisetty <c_mpubbi@qti.qualcomm.com> [kvalo@qca.qualcomm.com: simplified the file format, rewrote commit log, other smaller changes] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-09-27ath10k: fix MSI-X registering for qca99x0Janusz Dziedzic
In case of qca99x0 and MSI-X supported/enabled we failed during interrupts registering with message: ath10k_pci 0000:04:00.0: failed to request MSI-X ce irq 50: -22 Issue/fix was reproduced/tested using Dell Latitude E6430 laptop. Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-09-26ath10k: fix DMA related firmware crashes on multiple devicesFelix Fietkau
Some platforms really don't like DMA bursts of 256 bytes, and this causes the firmware to crash when sending beacons. Also, changing this based on the firmware version does not seem to make much sense, so use 128 bytes for all versions. Cc: stable@vger.kernel.org Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-08-17ath10k: add cycle/rx_clear counters frequency to hw_paramsVasanthakumar Thiagarajan
The frequency at which cycle/rx_clear counters are running might change from one target type to another. QCA99X0 is running the counters at 150Mhz while QCA9888X and QCA6174 are running at 88Mhz. Add a new entry to hw_params to store the target specific frequency and use it in msecs conversion. This change fixes inconsistent channel active/busy time. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-07-30ath10k: increase max client to 512 in qca99x0Raja Mani
When max client was set to 512 in qca99x0, there was host memory alloc failure during wmi service ready event handling. This issue got resolved now, increasing max client limit from 256 to 512. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-07-29ath10k: enable raw encap mode and software crypto engineDavid Liu
This patch enables raw Rx/Tx encap mode to support software based crypto engine. This patch introduces a new module param 'cryptmode'. cryptmode: 0: Use hardware crypto engine globally with native Wi-Fi mode TX/RX encapsulation to the firmware. This is the default mode. 1: Use sofware crypto engine globally with raw mode TX/RX encapsulation to the firmware. Known limitation: A-MSDU must be disabled for RAW Tx encap mode to perform well when heavy traffic is applied. Testing: (by Michal Kazior <michal.kazior@tieto.com>) a) Performance Testing cryptmode=1 ap=qca988x sta=killer1525 killer1525 -> qca988x 194.496 mbps [tcp1 ip4] killer1525 -> qca988x 238.309 mbps [tcp5 ip4] killer1525 -> qca988x 266.958 mbps [udp1 ip4] killer1525 -> qca988x 477.468 mbps [udp5 ip4] qca988x -> killer1525 301.378 mbps [tcp1 ip4] qca988x -> killer1525 297.949 mbps [tcp5 ip4] qca988x -> killer1525 331.351 mbps [udp1 ip4] qca988x -> killer1525 371.528 mbps [udp5 ip4] ap=killer1525 sta=qca988x qca988x -> killer1525 331.447 mbps [tcp1 ip4] qca988x -> killer1525 328.783 mbps [tcp5 ip4] qca988x -> killer1525 375.309 mbps [udp1 ip4] qca988x -> killer1525 403.379 mbps [udp5 ip4] killer1525 -> qca988x 203.689 mbps [tcp1 ip4] killer1525 -> qca988x 222.339 mbps [tcp5 ip4] killer1525 -> qca988x 264.199 mbps [udp1 ip4] killer1525 -> qca988x 479.371 mbps [udp5 ip4] Note: - only open network tested for RAW vs nwifi performance comparison - killer1525 (qca6174 hw2.2) is 2x2 device (hence max 866mbps) - used iperf - OTA, devices a few cm apart from each other, no shielding - tcpX/udpX, X - means number of threads used Overview: - relative Tx performance drop is seen but is within reasonable and expected threshold (A-MSDU must be disabled with RAW Tx) b) Connectivity Testing cryptmode=1 ap=iwl6205 sta1=qca988x crypto=open topology-1ap1sta OK ap=iwl6205 sta1=qca988x crypto=wep1 topology-1ap1sta OK ap=iwl6205 sta1=qca988x crypto=wpa topology-1ap1sta OK ap=iwl6205 sta1=qca988x crypto=wpa-ccmp topology-1ap1sta OK ap=qca988x sta1=iwl6205 crypto=open topology-1ap1sta OK ap=qca988x sta1=iwl6205 crypto=wep1 topology-1ap1sta OK ap=qca988x sta1=iwl6205 crypto=wpa topology-1ap1sta OK ap=qca988x sta1=iwl6205 crypto=wpa-ccmp topology-1ap1sta OK ap=iwl6205 sta1=qca988x crypto=open topology-1ap1sta2br OK ap=iwl6205 sta1=qca988x crypto=wep1 topology-1ap1sta2br OK ap=iwl6205 sta1=qca988x crypto=wpa topology-1ap1sta2br OK ap=iwl6205 sta1=qca988x crypto=wpa-ccmp topology-1ap1sta2br OK ap=qca988x sta1=iwl6205 crypto=open topology-1ap1sta2br OK ap=qca988x sta1=iwl6205 crypto=wep1 topology-1ap1sta2br OK ap=qca988x sta1=iwl6205 crypto=wpa topology-1ap1sta2br OK ap=qca988x sta1=iwl6205 crypto=wpa-ccmp topology-1ap1sta2br OK ap=iwl6205 sta1=qca988x crypto=open topology-1ap1sta2br1vlan OK ap=iwl6205 sta1=qca988x crypto=wep1 topology-1ap1sta2br1vlan OK ap=iwl6205 sta1=qca988x crypto=wpa topology-1ap1sta2br1vlan OK ap=iwl6205 sta1=qca988x crypto=wpa-ccmp topology-1ap1sta2br1vlan OK ap=qca988x sta1=iwl6205 crypto=open topology-1ap1sta2br1vlan OK ap=qca988x sta1=iwl6205 crypto=wep1 topology-1ap1sta2br1vlan OK ap=qca988x sta1=iwl6205 crypto=wpa topology-1ap1sta2br1vlan OK ap=qca988x sta1=iwl6205 crypto=wpa-ccmp topology-1ap1sta2br1vlan OK Note: - each test takes all possible endpoint pairs and pings - each pair-ping flushes arp table - ip6 is used c) Testbed Topology: 1ap1sta: [ap] ---- [sta] endpoints: ap, sta 1ap1sta2br: [veth0] [ap] ---- [sta] [veth2] | | | | [veth1] | \ [veth3] \ / \ / [br0] [br1] endpoints: veth0, veth2, br0, br1 note: STA works in 4addr mode, AP has wds_sta=1 1ap1sta2br1vlan: [veth0] [ap] ---- [sta] [veth2] | | | | [veth1] | \ [veth3] \ / \ / [br0] [br1] | | [vlan0_id2] [vlan1_id2] endpoints: vlan0_id2, vlan1_id2 note: STA works in 4addr mode, AP has wds_sta=1 Credits: Thanks to Michal Kazior <michal.kazior@tieto.com> who helped find the amsdu issue, contributed a workaround (already squashed into this patch), and contributed the throughput and connectivity tests results. Signed-off-by: David Liu <cfliu.tw@gmail.com> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Tested-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-07-02ath10k: add 10.4 fw specific htt msg definitionsRaja Mani
New htt event table is added for 10.4 firmware. Following new htt events are available only 10.4. adding this to generic htt event table, HTT_T2H_MSG_TYPE_EN_STATS, HTT_T2H_MSG_TYPE_TX_FETCH_IND, HTT_T2H_MSG_TYPE_TX_FETCH_CONF, HTT_T2H_MSG_TYPE_TX_LOW_LATENCY_IND Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: adjust default peer limits if qcache enabled in 10.4 fwRaja Mani
10.4 firmware supports upto 512 clients when qcache feature is enabled. Make adjustment on default max peer count, active peers, number of tid in such case to meet qcache requirement. 10.4 fw has extra unit info flag NUM_UNITS_IS_NUM_ACTIVE_PEERS which is also handled in this patch. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: fill 10.4 fw wmi init cmd default valuesRaja Mani
Define 10.4 wmi init command structure and introduce new function ath10k_wmi_10_4_op_gen_init() to fill default values for each field which goes as part of wmi init cmd to 10.4 firmware. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: include new wmi op version for 10.4 fwRaja Mani
qca99X0 chip uses firmware version 10.4. Define a new macro ATH10K_FW_WMI_OP_VERSION_10_4 for 10.4 firmware and include in switch cases where ATH10K_FW_WMI_OP_VERSION_* is used to avoid compilation error. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: Add support for code swapVasanthakumar Thiagarajan
Code swap is a mechanism to use host memory to store some fw binary code segment. Ath10k host driver allocates and loads the code swap binary into the host memory and configures the target with the host allocated memory information at the address taken from code swap binary. This patch adds code swap support for firmware binary. Code swap binary for firmware bin is available in ATH10K_FW_IE_FW_CODE_SWAP_IMAGE. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: Extend CE src desc flags for interrupt indicationVasanthakumar Thiagarajan
QCA99X0 uses two new copy engine src desc flags for interrupt indication. Bit_2 is to mark if host interrupt is disabled after processing the current desc and bit_3 is to mark if target interrupt is diabled after the processing of current descriptor. CE_DESC_FLAGS_META_DATA_MASK and CE_DESC_FLAGS_META_DATA_LSB are based on the target type. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-06-30ath10k: Copy Engine related changes for QCA99X0Vasanthakumar Thiagarajan
QCA99X0 supports upto 12 Copy engines. Host and target CE configuration table is updated to support new copy engine pipes. This also fixes the assumption of diagnostic CE by making CE_7 as the one instead of CE_COUNT - 1. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-19 16:06:46 +0000