From 859161b952a453b86362f168fadef72a8ba31a05 Mon Sep 17 00:00:00 2001 From: Stanislav Lisovskiy Date: Tue, 14 Jun 2022 15:30:49 +0300 Subject: drm/i915/dg2: Bump up CDCLK for DG2 We seem to need this W/A same way as for TGL, in order to fix some of the underruns, which we currently have and those not related to PSR. Signed-off-by: Stanislav Lisovskiy Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20220614123049.16183-2-stanislav.lisovskiy@intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 6e80162632dd..86a22c3766e5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2300,7 +2300,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); /* - * HACK. Currently for TGL platforms we calculate + * HACK. Currently for TGL/DG2 platforms we calculate * min_cdclk initially based on pixel_rate divided * by 2, accounting for also plane requirements, * however in some cases the lowest possible CDCLK @@ -2308,7 +2308,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * Explicitly stating here that this seems to be currently * rather a Hack, than final solution. */ - if (IS_TIGERLAKE(dev_priv)) { + if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { /* * Clamp to max_cdclk_freq in case pixel rate is higher, * in order not to break an 8K, but still leave W/A at place. -- cgit v1.2.3 From 75f664903d8672897333b86bb450335ec6486ad5 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Mon, 11 Jul 2022 14:17:50 +0300 Subject: drm/i915/display: Ensure PSR gets disabled if no encoders in new state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently PSR is left enabled when all planes are disabled if there is no attached encoder in new state. This seems to be causing FIFO underruns. Fix this by checking if encoder exists in new crtc state and disable PSR if it doesn't. v2: Unify disable logic with existing Cc: Mika Kahola Reported-by: Stanislav Lisovskiy Signed-off-by: Jouni Högander Signed-off-by: Stanislav Lisovskiy Reviewed-by: Stanislav Lisovskiy Signed-off-by: Stanislav Lisovskiy Link: https://patchwork.freedesktop.org/patch/msgid/20220711111750.881552-1-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 53 +++++++++++++++++++------------- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e6a870641cd2..90599dd1cb1b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1863,36 +1863,45 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - struct intel_encoder *encoder; + struct intel_crtc_state *new_crtc_state, *old_crtc_state; + int i; if (!HAS_PSR(i915)) return; - for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, - crtc_state->uapi.encoder_mask) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_psr *psr = &intel_dp->psr; - bool needs_to_disable = false; + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + struct intel_encoder *encoder; + u32 old_new_encoder_mask = old_crtc_state->uapi.encoder_mask | + new_crtc_state->uapi.encoder_mask; - mutex_lock(&psr->lock); + for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, + old_new_encoder_mask) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_psr *psr = &intel_dp->psr; + bool needs_to_disable = false; - /* - * Reasons to disable: - * - PSR disabled in new state - * - All planes will go inactive - * - Changing between PSR versions - */ - needs_to_disable |= intel_crtc_needs_modeset(crtc_state); - needs_to_disable |= !crtc_state->has_psr; - needs_to_disable |= !crtc_state->active_planes; - needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; + mutex_lock(&psr->lock); - if (psr->enabled && needs_to_disable) - intel_psr_disable_locked(intel_dp); + /* + * Reasons to disable: + * - PSR disabled in new state + * - All planes will go inactive + * - Changing between PSR versions + * - Encoder isn't present in new mask + */ + needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); + needs_to_disable |= !new_crtc_state->has_psr; + needs_to_disable |= !new_crtc_state->active_planes; + needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; + needs_to_disable |= !(new_crtc_state->uapi.encoder_mask & + drm_encoder_mask(&(encoder)->base)); - mutex_unlock(&psr->lock); + if (psr->enabled && needs_to_disable) + intel_psr_disable_locked(intel_dp); + + mutex_unlock(&psr->lock); + } } } -- cgit v1.2.3 From 81cb44274c654e49f55e6690079540b0bd177db0 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 8 Jul 2022 14:58:04 -0700 Subject: drm/i915: Add Wa_14016291713 We already disable FBC when PSR2 is enabled on display version 12 and above; this new workaround now requires that we do the same with PSR1 on display versions 12 and 13. Signed-off-by: Matt Roper Reviewed-by: Arun R Murthy Link: https://patchwork.freedesktop.org/patch/msgid/20220708215804.2889246-2-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 8b807284cde1..33f52feb622a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1097,6 +1097,12 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } + /* Wa_14016291713 */ + if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) { + plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; + return 0; + } + if (!pixel_format_is_valid(plane_state)) { plane_state->no_fbc_reason = "pixel format not supported"; return 0; -- cgit v1.2.3 From c19491894d4baf2155387e48aa326e1b52d7b986 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 17 Jun 2022 14:28:07 +0300 Subject: drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order Starting with TGL the disabling order of HDMI transcoder clock vs. DDI BUF has swapped, fix this. There hasn't been any issues seen related to this, but let's follow the spec. Reported-by: Sandeep K Lakkakula Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f76eb6e345ec..ec131973f374 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); - intel_ddi_disable_pipe_clock(old_crtc_state); + if (DISPLAY_VER(dev_priv) < 12) + intel_ddi_disable_pipe_clock(old_crtc_state); intel_disable_ddi_buf(encoder, old_crtc_state); + if (DISPLAY_VER(dev_priv) >= 12) + intel_ddi_disable_pipe_clock(old_crtc_state); + intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain, fetch_and_zero(&dig_port->ddi_io_wakeref)); -- cgit v1.2.3 From ad444123a4a1d2944bd72fc877af9aabef01b889 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 14 Jul 2022 08:07:54 -0700 Subject: Revert "drm/i915/display: Ensure PSR gets disabled if no encoders in new state" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patches fixes a issue but not in the right way as for_each_oldnew_intel_crtc_in_state() will interate over all CRTCs not only the crtc passed as parameter, also this two for_each loops are not necessary and only make code harder to understand. Proper fix will be discussed in the next patch. This reverts commit 75f664903d8672897333b86bb450335ec6486ad5. Cc: Jouni Högander Cc: Stanislav Lisovskiy Signed-off-by: José Roberto de Souza Reviewed-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20220714150755.154985-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 53 +++++++++++++------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 90599dd1cb1b..e6a870641cd2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1863,45 +1863,36 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - struct intel_crtc_state *new_crtc_state, *old_crtc_state; - int i; + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_encoder *encoder; if (!HAS_PSR(i915)) return; - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { - struct intel_encoder *encoder; - u32 old_new_encoder_mask = old_crtc_state->uapi.encoder_mask | - new_crtc_state->uapi.encoder_mask; - - for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, - old_new_encoder_mask) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_psr *psr = &intel_dp->psr; - bool needs_to_disable = false; + for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_psr *psr = &intel_dp->psr; + bool needs_to_disable = false; - mutex_lock(&psr->lock); + mutex_lock(&psr->lock); - /* - * Reasons to disable: - * - PSR disabled in new state - * - All planes will go inactive - * - Changing between PSR versions - * - Encoder isn't present in new mask - */ - needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); - needs_to_disable |= !new_crtc_state->has_psr; - needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; - needs_to_disable |= !(new_crtc_state->uapi.encoder_mask & - drm_encoder_mask(&(encoder)->base)); + /* + * Reasons to disable: + * - PSR disabled in new state + * - All planes will go inactive + * - Changing between PSR versions + */ + needs_to_disable |= intel_crtc_needs_modeset(crtc_state); + needs_to_disable |= !crtc_state->has_psr; + needs_to_disable |= !crtc_state->active_planes; + needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; - if (psr->enabled && needs_to_disable) - intel_psr_disable_locked(intel_dp); + if (psr->enabled && needs_to_disable) + intel_psr_disable_locked(intel_dp); - mutex_unlock(&psr->lock); - } + mutex_unlock(&psr->lock); } } -- cgit v1.2.3 From 031a2fea0482965175ad20adea44bdfe6ed817aa Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Thu, 14 Jul 2022 08:07:55 -0700 Subject: drm/i915/psr: Disable PSR before disable pipe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The issue here was on for_each_intel_encoder_mask_with_psr() over the new_crtc_state encoder mask, so if the CRTC was being disabled mask would be zero and it would not have any chance to disable PSR. So here doing for_each_intel_encoder_mask_with_psr() over the old_crtc_state encoder mask and then using the new_crtc_state to check if PSR needs to be disabled. Cc: Jouni Högander Cc: Stanislav Lisovskiy Signed-off-by: José Roberto de Souza Reviewed-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20220714150755.154985-2-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e6a870641cd2..98c3c8015a5c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1863,7 +1863,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_crtc_state *crtc_state = + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_encoder *encoder; @@ -1871,7 +1873,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, return; for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, - crtc_state->uapi.encoder_mask) { + old_crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_psr *psr = &intel_dp->psr; bool needs_to_disable = false; @@ -1884,10 +1886,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, * - All planes will go inactive * - Changing between PSR versions */ - needs_to_disable |= intel_crtc_needs_modeset(crtc_state); - needs_to_disable |= !crtc_state->has_psr; - needs_to_disable |= !crtc_state->active_planes; - needs_to_disable |= crtc_state->has_psr2 != psr->psr2_enabled; + needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); + needs_to_disable |= !new_crtc_state->has_psr; + needs_to_disable |= !new_crtc_state->active_planes; + needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; if (psr->enabled && needs_to_disable) intel_psr_disable_locked(intel_dp); -- cgit v1.2.3 From 9899834ae5f26649da09e0cae72d8d9eb8a07aab Mon Sep 17 00:00:00 2001 From: Swati Sharma Date: Wed, 6 Jul 2022 15:52:40 +0530 Subject: drm/i915/display: Add debug print for scaler filter Add debug print statement to print scaler filter property value. Since property can be set as either default or integer scaler; its good if we can get debug print for the same in dmesg log. Cc: Juha-Pekka Heikkila Signed-off-by: Swati Sharma Reviewed-by: Uma Shankar Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20220706102240.21414-1-swati2.sharma@intel.com --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++-- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 4ca6e9493ff2..e9212f69c360 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -134,8 +134,8 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state) plane->base.base.id, plane->base.name, fb->base.id, fb->width, fb->height, &fb->format->format, fb->modifier, str_yes_no(plane_state->uapi.visible)); - drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", - plane_state->hw.rotation, plane_state->scaler_id); + drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", + plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); if (plane_state->uapi.visible) drm_dbg_kms(&i915->drm, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", @@ -262,10 +262,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, if (DISPLAY_VER(i915) >= 9) drm_dbg_kms(&i915->drm, - "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", + "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", crtc->num_scalers, pipe_config->scaler_state.scaler_users, - pipe_config->scaler_state.scaler_id); + pipe_config->scaler_state.scaler_id, + pipe_config->hw.scaling_filter); if (HAS_GMCH(i915)) drm_dbg_kms(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 452d773fd4e3..a770c1bb2665 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -720,10 +720,11 @@ static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) /* Not all platformas have a scaler */ if (num_scalers) { - seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", + seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d scaling_filter=%d", num_scalers, crtc_state->scaler_state.scaler_users, - crtc_state->scaler_state.scaler_id); + crtc_state->scaler_state.scaler_id, + crtc_state->hw.scaling_filter); for (i = 0; i < num_scalers; i++) { const struct intel_scaler *sc = -- cgit v1.2.3 From 3565c7219c169ab6c6ef34ba9187c1b7bc6dbfa5 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 21 Jul 2022 14:16:45 +0530 Subject: drm/i915/hdmi: Prune modes that require HDMI2.1 FRL HDMI2.1 requires some higher resolution video modes to be enumerated only if HDMI2.1 Fixed Rate Link (FRL) is supported. Current platforms do not support FRL transmission so prune modes that require HDMI2.1 FRL. v2: Fixed the condition to check for dotclock > 600. Return MODE_CLOCK_HIGH as mode status. Signed-off-by: Ankit Nautiyal Reviewed-by: Arun R Murthy (v1) Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20220721084645.3411219-1-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index cb6898cbe1c8..872316ef895e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2000,6 +2000,15 @@ intel_hdmi_mode_valid(struct drm_connector *connector, clock *= 2; } + /* + * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be + * enumerated only if FRL is supported. Current platforms do not support + * FRL so prune the higher resolution modes that require doctclock more + * than 600MHz. + */ + if (clock > 600000) + return MODE_CLOCK_HIGH; + ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); -- cgit v1.2.3