From c98459cf6d8d26ff0989eb5aae5a4b9f261d58c6 Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:12 +0100 Subject: MAINTAINERS: Add maintainers for Keem Bay SoC Add maintainers for the new Intel Movidius SoC code-named Keem Bay. Link: https://lore.kernel.org/r/20200717090414.313530-4-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 7b5ffd646c6b..fd46dfc88c50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1954,6 +1954,12 @@ F: drivers/irqchip/irq-ixp4xx.c F: include/linux/irqchip/irq-ixp4xx.h F: include/linux/platform_data/timer-ixp4xx.h +ARM/INTEL KEEMBAY ARCHITECTURE +M: Paul J. Murphy +M: Daniele Alessandrelli +S: Maintained +F: Documentation/devicetree/bindings/arm/intel,keembay.yaml + ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- cgit v1.2.3 From 0a6e92f26784b8c6a9d24c26da7278a7362531ee Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:13 +0100 Subject: arm64: dts: keembay: Add device tree for Keem Bay SoC Add initial device tree for Intel Movidius SoC code-named Keem Bay. This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI, and PMU. Link: https://lore.kernel.org/r/20200717090414.313530-5-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 +++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index fd46dfc88c50..5bcd1c412f0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/intel,keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-soc.dtsi ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT M: Jonathan Cameron diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi new file mode 100644 index 000000000000..781761d2942b --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation. + * + * Device tree describing Keem Bay SoC. + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@20500000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ + <0x0 0x20580000 0x0 0x80000>; /* GICR */ + /* VGIC maintenance interrupt */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Secure, non-secure, virtual, and hypervisor */ + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@20150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20150000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@20160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20160000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20170000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@20180000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x20180000 0x0 0x100>; + interrupts = ; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From d846abff949d346ffc0fe31d492c2af00ea40e2e Mon Sep 17 00:00:00 2001 From: Daniele Alessandrelli Date: Fri, 17 Jul 2020 10:04:14 +0100 Subject: arm64: dts: keembay: Add device tree for Keem Bay EVM board Add initial device tree for Keem Bay EVM board. With this minimal device tree the board boots fine using an initramfs image. Link: https://lore.kernel.org/r/20200717090414.313530-6-daniele.alessandrelli@linux.intel.com Reviewed-by: Dinh Nguyen Signed-off-by: Daniele Alessandrelli Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/keembay-evm.dts | 37 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 5bcd1c412f0b..f139d9594564 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1959,6 +1959,7 @@ M: Paul J. Murphy M: Daniele Alessandrelli S: Maintained F: Documentation/devicetree/bindings/arm/intel,keembay.yaml +F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 40cb16e8c814..296eceec4276 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb +dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts new file mode 100644 index 000000000000..466c85363a29 --- /dev/null +++ b/arch/arm64/boot/dts/intel/keembay-evm.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) 2020, Intel Corporation + * + * Device tree describing Keem Bay EVM board. + */ + +/dts-v1/; + +#include "keembay-soc.dtsi" + +/ { + model = "Keem Bay EVM"; + compatible = "intel,keembay-evm", "intel,keembay"; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2GB of DDR memory. */ + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + +}; + +&uart3 { + status = "okay"; +}; -- cgit v1.2.3 From 31a91c87a42bf3f7261e5752db5784fa43fbced5 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:34 +0200 Subject: arm64: sparx5: Add support for Microchip 2xA53 SoC This adds support for the Microchip Sparx5 ARMv8-based SoC family of TSN-capable gigabit switches. Link: https://lore.kernel.org/r/20200615133242.24911-3-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- MAINTAINERS | 8 ++++++++ arch/arm64/Kconfig.platforms | 14 ++++++++++++++ 2 files changed, 22 insertions(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index f139d9594564..104972340822 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2119,6 +2119,14 @@ X: drivers/net/wireless/atmel/ N: at91 N: atmel +ARM/Microchip Sparx5 SoC support +M: Lars Povlsen +M: Steen Hegelund +M: Microchip Linux Driver Support +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +N: sparx5 + ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 95c1b9042009..fd9f45a52879 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,20 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. +config ARCH_SPARX5 + bool "ARMv8 based Microchip Sparx5 SoC family" + select PINCTRL + select DW_APB_TIMER_OF + help + This enables support for the Microchip Sparx5 ARMv8-based + SoC family of TSN-capable gigabit switches. + + The SparX-5 Ethernet switch family provides a rich set of + switching features such as advanced TCAM-based VLAN and QoS + processing enabling delivery of differentiated services, and + security through TCAM-based frame processing using versatile + content aware processor (VCAP). + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select PM_GENERIC_DOMAINS if PM -- cgit v1.2.3 From 6694aee00a4b478d2dd82837f39b5dc9cbedfbcf Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Mon, 15 Jun 2020 15:32:35 +0200 Subject: arm64: dts: sparx5: Add basic cpu support This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/microchip/Makefile | 4 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 142 +++++++++++++++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 17 +++ arch/arm64/boot/dts/microchip/sparx5_pcb134.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++ arch/arm64/boot/dts/microchip/sparx5_pcb135.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 10 ++ .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++ .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 +++ 12 files changed, 268 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/Makefile create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 104972340822..fc6b50723c22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2125,6 +2125,7 @@ M: Steen Hegelund M: Microchip Linux Driver Support L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported +F: arch/arm64/boot/dts/microchip/ N: sparx5 ARM/MIOA701 MACHINE SUPPORT diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index f19b762c008d..9680a7f20c30 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -17,6 +17,7 @@ subdir-y += intel subdir-y += lg subdir-y += marvell subdir-y += mediatek +subdir-y += microchip subdir-y += nvidia subdir-y += qcom subdir-y += realtek diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..c6e0313eea0f --- /dev/null +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi new file mode 100644 index 000000000000..4a54b7d03916 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include + +/ { + compatible = "microchip,sparx5"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks: clocks { + #address-cells = <2>; + #size-cells = <1>; + ranges; + ahb_clk: ahb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + sys_clk: sys-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <625000000>; + }; + }; + + axi: axi@600000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@600300000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ + <0x6 0x00340000 0xc0000>, /* GICR */ + <0x6 0x00200000 0x2000>, /* GICC */ + <0x6 0x00210000 0x2000>, /* GICV */ + <0x6 0x00220000 0x2000>; /* GICH */ + interrupts = ; + }; + + uart0: serial@600100000 { + compatible = "ns16550a"; + reg = <0x6 0x00100000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + uart1: serial@600102000 { + compatible = "ns16550a"; + reg = <0x6 0x00102000 0x20>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + + status = "disabled"; + }; + + timer1: timer@600105000 { + compatible = "snps,dw-apb-timer"; + reg = <0x6 0x00105000 0x1000>; + clocks = <&ahb_clk>; + clock-names = "timer"; + interrupts = ; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts new file mode 100644 index 000000000000..d7f985f7ee02 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/ { + model = "Sparx5 PCB125 Reference Board"; + compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts new file mode 100644 index 000000000000..feee4e99ff57 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi new file mode 100644 index 000000000000..005cf6babb9b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts new file mode 100644 index 000000000000..10081a66961b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb134_board.dtsi" + +/ { + model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts new file mode 100644 index 000000000000..20e409a9be19 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (NAND)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi new file mode 100644 index 000000000000..005cf6babb9b --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb_common.dtsi" + +/{ +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 000000000000..741f0e12260e --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi new file mode 100644 index 000000000000..1f99d0db1284 --- /dev/null +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5.dtsi" + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; -- cgit v1.2.3 From 343e8f7286e87f60ef7cc8c8b140e254f550886f Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:37 +0900 Subject: dt-bindings: arm: Add mstar YAML schema Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/mstar.yaml | 33 ++++++++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar.yaml (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/arm/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar.yaml new file mode 100644 index 000000000000..bdce34b3336e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mstar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar platforms device tree bindings + +maintainers: + - Daniel Palmer + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: infinity boards + items: + - enum: + - thingyjp,breadbee-crust # thingy.jp BreadBee Crust + - const: mstar,infinity + + - description: infinity3 boards + items: + - enum: + - thingyjp,breadbee # thingy.jp BreadBee + - const: mstar,infinity3 + + - description: mercury5 boards + items: + - enum: + - 70mai,midrived08 # 70mai midrive d08 + - const: mstar,mercury5 diff --git a/MAINTAINERS b/MAINTAINERS index fc6b50723c22..d9a4418b4733 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2134,6 +2134,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-pxa/mioa701.c +ARM/MStar/Sigmastar Armv7 SoC support +M: Daniel Palmer +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +W: http://linux-chenxing.org/ +F: Documentation/devicetree/bindings/arm/mstar.yaml + ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky S: Maintained -- cgit v1.2.3 From 312b62b6610cabea4cb535fd4889c41e9a84afca Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:38 +0900 Subject: ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs Initial support for the MStar/Sigmastar Armv7 based IP camera and dashcam SoCs. These chips are interesting in that they contain a Cortex-A7, peripherals and system memory in a single tiny QFN package that can be hand soldered allowing almost anyone to embed Linux in their projects. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-mstar/Kconfig | 26 ++++++++++++++ arch/arm/mach-mstar/Makefile | 1 + arch/arm/mach-mstar/mstarv7.c | 80 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 arch/arm/mach-mstar/Kconfig create mode 100644 arch/arm/mach-mstar/Makefile create mode 100644 arch/arm/mach-mstar/mstarv7.c (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index d9a4418b4733..fb7f5310169b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2ac74904a3ce..d54c413ad937 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" +source "arch/arm/mach-mstar/Kconfig" + source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/mach-mvebu/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59fde2d598d8..e7f4ca060c0f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs +machine-$(CONFIG_ARCH_MSTARV7) += mstar machine-$(CONFIG_ARCH_NOMADIK) += nomadik machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig new file mode 100644 index 000000000000..52744fe32368 --- /dev/null +++ b/arch/arm/mach-mstar/Kconfig @@ -0,0 +1,26 @@ +menuconfig ARCH_MSTARV7 + bool "MStar/Sigmastar Armv7 SoC Support" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_HEAVY_MB + help + Support for newer MStar/Sigmastar SoC families that are + based on Armv7 cores like the Cortex A7 and share the same + basic hardware like the infinity and mercury series. + +if ARCH_MSTARV7 + +config MACH_INFINITY + bool "MStar/Sigmastar infinity SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar infinity IP camera SoCs. + +config MACH_MERCURY + bool "MStar/Sigmastar mercury SoC support" + default ARCH_MSTARV7 + help + Support for MStar/Sigmastar mercury dash camera SoCs. + Note that older Mercury2 SoCs are ARM9 based and not supported. + +endif diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile new file mode 100644 index 000000000000..93b0391ede7e --- /dev/null +++ b/arch/arm/mach-mstar/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c new file mode 100644 index 000000000000..81a4cbcab206 --- /dev/null +++ b/arch/arm/mach-mstar/mstarv7.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree support for MStar/Sigmastar Armv7 SoCs + * + * Copyright (c) 2020 thingy.jp + * Author: Daniel Palmer + */ + +#include +#include +#include +#include +#include +#include + +/* + * In the u-boot code the area these registers are in is + * called "L3 bridge" and there are register descriptions + * for something in the same area called "AXI". + * + * It's not exactly known what this is but the vendor code + * for both u-boot and linux share calls to "flush the miu pipe". + * This seems to be to force pending CPU writes to memory so that + * the state is right before DMA capable devices try to read + * descriptors and data the CPU has prepared. Without doing this + * ethernet doesn't work reliably for example. + */ + +#define MSTARV7_L3BRIDGE_FLUSH 0x14 +#define MSTARV7_L3BRIDGE_STATUS 0x40 +#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) +#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) + +static void __iomem *l3bridge; + +static const char * const mstarv7_board_dt_compat[] __initconst = { + "mstar,infinity", + "mstar,infinity3", + "mstar,mercury5", + NULL, +}; + +/* + * This may need locking to deal with situations where an interrupt + * happens while we are in here and mb() gets called by the interrupt handler. + * + * The vendor code did have a spin lock but it doesn't seem to be needed and + * removing it hasn't caused any side effects so far. + * + * [writel|readl]_relaxed have to be used here because otherwise + * we'd end up right back in here. + */ +static void mstarv7_mb(void) +{ + /* toggle the flush miu pipe fire bit */ + writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH); + writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge + + MSTARV7_L3BRIDGE_FLUSH); + while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS) + & MSTARV7_L3BRIDGE_STATUS_DONE)) { + /* wait for flush to complete */ + } +} + +static void __init mstarv7_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge"); + l3bridge = of_iomap(np, 0); + if (l3bridge) + soc_mb = mstarv7_mb; + else + pr_warn("Failed to install memory barrier, DMA will be broken!\n"); +} + +DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") + .dt_compat = mstarv7_board_dt_compat, + .init_machine = mstarv7_init, +MACHINE_END -- cgit v1.2.3 From b0d0bb1b6f8700deaf23e8ea42eaca9c54488fc9 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:40 +0900 Subject: ARM: mstar: Add Armv7 base dtsi Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs. These SoCs have very similar memory maps and this will avoid duplicating nodes across multiple dtsis. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/mstar-v7.dtsi | 83 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-v7.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index fb7f5310169b..ccabe73ce800 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi new file mode 100644 index 000000000000..3b99bb435bb5 --- /dev/null +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + arch_timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + /* + * we shouldn't need this but the vendor + * u-boot is broken + */ + clock-frequency = <6000000>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16001000 0x16001000 0x00007000>, + <0x1f000000 0x1f000000 0x00400000>; + + gic: interrupt-controller@16001000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x16001000 0x1000>, + <0x16002000 0x2000>, + <0x16004000 0x2000>, + <0x16006000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + riu: bus@1f000000 { + compatible = "simple-bus"; + reg = <0x1f000000 0x00400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1f000000 0x00400000>; + + l3bridge: l3bridge@204400 { + compatible = "mstar,l3bridge"; + reg = <0x204400 0x200>; + }; + + pm_uart: uart@221000 { + compatible = "ns16550a"; + reg = <0x221000 0x100>; + reg-shift = <3>; + clock-frequency = <172000000>; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3 From 952c0ed6f96339ae5d0f22154d05f8eac2742c94 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:41 +0900 Subject: ARM: mstar: Add infinity/infinity3 family dtsis This adds two family level dtsis for the infinity and infinity3 and then adds a chip level dtsi each for a chip in those families. infinity3.dtsi includes infinity.dtsi as these SoCs share most of their memory map and we would have a lot of duplication otherwise. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/infinity-msc313.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/infinity.dtsi | 7 +++++++ arch/arm/boot/dts/infinity3-msc313e.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/infinity3.dtsi | 7 +++++++ 5 files changed, 43 insertions(+) create mode 100644 arch/arm/boot/dts/infinity-msc313.dtsi create mode 100644 arch/arm/boot/dts/infinity.dtsi create mode 100644 arch/arm/boot/dts/infinity3-msc313e.dtsi create mode 100644 arch/arm/boot/dts/infinity3.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index ccabe73ce800..48df02045641 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ diff --git a/arch/arm/boot/dts/infinity-msc313.dtsi b/arch/arm/boot/dts/infinity-msc313.dtsi new file mode 100644 index 000000000000..42f2b5552c77 --- /dev/null +++ b/arch/arm/boot/dts/infinity-msc313.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi new file mode 100644 index 000000000000..f68e6d59c328 --- /dev/null +++ b/arch/arm/boot/dts/infinity.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" diff --git a/arch/arm/boot/dts/infinity3-msc313e.dtsi b/arch/arm/boot/dts/infinity3-msc313e.dtsi new file mode 100644 index 000000000000..4e7239afd823 --- /dev/null +++ b/arch/arm/boot/dts/infinity3-msc313e.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity3.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi new file mode 100644 index 000000000000..2830d064c07d --- /dev/null +++ b/arch/arm/boot/dts/infinity3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "infinity.dtsi" -- cgit v1.2.3 From 3e54698c1ae1eaa60d213dc11bede651d9bacb8a Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Fri, 10 Jul 2020 18:45:42 +0900 Subject: ARM: mstar: Add mercury5 series dtsis This adds a family level dtsi for the mercury5 and then a chip level dtsi for the ssc8336n chip. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + arch/arm/boot/dts/mercury5-ssc8336n.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/mercury5.dtsi | 7 +++++++ 3 files changed, 22 insertions(+) create mode 100644 arch/arm/boot/dts/mercury5-ssc8336n.dtsi create mode 100644 arch/arm/boot/dts/mercury5.dtsi (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 48df02045641..5cf1f451d62e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2141,6 +2141,7 @@ S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml F: arch/arm/boot/dts/infinity*.dtsi +F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi F: arch/arm/mach-mstar/ diff --git a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi new file mode 100644 index 000000000000..7d4a4630c25c --- /dev/null +++ b/arch/arm/boot/dts/mercury5-ssc8336n.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mercury5.dtsi" + +/ { + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x4000000>; + }; +}; diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mercury5.dtsi new file mode 100644 index 000000000000..f68e6d59c328 --- /dev/null +++ b/arch/arm/boot/dts/mercury5.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-v7.dtsi" -- cgit v1.2.3 From 33cabc0bc679022160c48f96e2d358e666710f58 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:13 +0900 Subject: dt-bindings: arm: mstar: Add binding details for mstar, pmsleep This adds a YAML description of the pmsleep node used by MStar/SigmaStar Armv7 SoCs. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- .../bindings/arm/mstar/mstar,pmsleep.yaml | 43 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml new file mode 100644 index 000000000000..ef78097a7087 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,pmsleep.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,pmsleep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC pmsleep register region + +maintainers: + - Daniel Palmer + +description: | + MStar/Sigmastar's Armv7 SoCs contain a region of registers that are + in the always on domain that the vendor code calls the "pmsleep" area. + + This area contains registers and bits for a broad range of functionality + ranging from registers that control going into deep sleep to bits that + turn things like the internal temperature sensor on and off. + +properties: + compatible: + oneOf: + - items: + - enum: + - mstar,pmsleep + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmsleep: pmsleep@1c00 { + compatible = "mstar,pmsleep", "syscon"; + reg = <0x0x1c00 0x100>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 5cf1f451d62e..2de475e12d4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2140,6 +2140,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar.yaml +F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi F: arch/arm/boot/dts/mstar-v7.dtsi -- cgit v1.2.3 From 9e30b098f25f525af048e685ccb79fc958cfd200 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 28 Jul 2020 19:03:14 +0900 Subject: dt-bindings: arm: mstar: Move existing MStar binding descriptions Now there is an mstar directory move the existing MStar specific descriptions into that directory. Signed-off-by: Daniel Palmer Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/mstar.yaml | 33 ---------------- .../bindings/arm/mstar/mstar,l3bridge.yaml | 44 ++++++++++++++++++++++ .../devicetree/bindings/arm/mstar/mstar.yaml | 33 ++++++++++++++++ .../devicetree/bindings/misc/mstar,l3bridge.yaml | 44 ---------------------- MAINTAINERS | 1 - 5 files changed, 77 insertions(+), 78 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mstar.yaml create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar.yaml delete mode 100644 Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/arm/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar.yaml deleted file mode 100644 index bdce34b3336e..000000000000 --- a/Documentation/devicetree/bindings/arm/mstar.yaml +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/mstar.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MStar platforms device tree bindings - -maintainers: - - Daniel Palmer - -properties: - $nodename: - const: '/' - compatible: - oneOf: - - description: infinity boards - items: - - enum: - - thingyjp,breadbee-crust # thingy.jp BreadBee Crust - - const: mstar,infinity - - - description: infinity3 boards - items: - - enum: - - thingyjp,breadbee # thingy.jp BreadBee - - const: mstar,infinity3 - - - description: mercury5 boards - items: - - enum: - - 70mai,midrived08 # 70mai midrive d08 - - const: mstar,mercury5 diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml new file mode 100644 index 000000000000..6816bd68f9cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC l3bridge + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface + between the CPU and memory. This means that before DMA capable + devices are allowed to run the pipeline must be flushed to ensure + everything is in memory. + + The l3bridge region contains registers that allow such a flush + to be triggered. + + This node is used by the platform code to find where the registers + are and install a barrier that triggers the required pipeline flush. + +properties: + compatible: + items: + - const: mstar,l3bridge + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3bridge: l3bridge@1f204400 { + compatible = "mstar,l3bridge"; + reg = <0x1f204400 0x200>; + }; diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml new file mode 100644 index 000000000000..c2f980b00b06 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar platforms device tree bindings + +maintainers: + - Daniel Palmer + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: infinity boards + items: + - enum: + - thingyjp,breadbee-crust # thingy.jp BreadBee Crust + - const: mstar,infinity + + - description: infinity3 boards + items: + - enum: + - thingyjp,breadbee # thingy.jp BreadBee + - const: mstar,infinity3 + + - description: mercury5 boards + items: + - enum: + - 70mai,midrived08 # 70mai midrive d08 + - const: mstar,mercury5 diff --git a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml b/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml deleted file mode 100644 index cb7fd1cdfb1a..000000000000 --- a/Documentation/devicetree/bindings/misc/mstar,l3bridge.yaml +++ /dev/null @@ -1,44 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -# Copyright 2020 thingy.jp. -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/misc/mstar,l3bridge.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: MStar/SigmaStar Armv7 SoC l3bridge - -maintainers: - - Daniel Palmer - -description: | - MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface - between the CPU and memory. This means that before DMA capable - devices are allowed to run the pipeline must be flushed to ensure - everything is in memory. - - The l3bridge region contains registers that allow such a flush - to be triggered. - - This node is used by the platform code to find where the registers - are and install a barrier that triggers the required pipeline flush. - -properties: - compatible: - items: - - const: mstar,l3bridge - - reg: - maxItems: 1 - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - l3bridge: l3bridge@1f204400 { - compatible = "mstar,l3bridge"; - reg = <0x1f204400 0x200>; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 2de475e12d4f..f8e2683d8bff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2139,7 +2139,6 @@ M: Daniel Palmer L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ -F: Documentation/devicetree/bindings/arm/mstar.yaml F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/infinity*.dtsi F: arch/arm/boot/dts/mercury*.dtsi -- cgit v1.2.3