From a5238e360b715e9a1bb39d7d3537f78cc9e9e286 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: spi: s3c64xx: move controller information into driver data Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Acked-by: Grant Likely Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock-exynos4.c | 18 +++++++++--------- arch/arm/mach-exynos/setup-spi.c | 25 ------------------------- 2 files changed, 9 insertions(+), 34 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..10a46a9f0ea7 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 13), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 16), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { @@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, @@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = { static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, @@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = { static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, @@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40ee0e8..a71ec4db4cf4 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -12,17 +12,8 @@ #include #include -#include #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); @@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); @@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); -- cgit v1.2.3 From 868dee91a5f96dfbc97b2cd582614cdc339ec305 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Fri, 13 Jul 2012 07:15:14 +0900 Subject: ARM: SAMSUNG: Remove pdev pointer parameter from spi gpio setup functions The platform data pointer that is passed to the spi gpio setup functions is not used. Hence, this parameter is removed from all the spi gpio setup functions. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/setup-spi.c | 8 +++----- arch/arm/mach-s3c24xx/setup-spi.c | 2 +- arch/arm/mach-s3c64xx/setup-spi.c | 6 ++---- arch/arm/mach-s5p64x0/setup-spi.c | 5 ++--- arch/arm/mach-s5pc100/setup-spi.c | 8 +++----- arch/arm/mach-s5pv210/setup-spi.c | 6 ++---- arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 8 ++++---- drivers/spi/spi-s3c64xx.c | 5 ++--- 8 files changed, 19 insertions(+), 29 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index a71ec4db4cf4..4999829d1c6e 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); @@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); @@ -36,7 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c index 42abe157f98f..3d47e023ce94 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c24xx/setup-spi.c @@ -18,7 +18,7 @@ #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) +int s3c64xx_spi0_cfg_gpio(void) { /* enable hsspi bit in misccr */ s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c index ff999d95b370..4dc53450d715 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c64xx/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c index 1cf84b524698..7664356720ca 100644 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ b/arch/arm/mach-s5p64x0/setup-spi.c @@ -9,11 +9,10 @@ */ #include -#include #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, @@ -26,7 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c index 4b42718948a4..183567961de1 100644 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ b/arch/arm/mach-s5pc100/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -32,7 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index 2cd66a632791..81aecc162f82 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -9,12 +9,10 @@ */ #include -#include - #include #ifdef CONFIG_S3C64XX_DEV_SPI0 -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); @@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 4e9b9c314a29..89dbaee43800 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -39,7 +39,7 @@ struct s3c64xx_spi_csinfo { struct s3c64xx_spi_info { int src_clk_nr; int num_cs; - int (*cfg_gpio)(struct platform_device *pdev); + int (*cfg_gpio)(void); }; /** @@ -60,9 +60,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, int src_clk_nr, int num_cs); /* defined by architecture to configure gpio */ -extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); +extern int s3c64xx_spi0_cfg_gpio(void); +extern int s3c64xx_spi1_cfg_gpio(void); +extern int s3c64xx_spi2_cfg_gpio(void); extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 8698618e56fe..0a9e43e635aa 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1071,7 +1071,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) goto err1; } - if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { + if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { dev_err(&pdev->dev, "Unable to config gpio\n"); ret = -EBUSY; goto err2; @@ -1214,12 +1214,11 @@ static int s3c64xx_spi_suspend(struct device *dev) static int s3c64xx_spi_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); struct s3c64xx_spi_info *sci = sdd->cntrlr_info; - sci->cfg_gpio(pdev); + sci->cfg_gpio(); /* Enable the clock */ clk_enable(sdd->src_clk); -- cgit v1.2.3 From 46fda15c0c21493a9305db0a05e08f072d6409e4 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:53:08 +0900 Subject: ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock The sclk_spi clock is derived currently from the first level divider (MMCx_RATIO) which is incorrect. The output of the first level clock is divided by a second level divider (MMCx_PRE_RATIO), the output of which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy issues for the sclk_spi clock. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh [kgene.kim@samsung.com: changed the name of clk for consensus] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock-exynos4.c | 49 ++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 10a46a9f0ea7..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, }; /* Clock initialization code */ @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, - + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { -- cgit v1.2.3 From d40af3652bc91f3c25ce4c13b2ee1751c3e742f3 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:54:26 +0900 Subject: ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4 Add the platform bits which are required to support SPI controllers. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/irqs.h | 4 ++++ arch/arm/mach-exynos/mach-exynos4-dt.c | 6 ++++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 7a4b4789eb72..35bced6f9092 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -195,6 +195,10 @@ #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 +#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 +#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 +#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 + #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e7e9743543ac..b2b5d5faa748 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4-sdhci.3", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), {}, -- cgit v1.2.3 From ea5a9ce6aec67cc30ca43d6d2a0dd83f9291598c Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:53:13 +0900 Subject: ARM: EXYNOS: Add spi clock support for EXYNOS5 Add support for clock instances for each spi controller. Signed-off-by: Thomas Abraham Acked-by: Jaswinder Singh [kgene.kim@samsung.com: changed the name of clk for consensus] Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock-exynos5.c | 95 ++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336be2b4..774533c67066 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); } +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); +} + static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); @@ -740,6 +745,24 @@ static struct clk exynos5_init_clocks_off[] = { .parent = &exynos5_clk_aclk_66.clk, .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 14), + }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 18), }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), @@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos5_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_mdout_spi0.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_mdout_spi1.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_mdout_spi2.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_dout_mmc4, &exynos5_clk_aclk_acp, &exynos5_clk_pclk_acp, + &exynos5_clk_sclk_spi0, + &exynos5_clk_sclk_spi1, + &exynos5_clk_sclk_spi2, + &exynos5_clk_mdout_spi0, + &exynos5_clk_mdout_spi1, + &exynos5_clk_mdout_spi2, }; static struct clk *exynos5_clk_cdev[] = { @@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), -- cgit v1.2.3 From b0b27815c752714e74cce5fc53c4e14797d12214 Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sat, 14 Jul 2012 10:54:31 +0900 Subject: ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5 Add the platform bits which are required to support SPI controllers. Signed-off-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/map.h | 3 +++ arch/arm/mach-exynos/mach-exynos5-dt.c | 6 ++++++ 2 files changed, 9 insertions(+) (limited to 'arch/arm/mach-exynos') diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89aa46b..c72b675b3e4b 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -154,6 +154,9 @@ #define EXYNOS4_PA_SPI0 0x13920000 #define EXYNOS4_PA_SPI1 0x13930000 #define EXYNOS4_PA_SPI2 0x13940000 +#define EXYNOS5_PA_SPI0 0x12D20000 +#define EXYNOS5_PA_SPI1 0x12D30000 +#define EXYNOS5_PA_SPI2 0x12D40000 #define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO2 0x11000000 diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a228cc..ef770bc2318f 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), -- cgit v1.2.3