From bffed3d4abcd32ba6d492a9bd7ebe81dc92eaa9a Mon Sep 17 00:00:00 2001 From: Ellie Reeves Date: Sun, 25 Mar 2018 21:57:36 +0200 Subject: arm64: dts: armada-3720-espressobin: wire up spi flash MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the storage the machine boots from by default. The partitioning is taken from the U-Boot that is shipped with the board. There is some more space on the flash that isn't used. Tested-by: Gregory CLEMENT Signed-off-by: Ellie Reeves Signed-off-by: Uwe Kleine-König Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-3720-espressobin.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index ef7fd2ca2515..3ab25ad402b9 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -63,6 +63,33 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "winbond,w25q32dw", "jedec,spi-flash"; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0 0x180000>; + }; + + partition@180000 { + label = "ubootenv"; + reg = <0x180000 0x10000>; + }; + }; + }; +}; + /* Exported on the micro USB connector J5 through an FTDI */ &uart0 { pinctrl-names = "default"; -- cgit v1.2.3 From 02ba4ce64d022609c2510ba39ccca140776d4121 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Sat, 31 Mar 2018 16:44:06 +0200 Subject: arm64: dts: marvell: mark CP110 ahci as dma-coherent The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel. Signed-off-by: Mark Kettenis Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 48cad7919efa..690d445bd516 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -233,6 +233,7 @@ compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; + dma-coherent; interrupts = ; clocks = <&CP110_LABEL(clk) 1 15>, <&CP110_LABEL(clk) 1 16>; -- cgit v1.2.3 From 9429d508fd87684f8665421e7d6c7cae2d6fc694 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 17 May 2018 10:29:36 +0200 Subject: arm64: dts: marvell: mcbin: add 10G SFP support This patch adds the SFP cage description in the Marvell Armada 8040 mcbin, for both 10G interfaces. Signed-off-by: Russell King [Antoine: small reworks, commit message] Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index 81de03ef860d..eaa67de8c2bb 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -64,6 +64,30 @@ compatible = "usb-nop-xceiv"; vcc-supply = <&v_5v0_usb3_hst_vbus>; }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp0_i2c>; + los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp0_pins>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp1_i2c>; + los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + }; }; &uart0 { @@ -180,6 +204,10 @@ "mpp60", "mpp61"; marvell,function = "sdio"; }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; }; &cp0_xmdio { @@ -188,11 +216,13 @@ phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0>; + sfp = <&sfp_eth0>; }; phy8: ethernet-phy@8 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <8>; + sfp = <&sfp_eth1>; }; }; @@ -258,6 +288,10 @@ }; &cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp8", "mpp10", "mpp11"; + marvell,function = "gpio"; + }; cp1_spi1_pins: spi1-pins { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; marvell,function = "spi1"; @@ -266,6 +300,10 @@ marvell,pins = "mpp6", "mpp7"; marvell,function = "uart0"; }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function = "gpio"; + }; }; /* J27 UART header */ -- cgit v1.2.3 From e720bf6e3a4132b62a5c70e21af5f9aa34b357ae Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 17 May 2018 10:29:37 +0200 Subject: arm64: dts: marvell: mcbin: enable the fourth network interface This patch enables the fourth network interface on the Marvell Macchiatobin. It is configured in the 2500Base-X PHY mode. The SFP cage is also described. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index eaa67de8c2bb..a66958ff4de6 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -27,6 +27,7 @@ ethernet0 = &cp0_eth0; ethernet1 = &cp1_eth0; ethernet2 = &cp1_eth1; + ethernet3 = &cp1_eth2; }; /* Regulator labels correspond with schematics */ @@ -88,6 +89,18 @@ pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; }; + + sfp_eth3: sfp-eth3 { + /* CON3,4 - CPS lane 5 */ + compatible = "sff,sfp"; + i2c-bus = <&sfp_1g_i2c>; + los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + }; }; &uart0 { @@ -195,6 +208,10 @@ marvell,pins = "mpp47"; marvell,function = "gpio"; }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp51", "mpp53", "mpp54"; + marvell,function = "gpio"; + }; cp0_pcie_pins: pcie-pins { marvell,pins = "mpp52"; marvell,function = "gpio"; @@ -287,6 +304,17 @@ phys = <&cp1_comphy0 1>; }; +&cp1_eth2 { + /* CPS Lane 5 */ + status = "okay"; + /* Network PHY */ + phy-mode = "2500base-x"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy5 2>; + sfp = <&sfp_eth3>; +}; + &cp1_pinctrl { cp1_sfpp1_pins: sfpp1-pins { marvell,pins = "mpp8", "mpp10", "mpp11"; @@ -300,6 +328,10 @@ marvell,pins = "mpp6", "mpp7"; marvell,function = "uart0"; }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; cp1_sfpp0_pins: sfpp0-pins { marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; marvell,function = "gpio"; -- cgit v1.2.3 From 639585ac2ff722d4dca1add27c37e6258a091c70 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 17 May 2018 10:29:38 +0200 Subject: arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link This patch adds a fixed-link node to both 10G interfaces of the 8040-db board. This is required as the mvpp2 driver now uses phylink. The best solution would have been to describe the SFP cages but they are not wired correctly, and thus unusable, so we chose to use fixed-link instead. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 5689fb23bbab..1bac437369a1 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -177,6 +177,11 @@ &cp0_eth0 { status = "okay"; phy-mode = "10gbase-kr"; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; &cp0_eth2 { @@ -303,6 +308,11 @@ &cp1_eth0 { status = "okay"; phy-mode = "10gbase-kr"; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; &cp1_eth1 { -- cgit v1.2.3 From 4640efc01d5ab2f5c918cd2683f9c6208c8c637f Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 17 May 2018 10:29:39 +0200 Subject: arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link This patch adds a fixed-link node to the 10G interface of the 7040-db board. This is required as the mvpp2 driver now uses phylink. The best solution would have been to describe the SFP cage but they are not wired correctly, and thus unusable, so we chose to use fixed-link instead. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index d6bec058a30a..412efdb46e7c 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -242,6 +242,11 @@ phy-mode = "10gbase-kr"; /* Generic PHY, providing serdes lanes */ phys = <&cp0_comphy2 0>; + + fixed-link { + speed = <10000>; + full-duplex; + }; }; &cp0_eth1 { -- cgit v1.2.3 From bd473ecda24c6214868d58500c4d7569f6597946 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 21 Mar 2018 11:50:03 +0100 Subject: arm64: dts: marvell: armada-37xx: mark the gpio controllers as irq controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to reference these gpio controller as interrupt parent. Also add a comment which cpu line names are managed by the controllers because "nb" and "sb" usually doesn't appear in schematics, but MPPX_Y do. Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 97207a61bc79..3353252d78a0 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -148,10 +148,13 @@ compatible = "marvell,armada3710-nb-pinctrl", "syscon", "simple-mfd"; reg = <0x13800 0x100>, <0x13C00 0x20>; + /* MPP1[19:0] */ gpionb: gpio { #gpio-cells = <2>; gpio-ranges = <&pinctrl_nb 0 0 36>; gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; interrupts = , , @@ -209,10 +212,13 @@ compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; reg = <0x18800 0x100>, <0x18C00 0x20>; + /* MPP2[23:0] */ gpiosb: gpio { #gpio-cells = <2>; gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; interrupts = , , -- cgit v1.2.3