From f759b640c7219c99e19f0a42c6e086a19d2e2a17 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sun, 10 Jul 2016 11:11:06 +0200 Subject: ARM64: dts: amlogic: meson-gxbb: Add watchdog node Signed-off-by: Neil Armstrong Reviewed-by: Guenter Roeck Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index e502c24b0ac7..d296af0e44e5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -160,6 +160,12 @@ clocks = <&xtal>; status = "disabled"; }; + + watchdog@98d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0x098d0 0x0 0x10>; + clocks = <&xtal>; + }; }; gic: interrupt-controller@c4301000 { -- cgit v1.2.3 From c3929b72e605d1ca7b6b2056c5c23e09b65f4141 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 14 Jun 2016 12:03:39 -0700 Subject: ARM64: DTS: meson-gxbb: switch ethernet to real clock With the clock driver upstream, switch to the real clock. Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index d296af0e44e5..92c88daf0220 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-gxbb"; @@ -343,7 +344,7 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&xtal>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; phy-mode = "rgmii"; status = "disabled"; -- cgit v1.2.3 From 8d298f5b8eb2a81dc42690548df1b0737d351c4b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 18 Aug 2016 12:08:48 +0200 Subject: ARM64: dts: meson-gxbb: Add GXBB AO Clock and Reset node Add the AO clock controller node for the AmLogic GXBB SoC. Signed-off-by: Neil Armstrong Acked-by: Linus Walleij Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 92c88daf0220..592c3dac00a4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -46,6 +46,8 @@ #include #include #include +#include +#include / { compatible = "amlogic,meson-gxbb"; @@ -212,6 +214,13 @@ }; }; + clkc_AO: clock-controller@040 { + compatible = "amlogic,gxbb-aoclkc"; + reg = <0x0 0x00040 0x0 0x4>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart_AO: serial@4c0 { compatible = "amlogic,meson-uart"; reg = <0x0 0x004c0 0x0 0x14>; -- cgit v1.2.3 From 9bfd6329333a0430799ca7d2e1e2087fe3d0feec Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 1 Sep 2016 15:26:13 -0700 Subject: ARM64: dts: amlogic: add the input pin for the IR remote Signed-off-by: Martin Blumenstingl Tested-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 592c3dac00a4..d5762022d2fe 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -212,6 +212,13 @@ function = "uart_ao"; }; }; + + remote_input_ao_pins: remote_input_ao { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; }; clkc_AO: clock-controller@040 { -- cgit v1.2.3 From c58d77855f0069b51f28592a07d1c0f0ca091052 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sat, 20 Aug 2016 11:54:23 +0200 Subject: ARM64: dts: meson-gxbb: Add Infrared Remote Controller decoder This adds the Infrared Remote Controller node so boards with an IR remote can simply enable it. Signed-off-by: Neil Armstrong Signed-off-by: Martin Blumenstingl Tested-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index d5762022d2fe..3419e4f01f02 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -235,6 +235,13 @@ clocks = <&xtal>; status = "disabled"; }; + + ir: ir@580 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x00580 0x0 0x40>; + interrupts = ; + status = "disabled"; + }; }; periphs: periphs@c8834000 { -- cgit v1.2.3 From ae89ed79ae9d1c3e9ed2a3cd861e2f7416d1a9f6 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 20 Aug 2016 11:54:24 +0200 Subject: ARM64: dts: meson-gxbb: Enable the the IR decoder on supported boards Enable the Infrared Remote Controller on boards which have an Infrared receiver. Signed-off-by: Martin Blumenstingl Tested-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 5 +++++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 6 ++++++ 3 files changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 90a84c514d3d..233703529201 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -87,3 +87,8 @@ pinctrl-names = "default"; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index f4f30f674b4c..0eaca7277cfd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -72,3 +72,8 @@ pinctrl-names = "default"; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 54bb7c739089..560770e6c648 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -60,3 +60,9 @@ pinctrl-names = "default"; }; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From f03faf31ea0a6c5aaff38b9c38f5504a962ffb72 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 1 Sep 2016 15:26:56 -0700 Subject: ARM64: dts: meson-gxbb: Add PWM pinctrl nodes Add DT nodes for PWMs in EE and AO domains. Acked-by: Linus Walleij Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 77 +++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 3419e4f01f02..cecacd26f02a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -219,6 +219,34 @@ function = "remote_input_ao"; }; }; + + pwm_ao_a_3_pins: pwm_ao_a_3 { + mux { + groups = "pwm_ao_a_3"; + function = "pwm_ao_a_3"; + }; + }; + + pwm_ao_a_6_pins: pwm_ao_a_6 { + mux { + groups = "pwm_ao_a_6"; + function = "pwm_ao_a_6"; + }; + }; + + pwm_ao_a_12_pins: pwm_ao_a_12 { + mux { + groups = "pwm_ao_a_12"; + function = "pwm_ao_a_12"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; }; clkc_AO: clock-controller@040 { @@ -336,6 +364,55 @@ function = "eth"; }; }; + + pwm_a_x_pins: pwm_a_x { + mux { + groups = "pwm_a_x"; + function = "pwm_a_x"; + }; + }; + + pwm_a_y_pins: pwm_a_y { + mux { + groups = "pwm_a_y"; + function = "pwm_a_y"; + }; + }; + + pwm_b_pins: pwm_b { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_d_pins: pwm_d { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_x_pins: pwm_f_x { + mux { + groups = "pwm_f_x"; + function = "pwm_f_x"; + }; + }; + + pwm_f_y_pins: pwm_f_y { + mux { + groups = "pwm_f_y"; + function = "pwm_f_y"; + }; + }; }; }; -- cgit v1.2.3 From f1a095b96d56402f84ef381121dd72afabd6312e Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 27 Aug 2016 15:43:45 +0200 Subject: ARM64: dts: amlogic: gxbb: Enable secure monitor Add the secure monitor node in the Amlogic Meson GXBB DTSI file to enable it. Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index cecacd26f02a..98e37bb1aee3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -102,6 +102,12 @@ method = "smc"; }; + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Sat, 27 Aug 2016 15:43:48 +0200 Subject: ARM64: dts: amlogic: gxbb: Enable NVMEM Add the NVMEM device node in the DTSI. Signed-off-by: Carlo Caione [khilman: dropped driver cleanup hunk] Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 98e37bb1aee3..762f3681a49c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -108,6 +108,24 @@ }; }; + efuse: efuse { + compatible = "amlogic,meson-gxbb-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + sn: sn@14 { + reg = <0x14 0x10>; + }; + + eth_mac: eth_mac@34 { + reg = <0x34 0x10>; + }; + + bid: bid@46 { + reg = <0x46 0x30>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Thu, 30 Jun 2016 14:32:42 +0100 Subject: arm64: dts: r8a7795: add FCPF device nodes Provide nodes for the FCP devices dedicated to the FDP device channels. Reviewed-by: Geert Uytterhoeven Signed-off-by: Kieran Bingham Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b902356873c2..8c85b50d306b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1273,5 +1273,26 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpf2: fcp@fe952000 { + compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; + reg = <0 0xfe952000 0 0x200>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; }; }; -- cgit v1.2.3 From bfb31459342701e0017f790ce675fcaf4df0d1c9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Thu, 30 Jun 2016 14:32:43 +0100 Subject: arm64: dts: r8a7795: add FDP1 device nodes Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Kieran Bingham Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 8c85b50d306b..99953ca9a45e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1294,5 +1294,32 @@ clocks = <&cpg CPG_MOD 613>; power-domains = <&sysc R8A7795_PD_A3VP>; }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf1>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7795_PD_A3VP>; + renesas,fcp = <&fcpf2>; + }; }; }; -- cgit v1.2.3 From dcdca4d53845d1fdf3f7f25e7db709886facea00 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 21 Jul 2016 19:01:44 +0200 Subject: arm64: dts: r8a7795: set maximum frequency for SDHI clocks Define the upper limit otherwise the driver cannot utilize max speeds. Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 99953ca9a45e..834a12a13735 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1098,6 +1098,7 @@ reg = <0 0xee100000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1107,6 +1108,7 @@ reg = <0 0xee120000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1116,6 +1118,7 @@ reg = <0 0xee140000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; cap-mmc-highspeed; status = "disabled"; @@ -1126,6 +1129,7 @@ reg = <0 0xee160000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; cap-mmc-highspeed; status = "disabled"; -- cgit v1.2.3 From d2422e1088128f7c7c93681dde7bafe4e52e9255 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 Jul 2016 19:46:57 +0900 Subject: arm64: dts: r8a7795: Add HSUSB device node Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 834a12a13735..58376e72404b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1228,6 +1228,23 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; status = "disabled"; }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7795"; reg = <0 0xfe000000 0 0x80000>; -- cgit v1.2.3 From a905b72ce9216a501d8239a1f1790817b5645ef9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 Jul 2016 19:46:58 +0900 Subject: arm64: dts: r8a7795: salvator-x: enable usb2_phy of channel 0 This patch also adds a regulator node for USB2.0 to handle VBUS on/off by the phy-rcar-gen3-usb2 driver. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 98f02631a0f0..8c8bfdccdc2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -110,6 +110,17 @@ 1800000 0>; }; + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + audio_clkout: audio_clkout { /* * This is same as <&rcar_sound 0> @@ -193,6 +204,11 @@ function = "audio_clk"; }; + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + usb1_pins: usb1 { groups = "usb1"; function = "usb1"; @@ -369,6 +385,14 @@ status = "okay"; }; +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + &usb2_phy1 { pinctrl-0 = <&usb1_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 34ccd788a38983249727b081b2bf92ab54bfa27c Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 Jul 2016 19:46:59 +0900 Subject: arm64: dts: r8a7795: salvator-x: enable USB 2.0 Host channel 0 We have to set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 8c8bfdccdc2b..c0e6e8f7c7d8 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -407,6 +407,10 @@ status = "okay"; }; +&ehci0 { + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -415,6 +419,10 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; -- cgit v1.2.3 From 0b4dca78f0f7c8fb1e9ccc06a173500f3a27d0fd Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 Jul 2016 19:47:00 +0900 Subject: arm64: dts: r8a7795: salvator-x: enable HSUSB Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index c0e6e8f7c7d8..4332ec7bb38c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -431,6 +431,10 @@ status = "okay"; }; +&hsusb { + status = "okay"; +}; + &pcie_bus_clk { clock-frequency = <100000000>; status = "okay"; -- cgit v1.2.3 From 52cd078325e5476896dd7027c8398145955489e9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 9 Aug 2016 15:29:09 +0300 Subject: arm64: dts: renesas: r8a7795: Add FCPV nodes The FCPs handle the interface between various IP cores and memory. Add the instances related to the VSP2s. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 63 ++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 58376e72404b..fe7725d1d131 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1295,6 +1295,13 @@ status = "disabled"; }; + fcpvb1: fcp@fe92f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,r8a7795-fcpf", "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; @@ -1316,6 +1323,62 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + fcpvb0: fcp@fe96f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpvi2: fcp@fe9cf000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfe9cf000 0 0x200>; + clocks = <&cpg CPG_MOD 609>; + power-domains = <&sysc R8A7795_PD_A3VP>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + + fcpvd3: fcp@fea3f000 { + compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; + reg = <0 0xfea3f000 0 0x200>; + clocks = <&cpg CPG_MOD 600>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; -- cgit v1.2.3 From 9f8573e38a0b377aa092db96be140be4d59a7fae Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 9 Aug 2016 15:29:10 +0300 Subject: arm64: dts: renesas: r8a7795: Add VSP instances The r8a7795 has 9 VSP instances. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 ++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index fe7725d1d131..19daa6a88312 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1295,6 +1295,16 @@ status = "disabled"; }; + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvb1>; + }; + fcpvb1: fcp@fe92f000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfe92f000 0 0x200>; @@ -1323,6 +1333,16 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvb0>; + }; + fcpvb0: fcp@fe96f000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -1330,6 +1350,16 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi0>; + }; + fcpvi0: fcp@fe9af000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; @@ -1337,6 +1367,16 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi1>; + }; + fcpvi1: fcp@fe9bf000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfe9bf000 0 0x200>; @@ -1344,6 +1384,16 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + vspi2: vsp@fe9c0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9c0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A7795_PD_A3VP>; + + renesas,fcp = <&fcpvi2>; + }; + fcpvi2: fcp@fe9cf000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfe9cf000 0 0x200>; @@ -1351,6 +1401,16 @@ power-domains = <&sysc R8A7795_PD_A3VP>; }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd0>; + }; + fcpvd0: fcp@fea27000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; @@ -1358,6 +1418,16 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; }; + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd1>; + }; + fcpvd1: fcp@fea2f000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; @@ -1365,6 +1435,16 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; }; + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd2>; + }; + fcpvd2: fcp@fea37000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfea37000 0 0x200>; @@ -1372,6 +1452,16 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; }; + vspd3: vsp@fea38000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea38000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + + renesas,fcp = <&fcpvd3>; + }; + fcpvd3: fcp@fea3f000 { compatible = "renesas,r8a7795-fcpv", "renesas,fcpv"; reg = <0 0xfea3f000 0 0x200>; -- cgit v1.2.3 From a001a07fe851ce69fcbe85ee25e292b04624b154 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 9 Aug 2016 15:29:11 +0300 Subject: arm64: dts: renesas: r8a7795: Add DU device to DT Add the DU device to r8a7795.dtsi in a disabled state. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 19daa6a88312..5d59e7fe7bbc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1495,5 +1495,51 @@ power-domains = <&sysc R8A7795_PD_A3VP>; renesas,fcp = <&fcpf2>; }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_hdmi1: endpoint { + }; + }; + port@3 { + reg = <3>; + du_out_lvds0: endpoint { + }; + }; + }; + }; }; }; -- cgit v1.2.3 From aadc4ee00a0ec4de5e4aea9f879ab738fd34d0e1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 9 Aug 2016 15:29:12 +0300 Subject: arm64: dts: r8a7795: renesas: salvator-x: Enable DU Only the VGA output is supported for now. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 4332ec7bb38c..64a29a87a724 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -146,6 +146,50 @@ sound-dai = <&ak4613>; }; }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; }; &extal_clk { -- cgit v1.2.3 From f826473520e7aba2e416f79a3acbd6da3921e0a2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 31 Aug 2016 11:31:55 +0200 Subject: arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes The audio-dmac nodes used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 5d59e7fe7bbc..64899b556a0e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -328,7 +328,8 @@ }; audma0: dma-controller@ec700000 { - compatible = "renesas,rcar-dmac"; + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; reg = <0 0xec700000 0 0x10000>; interrupts = ; interrupts = Date: Wed, 31 Aug 2016 13:02:39 +0300 Subject: arm64: dts: h3ulcb: initial device tree Add the initial device tree for the R8A7795 SoC based H3ULCB low cost board. This commit supports the following peripherals: - SCIF (console) Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/Makefile | 2 +- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 51 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 17139f7003a6..eb72830ec9eb 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts new file mode 100644 index 000000000000..ecb9e1102266 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -0,0 +1,51 @@ +/* + * Device Tree Source for the H3ULCB board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include + +/ { + model = "Renesas H3ULCB board based on r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&pfc { + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From af111bce5437c6d4174434c9f5002f463f83d651 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:02:49 +0300 Subject: arm64: dts: h3ulcb: enable SCIF clk and pins This enables the external crystal for the SCIF_CLK and its pinctrl, to be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index ecb9e1102266..67ce368ff9ee 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -37,10 +37,18 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; }; &scif2 { @@ -49,3 +57,8 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; -- cgit v1.2.3 From 144bf6ccb13fc661a2d18ae8b13f25e61015331b Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:02:59 +0300 Subject: arm64: dts: h3ulcb: enable EthernetAVB This supports Ethernet AVB on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 67ce368ff9ee..fb694b8c6f59 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -19,6 +19,7 @@ aliases { serial0 = &scif2; + ethernet0 = &avb; }; chosen { @@ -49,6 +50,11 @@ groups = "scif_clk_a"; function = "scif_clk"; }; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; }; &scif2 { @@ -62,3 +68,29 @@ clock-frequency = <14745600>; status = "okay"; }; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <900>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <900>; + txen-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; -- cgit v1.2.3 From eb3f0f199fc48a813ee8f22212c91d5f8859ff79 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:03:29 +0300 Subject: arm64: dts: h3ulcb: enable I2C2 This supports I2C2 bus on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index fb694b8c6f59..3ba1f72526ba 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -51,6 +51,11 @@ function = "scif_clk"; }; + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + avb_pins: avb { groups = "avb_mdc"; function = "avb"; @@ -69,6 +74,13 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From b00d23f71f2cbca63d4d8ddde15b39f18fccd7a8 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:03:36 +0300 Subject: arm64: dts: h3ulcb: enable EXTALR clk This enables EXTALR clock that can be used for the watchdog. Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 3ba1f72526ba..42a4208f57ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -37,6 +37,10 @@ clock-frequency = <16666666>; }; +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 4bdb25d0f1b437ac8d58ce8007a4b4ae33a4533a Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:03:48 +0300 Subject: arm64: dts: h3ulcb: enable WDT This supports watchdog timer for H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 42a4208f57ed..ce95a3346102 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -85,6 +85,11 @@ status = "okay"; }; +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 0baa64d8d2f0dc7ef006b6f7669cb2c7862899da Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:03:56 +0300 Subject: arm64: dts: h3ulcb: enable USB2 PHY of channel 1 This supports USB2 PHY channel #1 on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index ce95a3346102..c7ce96f90722 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -64,6 +64,11 @@ groups = "avb_mdc"; function = "avb"; }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; }; &scif2 { @@ -115,3 +120,10 @@ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; }; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From 15907f1f875f267ea0111654f52966c0adadb3ea Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 31 Aug 2016 13:04:03 +0300 Subject: arm64: dts: h3ulcb: enable USB2.0 Host channel 1 This supports USB2.0 Host channel 1 on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index c7ce96f90722..234b66a9e163 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -127,3 +127,11 @@ status = "okay"; }; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; -- cgit v1.2.3 From 56de959f533f5138f1cd5aaa4706e1831c479e28 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 30 Aug 2016 23:09:55 +0200 Subject: arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property Remove cap-mmc-highspeed property from SDHI2 and SDHI3. This property is unnecessary as the driver automatically sets the highspeed capability. Furthermore its use is inconsistent with SDHI0 and SDHI1 which are also highspeed capable but do not have this property present. Found by inspection. Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 64899b556a0e..8c15040f2540 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1122,7 +1122,6 @@ clocks = <&cpg CPG_MOD 312>; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - cap-mmc-highspeed; status = "disabled"; }; @@ -1133,7 +1132,6 @@ clocks = <&cpg CPG_MOD 311>; max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - cap-mmc-highspeed; status = "disabled"; }; -- cgit v1.2.3 From 0e3886a981e062740fbb89670f79fd57caed8137 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Fri, 2 Sep 2016 19:24:58 +0300 Subject: arm64: dts: h3ulcb: enable GPIO keys This supports GPIO keys on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 234b66a9e163..adf2b0e44dac 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "r8a7795.dtsi" #include +#include / { model = "Renesas H3ULCB board based on r8a7795"; @@ -31,6 +32,18 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; }; &extal_clk { -- cgit v1.2.3 From 57094363192098bd798aab07851b702f563fb0a2 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Fri, 2 Sep 2016 19:25:08 +0300 Subject: arm64: dts: h3ulcb: enable SDHI0 This supports SDHI0 on H3ULCB board SD card slot Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index adf2b0e44dac..44f1184e1a14 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -44,6 +44,30 @@ gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; }; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &extal_clk { @@ -78,6 +102,18 @@ function = "avb"; }; + sdhi0_pins_3v3: sd0_3v3 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_1v8: sd0_1v8 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + usb1_pins: usb1 { groups = "usb1"; function = "usb1"; @@ -103,6 +139,19 @@ status = "okay"; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins_3v3>; + pinctrl-1 = <&sdhi0_pins_1v8>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; -- cgit v1.2.3 From 2627d5179f2c9e0a15a7ccc257d290719efdf694 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Fri, 2 Sep 2016 19:25:29 +0300 Subject: arm64: dts: h3ulcb: Sound SSI support This supports SSI sound for H3ULCB board. SSI DMA mode used. CS2000 used as AUDIO_CLK_B. Signed-off-by: Vladimir Barinov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 118 +++++++++++++++++++++++++ 1 file changed, 118 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 44f1184e1a14..c6d4ee336740 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -45,6 +45,12 @@ }; }; + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -68,6 +74,32 @@ states = <3300000 1 1800000 0>; }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; }; &extal_clk { @@ -114,6 +146,17 @@ power-source = <1800>; }; + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + usb1_pins: usb1 { groups = "usb1"; function = "usb1"; @@ -137,6 +180,73 @@ pinctrl-names = "default"; status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk-multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update to */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; }; &sdhi0 { @@ -152,11 +262,19 @@ status = "okay"; }; +&ssi1 { + shared-pin; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; }; +&audio_clk_a { + clock-frequency = <22579200>; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From e8c841f5ac166e602646c955aa1b0b7499900101 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 5 Sep 2016 15:40:21 +0300 Subject: arm64: dts: h3ulcb: enable GPIO leds This supports GPIO leds on H3ULCB board Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index c6d4ee336740..bcb11a868343 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -33,6 +33,17 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + keyboard { compatible = "gpio-keys"; -- cgit v1.2.3 From 272bde03842b2e89892f876cb2d2285c2ae7eada Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 12 Aug 2016 12:18:55 +0300 Subject: arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 64a29a87a724..b1eab6876f8c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -181,6 +181,8 @@ }; &du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; status = "okay"; ports { @@ -227,6 +229,11 @@ function = "avb"; }; + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; -- cgit v1.2.3 From 50809470486ae28a814c17f813d9201c3299692f Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 18 Aug 2016 15:12:34 +0200 Subject: arm64: dts: r8a7796: Add pinctrl device node This patch adds pinctrl device node for R8A7796 SoC. Signed-off-by: Takeshi Kihara Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1edf82440d78..91abc0732bdf 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -107,6 +107,11 @@ status = "disabled"; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7796"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit v1.2.3 From 6b5f8e7e7fc5e5ff293d95406d1adb2e24e037ce Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 18 Aug 2016 15:12:35 +0200 Subject: arm64: dts: r8a7796: salvator-x: add serial console pins Adds pin control for SCIF2. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index e72be3856d79..13db7d61c26c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -31,11 +31,27 @@ }; }; +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; status = "okay"; }; -- cgit v1.2.3 From fa765e5ef49d57834ee66690ba8ed5932edb7968 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 17 Aug 2016 11:13:51 +0200 Subject: arm64: dts: r8a7796: Add GPIO device nodes Add GPIO device nodes to the DT of the r8a7796 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 112 +++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 91abc0732bdf..9217da983525 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -107,6 +107,118 @@ status = "disabled"; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; -- cgit v1.2.3 From f59063aee201bf6acc1eb04fdb726821e136c661 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Sep 2016 20:29:03 +0200 Subject: ARM64: dts: amlogic: enable ethernet on all Tronsmart Vega S95 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All of these have a Realtek Gbit RGMII PHY. Signed-off-by: Martin Blumenstingl Tested-by: Andreas Färber Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 560770e6c648..56243261e9d5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -66,3 +66,9 @@ pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 7b5682c64bd50737050e1c1d30770a580feaf13a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 18 Aug 2016 12:10:27 +0200 Subject: ARM64: dts: meson-gxbb: Add Meson MHU Node Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 762f3681a49c..cac8e51c2108 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -452,6 +452,15 @@ #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3db>; }; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; }; apb: apb@d0000000 { -- cgit v1.2.3 From 8f14a89305b53fdf18e04cf94a89cd5460423d69 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Aug 2016 17:36:32 +0200 Subject: ARM64: dts: meson-gxbb: Add Meson GXBB PWM Controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Neil Armstrong Tested-by: Jérôme Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index cac8e51c2108..3b181939f437 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -180,6 +180,27 @@ status = "disabled"; }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x08650 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x086c0 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart_C: serial@8700 { compatible = "amlogic,meson-uart"; reg = <0x0 0x8700 0x0 0x14>; @@ -294,6 +315,13 @@ interrupts = ; status = "disabled"; }; + + pwm_ab_AO: pwm@550 { + compatible = "amlogic,meson-gxbb-pwm"; + reg = <0x0 0x0550 0x0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; }; periphs: periphs@c8834000 { -- cgit v1.2.3 From 42bede64c834e29fda0bd126c61ef61bc9d71278 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Sep 2016 20:23:20 +0200 Subject: ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver The Amlogic reference driver uses the "mc_val" devicetree property to configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic values for this configuration. According to the datasheet the PRG_ETHERNET_ADDR0 register is at address 0xc8834108. However, the reference driver uses 0xc8834540 instead. According to my tests, the value from the reference driver is correct. No changes are required to the board dts files because the only required configuration option is the phy-mode, which had to be configured correctly before as well. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 3b181939f437..f76a3cdd1b2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -500,13 +500,15 @@ }; ethmac: ethernet@c9410000 { - compatible = "amlogic,meson6-dwmac", "snps,dwmac"; + compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; phy-mode = "rgmii"; status = "disabled"; }; -- cgit v1.2.3 From c74b5ecfe3328196ae3c1809e98ce5fd0fb17ed8 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Sep 2016 10:28:57 +0200 Subject: ARM64: dts: amlogic: add spi nor pins Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index f76a3cdd1b2c..195c012bab9a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -361,6 +361,16 @@ }; }; + nor_pins: nor { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_cs"; + function = "nor"; + }; + }; + sdcard_pins: sdcard { mux { groups = "sdcard_d0", -- cgit v1.2.3 From 2d7ed3df4401ea818ff821650b37ed56c5a0fbf5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sun, 11 Sep 2016 14:39:03 +0200 Subject: ARM64: dts: meson-gxbb: add the SDIO pins This is used to configure the pins of the sd_emmc_a controller to which an SDIO module is connected (when available). Signed-off-by: Neil Armstrong Tested-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 195c012bab9a..c598e75b707d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -383,6 +383,25 @@ }; }; + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_cmd", + "sdio_clk"; + function = "sdio"; + }; + }; + + sdio_irq_pins: sdio_irq { + mux { + groups = "sdio_irq"; + function = "sdio"; + }; + }; + uart_a_pins: uart_a { mux { groups = "uart_tx_a", -- cgit v1.2.3 From e9c9b651a3e22bab72a84dae0d7871efcaebe13c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 9 Sep 2016 10:28:58 +0200 Subject: ARM64: dts: meson-gxbb: Add SPIFC node Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index c598e75b707d..1fff91c4bb89 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -214,6 +214,15 @@ reg = <0x0 0x098d0 0x0 0x10>; clocks = <&xtal>; }; + + spifc: spi@8c80 { + compatible = "amlogic,meson-gxbb-spifc"; + reg = <0x0 0x08c80 0x0 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_SPI>; + status = "disabled"; + }; }; gic: interrupt-controller@c4301000 { -- cgit v1.2.3 From 8c04d7950ac6c6ba1086eeb50e0f00c0eec06263 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Sep 2016 12:06:06 +0200 Subject: ARM64: dts: meson-gxbb: add pins for I2C Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 1fff91c4bb89..0da9131d1a38 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -274,6 +274,14 @@ }; }; + i2c_ao_pins: i2c_ao { + mux { + groups = "i2c_sck_ao", + "i2c_sda_ao"; + function = "i2c_ao"; + }; + }; + pwm_ao_a_3_pins: pwm_ao_a_3 { mux { groups = "pwm_ao_a_3"; @@ -435,6 +443,30 @@ }; }; + i2c_a_pins: i2c_a { + mux { + groups = "i2c_sck_a", + "i2c_sda_a"; + function = "i2c_a"; + }; + }; + + i2c_b_pins: i2c_b { + mux { + groups = "i2c_sck_b", + "i2c_sda_b"; + function = "i2c_b"; + }; + }; + + i2c_c_pins: i2c_c { + mux { + groups = "i2c_sck_c", + "i2c_sda_c"; + function = "i2c_c"; + }; + }; + eth_pins: eth_c { mux { groups = "eth_mdio", -- cgit v1.2.3 From 1befc626c175871d3a95a9b7dc51956a66e8760a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 14 Sep 2016 12:06:07 +0200 Subject: ARM64: dts: meson-gxbb: add I2C nodes Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 40 +++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 0da9131d1a38..0ed7c3a83195 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -223,6 +223,36 @@ clocks = <&clkc CLKID_SPI>; status = "disabled"; }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x08500 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087c0 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_C: i2c@87e0 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x087e0 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; gic: interrupt-controller@c4301000 { @@ -339,6 +369,16 @@ #pwm-cells = <3>; status = "disabled"; }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson-gxbb-i2c"; + reg = <0x0 0x500 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_AO_I2C>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; periphs: periphs@c8834000 { -- cgit v1.2.3 From cb700f4935dbd65aedfaabb0f5799eb14e5ebb60 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Sep 2016 12:06:08 +0200 Subject: ARM64: dts: gxbb: add i2c bus Add nodes for i2c bus on gxbb based platforms. On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are present directly on the board. This indicates that these pins are dedicated to i2c. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 233703529201..e6e3491d48a5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -92,3 +92,9 @@ pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index 62979076e250..03e3d76626dd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -50,3 +50,9 @@ compatible = "amlogic,p200", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P200 Development Board"; }; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 566603e5e6b68da1e72011ec3091fe12ba9510b7 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Sep 2016 15:41:09 +0200 Subject: ARM64: dts: meson-gxbb: add USB Nodes Add the nodes for the dwc2 USB controller and the related USB PHYs. Currently we force usb0 to host mode because OTG is currently not working in our PHY driver. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 0ed7c3a83195..4e9cd01c60a7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -151,6 +151,25 @@ #size-cells = <2>; ranges; + usb0_phy: phy@c0000000 { + compatible = "amlogic,meson-gxbb-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0xc0000000 0x0 0x20>; + resets = <&reset RESET_USB_OTG>; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + status = "disabled"; + }; + + usb1_phy: phy@c0000020 { + compatible = "amlogic,meson-gxbb-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0xc0000020 0x0 0x20>; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + status = "disabled"; + }; + cbus: cbus@c1100000 { compatible = "simple-bus"; reg = <0x0 0xc1100000 0x0 0x100000>; @@ -609,6 +628,30 @@ ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; }; + usb0: usb@c9000000 { + compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; + reg = <0x0 0xc9000000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb@c9100000 { + compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; + reg = <0x0 0xc9100000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet@c9410000 { compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 -- cgit v1.2.3 From 8735053d79686dd87217e300b006175cda1b5c59 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Sun, 11 Sep 2016 15:41:10 +0200 Subject: ARM64: dts: meson-gxbb-p20x: Enable USB Nodes Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Jerome Brunet [khilman: rename vbus node to match P200 schematics] Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 0eaca7277cfd..06a34dc6002f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -57,6 +57,19 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; + + usb_pwr: regulator-usb-pwrs { + compatible = "regulator-fixed"; + + regulator-name = "USB_PWR"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + /* signal name in schematic: USB_PWR_EN */ + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; /* This UART is brought out to the DB9 connector */ @@ -77,3 +90,20 @@ pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_pwr>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit v1.2.3 From c763eb82a01dd4536a4d4b6bb6be115d4ee32842 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Sep 2016 15:41:11 +0200 Subject: ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 56243261e9d5..73f159370188 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -52,6 +52,19 @@ chosen { stdout-path = "serial0:115200n8"; }; + + usb_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; &uart_AO { @@ -72,3 +85,20 @@ pinctrl-0 = <ð_pins>; pinctrl-names = "default"; }; + +&usb0_phy { + status = "okay"; + phy-supply = <&usb_vbus>; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit v1.2.3