From 9f78d3b5ab97a22a7e836312c495804ee4bca4ab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 31 Jul 2012 11:30:57 +0200 Subject: microblaze: Do not used hardcoded value in exception handler Use predefined macros to support more page sizes. Signed-off-by: Michal Simek --- arch/microblaze/kernel/hw_exception_handler.S | 53 +++++++++++++++------------ 1 file changed, 30 insertions(+), 23 deletions(-) (limited to 'arch/microblaze/kernel/hw_exception_handler.S') diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index aa510f450ac6..76a069dc13cb 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -602,18 +602,19 @@ ex_handler_done: lwi r4, r4, TASK_THREAD+PGDIR ex4: tophys(r4,r4) - BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ - andi r5, r5, 0xffc + /* Create L1 (pgdir/pmd) address */ + BSRLI(r5,r3, PGDIR_SHIFT - 2) + andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 lwi r4, r4, 0 /* Get L1 entry */ - andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ + andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */ beqi r5, ex2 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,10) /* Compute PTE address */ - andi r6, r6, 0xffc - andi r5, r5, 0xfffff003 + BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + andi r6, r6, PAGE_SIZE - 4 + andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -632,7 +633,9 @@ ex_handler_done: * Many of these bits are software only. Bits we don't set * here we (properly should) assume have the appropriate value. */ - andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ +/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */ + andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \ + TLB_ZSEL(1) | TLB_ATTR_MASK ori r4, r4, _PAGE_HWEXEC /* make it executable */ /* find the TLB index that caused the fault. It has to be here*/ @@ -701,18 +704,19 @@ ex_handler_done: lwi r4, r4, TASK_THREAD+PGDIR ex6: tophys(r4,r4) - BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ - andi r5, r5, 0xffc + /* Create L1 (pgdir/pmd) address */ + BSRLI(r5,r3, PGDIR_SHIFT - 2) + andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 lwi r4, r4, 0 /* Get L1 entry */ - andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ + andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */ beqi r5, ex7 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,10) /* Compute PTE address */ - andi r6, r6, 0xffc - andi r5, r5, 0xfffff003 + BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + andi r6, r6, PAGE_SIZE - 4 + andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -731,7 +735,8 @@ ex_handler_done: * here we (properly should) assume have the appropriate value. */ brid finish_tlb_load - andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ + andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \ + TLB_ZSEL(1) | TLB_ATTR_MASK ex7: /* The bailout. Restore registers to pre-exception conditions * and call the heavyweights to help us out. @@ -771,18 +776,19 @@ ex_handler_done: lwi r4, r4, TASK_THREAD+PGDIR ex9: tophys(r4,r4) - BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ - andi r5, r5, 0xffc + /* Create L1 (pgdir/pmd) address */ + BSRLI(r5,r3, PGDIR_SHIFT - 2) + andi r5, r5, PAGE_SIZE - 4 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ or r4, r4, r5 lwi r4, r4, 0 /* Get L1 entry */ - andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ + andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */ beqi r5, ex10 /* Bail if no table */ tophys(r5,r5) - BSRLI(r6,r3,10) /* Compute PTE address */ - andi r6, r6, 0xffc - andi r5, r5, 0xfffff003 + BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ + andi r6, r6, PAGE_SIZE - 4 + andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -801,7 +807,8 @@ ex_handler_done: * here we (properly should) assume have the appropriate value. */ brid finish_tlb_load - andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ + andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \ + TLB_ZSEL(1) | TLB_ATTR_MASK ex10: /* The bailout. Restore registers to pre-exception conditions * and call the heavyweights to help us out. @@ -854,8 +861,8 @@ ex_handler_done: * set of bits. These are size, valid, E, U0, and ensure * bits 20 and 21 are zero. */ - andi r3, r3, 0xfffff000 - ori r3, r3, 0x0c0 + andi r3, r3, PAGE_MASK + ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K) mts rtlbhi, r3 /* Load TLB HI */ nop -- cgit v1.2.3 From 6e80cff5430efb9dc8c12cb066e12c62d0a2d9d2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Aug 2012 10:29:28 +0200 Subject: microblaze: Support 4k/16k/64k pages Add support for page size which is supported by MMU. Remove 8k and 32k page size because they are not supported by MMU. Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 7 ++----- arch/microblaze/include/asm/page.h | 6 ++---- arch/microblaze/kernel/hw_exception_handler.S | 6 ++++++ 3 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/microblaze/kernel/hw_exception_handler.S') diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index ab9afcaa7f6a..6133bed2b855 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -243,14 +243,11 @@ choice config MICROBLAZE_4K_PAGES bool "4k page size" -config MICROBLAZE_8K_PAGES - bool "8k page size" - config MICROBLAZE_16K_PAGES bool "16k page size" -config MICROBLAZE_32K_PAGES - bool "32k page size" +config MICROBLAZE_64K_PAGES + bool "64k page size" endchoice diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h index dd9ea9d6b765..85a5ae8e9bd0 100644 --- a/arch/microblaze/include/asm/page.h +++ b/arch/microblaze/include/asm/page.h @@ -23,12 +23,10 @@ #ifdef __KERNEL__ /* PAGE_SHIFT determines the page size */ -#if defined(CONFIG_MICROBLAZE_32K_PAGES) -#define PAGE_SHIFT 15 +#if defined(CONFIG_MICROBLAZE_64K_PAGES) +#define PAGE_SHIFT 16 #elif defined(CONFIG_MICROBLAZE_16K_PAGES) #define PAGE_SHIFT 14 -#elif defined(CONFIG_MICROBLAZE_8K_PAGES) -#define PAGE_SHIFT 13 #else #define PAGE_SHIFT 12 #endif diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 76a069dc13cb..0a573df47ff8 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -862,7 +862,13 @@ ex_handler_done: * bits 20 and 21 are zero. */ andi r3, r3, PAGE_MASK +#ifdef CONFIG_MICROBLAZE_64K_PAGES + ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K) +#elif CONFIG_MICROBLAZE_16K_PAGES + ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K) +#else ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K) +#endif mts rtlbhi, r3 /* Load TLB HI */ nop -- cgit v1.2.3 From 91836710c73497bdbd4eef966c560d178910400a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 31 Jul 2012 12:01:00 +0200 Subject: microblaze: Use predefined macro for ESR_DIZ Just use macro instead of hardcoded value. Signed-off-by: Michal Simek --- arch/microblaze/kernel/hw_exception_handler.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/microblaze/kernel/hw_exception_handler.S') diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 0a573df47ff8..52b9feb98515 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -75,6 +75,7 @@ #include #include #include +#include #include #undef DEBUG @@ -581,7 +582,7 @@ ex_handler_done: * tried to access a kernel or read-protected page - always * a SEGV). All other faults here must be stores, so no * need to check ESR_S as well. */ - andi r4, r4, 0x800 /* ESR_Z - zone protection */ + andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */ bnei r4, ex2 ori r4, r0, swapper_pg_dir @@ -595,7 +596,7 @@ ex_handler_done: * tried to access a kernel or read-protected page - always * a SEGV). All other faults here must be stores, so no * need to check ESR_S as well. */ - andi r4, r4, 0x800 /* ESR_Z */ + andi r4, r4, ESR_DIZ /* ESR_Z */ bnei r4, ex2 /* get current task address */ addi r4 ,CURRENT_TASK, TOPHYS(0); -- cgit v1.2.3 From 1f26076084678d0edecc07aad7671d8140f97b91 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 1 Aug 2012 10:09:28 +0200 Subject: microblaze: Remove additional andi which has been already done Remove one additional step. Signed-off-by: Michal Simek --- arch/microblaze/kernel/hw_exception_handler.S | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/microblaze/kernel/hw_exception_handler.S') diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S index 52b9feb98515..61b3a1fed46f 100644 --- a/arch/microblaze/kernel/hw_exception_handler.S +++ b/arch/microblaze/kernel/hw_exception_handler.S @@ -615,7 +615,6 @@ ex_handler_done: tophys(r5,r5) BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 - andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -717,7 +716,6 @@ ex_handler_done: tophys(r5,r5) BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 - andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ @@ -789,7 +787,6 @@ ex_handler_done: tophys(r5,r5) BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */ andi r6, r6, PAGE_SIZE - 4 - andi r5, r5, PAGE_MASK + 0x3 or r5, r5, r6 lwi r4, r5, 0 /* Get Linux PTE */ -- cgit v1.2.3