From 46060be6d8400ac0e1965b90a29fde96981a2ba7 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Thu, 18 Feb 2021 12:20:01 +0100 Subject: clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll Previously it was not possible to achieve clock rates of 24.576MHz and 22.5792MHz, which are commonly required core clocks for the i2s peripheral of v3s based SoCs. Add support for those clock rates through the audio pll's sigma-delta modulator. Signed-off-by: Tobias Schramm Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210218112001.479018-2-t.schramm@manjaro.org --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 0e36ca3bf3d5..a774942cb153 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -40,18 +40,29 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", * the base (2x, 4x and 8x), and one variable divider (the one true * pll audio). * - * We don't have any need for the variable divider for now, so we just - * hardcode it to match with the clock names + * With sigma-delta modulation for fractional-N on the audio PLL, + * we have to use specific dividers. This means the variable divider + * can no longer be used, as the audio codec requests the exact clock + * rates we support through this mechanism. So we now hard code the + * variable divider to 1. This means the clock rates will no longer + * match the clock names. */ #define SUN8I_V3S_PLL_AUDIO_REG 0x008 -static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", - "osc24M", 0x008, - 8, 7, /* N */ - 0, 5, /* M */ - BIT(31), /* gate */ - BIT(28), /* lock */ - 0); +static struct ccu_sdm_setting pll_audio_sdm_table[] = { + { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, + { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, +}; + +static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + pll_audio_sdm_table, BIT(24), + 0x284, BIT(31), + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", "osc24M", 0x0010, @@ -524,10 +535,10 @@ static struct ccu_common *sun8i_v3_ccu_clks[] = { &mipi_csi_clk.common, }; -/* We hardcode the divider to 4 for now */ +/* We hardcode the divider to 1 for SDM support */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, - 4, 1, CLK_SET_RATE_PARENT); + 1, 1, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", clk_parent_pll_audio, 2, 1, CLK_SET_RATE_PARENT); -- cgit v1.2.3 From dcc354572d094b9dcf7c532c7263ab55dd376587 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 3 Mar 2021 14:24:30 +0000 Subject: clk: sunxi: Demote non-conformant kernel-doc headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Headers must describe their parameters. Fixes the following W=1 kernel build warning(s): drivers/clk/sunxi/clk-sun9i-core.c:27: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_pll4_factors' drivers/clk/sunxi/clk-sun9i-core.c:100: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_gt_factors' drivers/clk/sunxi/clk-sun9i-core.c:155: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_ahb_factors' drivers/clk/sunxi/clk-sun9i-core.c:235: warning: Function parameter or member 'req' not described in 'sun9i_a80_get_apb1_factors' drivers/clk/sunxi/clk-usb.c:22: warning: cannot understand function prototype: 'struct usb_reset_data ' drivers/clk/sunxi/clk-sun6i-ar100.c:26: warning: Function parameter or member 'req' not described in 'sun6i_get_ar100_factors' Cc: "Emilio López" Cc: Michael Turquette Cc: Stephen Boyd Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: Boris BREZILLON Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210303142430.3168703-1-lee.jones@linaro.org --- drivers/clk/sunxi/clk-sun6i-ar100.c | 2 +- drivers/clk/sunxi/clk-sun9i-core.c | 8 ++++---- drivers/clk/sunxi/clk-usb.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c index e1b7d0929cf7..54babc2b4b9e 100644 --- a/drivers/clk/sunxi/clk-sun6i-ar100.c +++ b/drivers/clk/sunxi/clk-sun6i-ar100.c @@ -16,7 +16,7 @@ #include "clk-factors.h" -/** +/* * sun6i_get_ar100_factors - Calculates factors p, m for AR100 * * AR100 rate is calculated as follows diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c index 305ad78d5fb4..d93c7a53c6c0 100644 --- a/drivers/clk/sunxi/clk-sun9i-core.c +++ b/drivers/clk/sunxi/clk-sun9i-core.c @@ -14,7 +14,7 @@ #include "clk-factors.h" -/** +/* * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4 * PLL4 rate is calculated as follows * rate = (parent_rate * n >> p) / (m + 1); @@ -90,7 +90,7 @@ static void __init sun9i_a80_pll4_setup(struct device_node *node) CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup); -/** +/* * sun9i_a80_get_gt_factors() - calculates m factor for GT * GT rate is calculated as follows * rate = parent_rate / (m + 1); @@ -145,7 +145,7 @@ static void __init sun9i_a80_gt_setup(struct device_node *node) CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup); -/** +/* * sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2 * AHB rate is calculated as follows * rate = parent_rate >> p; @@ -225,7 +225,7 @@ static void __init sun9i_a80_apb0_setup(struct device_node *node) CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup); -/** +/* * sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1 * APB1 rate is calculated as follows * rate = (parent_rate >> p) / (m + 1); diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c index d78a78495bed..5460218f3467 100644 --- a/drivers/clk/sunxi/clk-usb.c +++ b/drivers/clk/sunxi/clk-usb.c @@ -15,7 +15,7 @@ #include -/** +/* * sunxi_usb_reset... - reset bits in usb clk registers handling */ -- cgit v1.2.3