From 2867ff6ceb25ea09456ea233007a1e3fdeebd644 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 20 Jan 2021 12:14:38 +0000 Subject: drm/i915: Strip out internal priorities Since we are not using any internal priority levels, and in the next few patches will introduce a new index for which the optimisation is not so lear cut, discard the small table within the priolist. Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20210120121439.17600-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +- .../gpu/drm/i915/gt/intel_execlists_submission.c | 22 +++------- drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 - drivers/gpu/drm/i915/gt/selftest_lrc.c | 1 - drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +-- drivers/gpu/drm/i915/i915_priolist_types.h | 8 +--- drivers/gpu/drm/i915/i915_scheduler.c | 51 +++------------------- drivers/gpu/drm/i915/i915_scheduler.h | 16 ++----- 8 files changed, 20 insertions(+), 87 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index d7be2b9339f9..1732a42e9075 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -125,7 +125,7 @@ static void heartbeat(struct work_struct *wrk) * low latency and no jitter] the chance to naturally * complete before being preempted. */ - attr.priority = I915_PRIORITY_MASK; + attr.priority = 0; if (rq->sched.attr.priority >= attr.priority) attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT); if (rq->sched.attr.priority >= attr.priority) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index ac1be7a632d3..b31ce0d60028 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -274,22 +274,13 @@ static int effective_prio(const struct i915_request *rq) static int queue_prio(const struct intel_engine_execlists *execlists) { - struct i915_priolist *p; struct rb_node *rb; rb = rb_first_cached(&execlists->queue); if (!rb) return INT_MIN; - /* - * As the priolist[] are inverted, with the highest priority in [0], - * we have to flip the index value to become priority. - */ - p = to_priolist(rb); - if (!I915_USER_PRIORITY_SHIFT) - return p->priority; - - return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); + return to_priolist(rb)->priority; } static int virtual_prio(const struct intel_engine_execlists *el) @@ -1452,9 +1443,8 @@ unlock: while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); struct i915_request *rq, *rn; - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { bool merge = true; /* @@ -2968,9 +2958,8 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) /* Flush the queued requests to the timeline list (for retiring). */ while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { i915_request_mark_eio(rq); __i915_request_submit(rq); } @@ -3244,7 +3233,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) static struct list_head *virtual_queue(struct virtual_engine *ve) { - return &ve->base.execlists.default_priolist.requests[0]; + return &ve->base.execlists.default_priolist.requests; } static void rcu_virtual_context_destroy(struct work_struct *wrk) @@ -3840,9 +3829,8 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine, count = 0; for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { struct i915_priolist *p = rb_entry(rb, typeof(*p), node); - int i; - priolist_for_each_request(rq, p, i) { + priolist_for_each_request(rq, p) { if (count++ < max - 1) show_request(m, rq, "\t\t", 0); else diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 264b5ebdb021..6bce45f63f37 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -1081,7 +1081,6 @@ create_rewinder(struct intel_context *ce, intel_ring_advance(rq, cs); - rq->sched.attr.priority = I915_PRIORITY_MASK; err = 0; err: i915_request_get(rq); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 920979a89413..693a7e2d67c9 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -733,7 +733,6 @@ create_timestamp(struct intel_context *ce, void *slot, int idx) intel_ring_advance(rq, cs); - rq->sched.attr.priority = I915_PRIORITY_MASK; err = 0; err: i915_request_get(rq); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 23dc0aeaa0ab..3124d8794d87 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -206,9 +206,8 @@ static void __guc_dequeue(struct intel_engine_cs *engine) while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); struct i915_request *rq, *rn; - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { if (last && rq->context != last->context) { if (port == last_port) goto done; @@ -361,9 +360,8 @@ static void guc_reset_cancel(struct intel_engine_cs *engine) /* Flush the queued requests to the timeline list (for retiring). */ while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { list_del_init(&rq->sched.link); __i915_request_submit(rq); dma_fence_set_error(&rq->fence, -EIO); diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index 8aa7866ec6b6..9a7657bb002e 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -27,11 +27,8 @@ enum { #define I915_USER_PRIORITY_SHIFT 0 #define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) -#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) -#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) - /* Smallest priority value that cannot be bumped. */ -#define I915_PRIORITY_INVALID (INT_MIN | (u8)I915_PRIORITY_MASK) +#define I915_PRIORITY_INVALID (INT_MIN) /* * Requests containing performance queries must not be preempted by @@ -45,9 +42,8 @@ enum { #define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1) struct i915_priolist { - struct list_head requests[I915_PRIORITY_COUNT]; + struct list_head requests; struct rb_node node; - unsigned long used; int priority; }; diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 7144239f08df..d9f4cafe5a74 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -43,7 +43,7 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb) static void assert_priolists(struct intel_engine_execlists * const execlists) { struct rb_node *rb; - long last_prio, i; + long last_prio; if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) return; @@ -57,14 +57,6 @@ static void assert_priolists(struct intel_engine_execlists * const execlists) GEM_BUG_ON(p->priority > last_prio); last_prio = p->priority; - - GEM_BUG_ON(!p->used); - for (i = 0; i < ARRAY_SIZE(p->requests); i++) { - if (list_empty(&p->requests[i])) - continue; - - GEM_BUG_ON(!(p->used & BIT(i))); - } } } @@ -75,13 +67,10 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) struct i915_priolist *p; struct rb_node **parent, *rb; bool first = true; - int idx, i; lockdep_assert_held(&engine->active.lock); assert_priolists(execlists); - /* buckets sorted from highest [in slot 0] to lowest priority */ - idx = I915_PRIORITY_COUNT - (prio & I915_PRIORITY_MASK) - 1; prio >>= I915_USER_PRIORITY_SHIFT; if (unlikely(execlists->no_priolist)) prio = I915_PRIORITY_NORMAL; @@ -99,7 +88,7 @@ find_priolist: parent = &rb->rb_right; first = false; } else { - goto out; + return &p->requests; } } @@ -125,15 +114,12 @@ find_priolist: } p->priority = prio; - for (i = 0; i < ARRAY_SIZE(p->requests); i++) - INIT_LIST_HEAD(&p->requests[i]); + INIT_LIST_HEAD(&p->requests); + rb_link_node(&p->node, rb, parent); rb_insert_color_cached(&p->node, &execlists->queue, first); - p->used = 0; -out: - p->used |= BIT(idx); - return &p->requests[idx]; + return &p->requests; } void __i915_priolist_free(struct i915_priolist *p) @@ -363,30 +349,6 @@ void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr) spin_unlock_irq(&schedule_lock); } -static void __bump_priority(struct i915_sched_node *node, unsigned int bump) -{ - struct i915_sched_attr attr = node->attr; - - if (attr.priority & bump) - return; - - attr.priority |= bump; - __i915_schedule(node, &attr); -} - -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump) -{ - unsigned long flags; - - GEM_BUG_ON(bump & ~I915_PRIORITY_MASK); - if (READ_ONCE(rq->sched.attr.priority) & bump) - return; - - spin_lock_irqsave(&schedule_lock, flags); - __bump_priority(&rq->sched, bump); - spin_unlock_irqrestore(&schedule_lock, flags); -} - void i915_sched_node_init(struct i915_sched_node *node) { INIT_LIST_HEAD(&node->signalers_list); @@ -553,8 +515,7 @@ int __init i915_global_scheduler_init(void) if (!global.slab_dependencies) return -ENOMEM; - global.slab_priorities = KMEM_CACHE(i915_priolist, - SLAB_HWCACHE_ALIGN); + global.slab_priorities = KMEM_CACHE(i915_priolist, 0); if (!global.slab_priorities) goto err_priorities; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 4501e5ac2637..858a0938f47a 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -15,17 +15,11 @@ struct drm_printer; -#define priolist_for_each_request(it, plist, idx) \ - for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \ - list_for_each_entry(it, &(plist)->requests[idx], sched.link) +#define priolist_for_each_request(it, plist) \ + list_for_each_entry(it, &(plist)->requests, sched.link) -#define priolist_for_each_request_consume(it, n, plist, idx) \ - for (; \ - (plist)->used ? (idx = __ffs((plist)->used)), 1 : 0; \ - (plist)->used &= ~BIT(idx)) \ - list_for_each_entry_safe(it, n, \ - &(plist)->requests[idx], \ - sched.link) +#define priolist_for_each_request_consume(it, n, plist) \ + list_for_each_entry_safe(it, n, &(plist)->requests, sched.link) void i915_sched_node_init(struct i915_sched_node *node); void i915_sched_node_reinit(struct i915_sched_node *node); @@ -44,8 +38,6 @@ void i915_sched_node_fini(struct i915_sched_node *node); void i915_schedule(struct i915_request *request, const struct i915_sched_attr *attr); -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump); - struct list_head * i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio); -- cgit v1.2.3 From eb5c10cbbc2fc6c743108a3a94c3edfde4059002 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 20 Jan 2021 12:14:39 +0000 Subject: drm/i915: Remove I915_USER_PRIORITY_SHIFT As we do not have any internal priority levels, the priority can be set directed from the user values. Signed-off-by: Chris Wilson Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20210120121439.17600-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-- .../drm/i915/gem/selftests/i915_gem_object_blt.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 10 ++--- drivers/gpu/drm/i915/gt/selftest_execlists.c | 44 ++++++++-------------- drivers/gpu/drm/i915/i915_priolist_types.h | 3 -- drivers/gpu/drm/i915/i915_scheduler.c | 1 - 7 files changed, 24 insertions(+), 48 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e3f8d0034fcf..ebb0a47dca4b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11382,9 +11382,7 @@ int intel_prepare_plane_fb(struct drm_plane *_plane, struct drm_plane_state *_new_plane_state) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY }; struct intel_plane *plane = to_intel_plane(_plane); struct intel_plane_state *new_plane_state = to_intel_plane_state(_new_plane_state); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 4d2f40cf237b..61a7360c4d9a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -679,7 +679,7 @@ __create_context(struct drm_i915_private *i915) kref_init(&ctx->ref); ctx->i915 = i915; - ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL); + ctx->sched.priority = I915_PRIORITY_NORMAL; mutex_init(&ctx->mutex); INIT_LIST_HEAD(&ctx->link); @@ -1959,7 +1959,7 @@ static int set_priority(struct i915_gem_context *ctx, !capable(CAP_SYS_NICE)) return -EPERM; - ctx->sched.priority = I915_USER_PRIORITY(priority); + ctx->sched.priority = priority; context_apply_all(ctx, __apply_priority, ctx); return 0; @@ -2463,7 +2463,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, case I915_CONTEXT_PARAM_PRIORITY: args->size = 0; - args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT; + args->value = ctx->sched.priority; break; case I915_CONTEXT_PARAM_SSEU: diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c index 23b6e11bbc3e..c4c04fb97d14 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c @@ -220,7 +220,7 @@ static int igt_fill_blt_thread(void *arg) return PTR_ERR(ctx); prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng); - ctx->sched.priority = I915_USER_PRIORITY(prio); + ctx->sched.priority = prio; } ce = i915_gem_context_get_engine(ctx, 0); @@ -338,7 +338,7 @@ static int igt_copy_blt_thread(void *arg) return PTR_ERR(ctx); prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng); - ctx->sched.priority = I915_USER_PRIORITY(prio); + ctx->sched.priority = prio; } ce = i915_gem_context_get_engine(ctx, 0); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index 1732a42e9075..ed03c08737f5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -81,9 +81,7 @@ static void show_heartbeat(const struct i915_request *rq, static void heartbeat(struct work_struct *wrk) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN }; struct intel_engine_cs *engine = container_of(wrk, typeof(*engine), heartbeat.work.work); struct intel_context *ce = engine->kernel_context; @@ -127,7 +125,7 @@ static void heartbeat(struct work_struct *wrk) */ attr.priority = 0; if (rq->sched.attr.priority >= attr.priority) - attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT); + attr.priority = I915_PRIORITY_HEARTBEAT; if (rq->sched.attr.priority >= attr.priority) attr.priority = I915_PRIORITY_BARRIER; @@ -285,9 +283,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) int intel_engine_flush_barriers(struct intel_engine_cs *engine) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN }; struct intel_context *ce = engine->kernel_context; struct i915_request *rq; int err; diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 6bce45f63f37..7240a61ccb78 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -321,7 +321,7 @@ static int live_unlite_switch(void *arg) static int live_unlite_preempt(void *arg) { - return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); + return live_unlite_restore(arg, I915_PRIORITY_MAX); } static int live_unlite_ring(void *arg) @@ -1311,9 +1311,7 @@ static int live_timeslice_queue(void *arg) goto err_pin; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct i915_request *rq, *nop; if (!intel_engine_has_preemption(engine)) @@ -1528,14 +1526,12 @@ static int live_busywait_preempt(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) return -ENOMEM; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); if (IS_ERR(obj)) { @@ -1732,14 +1728,12 @@ static int live_preempt(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) goto err_spin_lo; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; for_each_engine(engine, gt, id) { struct igt_live_test t; @@ -1832,7 +1826,7 @@ static int live_late_preempt(void *arg) goto err_ctx_hi; /* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */ - ctx_lo->sched.priority = I915_USER_PRIORITY(1); + ctx_lo->sched.priority = 1; for_each_engine(engine, gt, id) { struct igt_live_test t; @@ -1873,7 +1867,7 @@ static int live_late_preempt(void *arg) goto err_wedged; } - attr.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX); + attr.priority = I915_PRIORITY_MAX; engine->schedule(rq, &attr); if (!igt_wait_for_spinner(&spin_hi, rq)) { @@ -1954,7 +1948,7 @@ static int live_nopreempt(void *arg) return -ENOMEM; if (preempt_client_init(gt, &b)) goto err_client_a; - b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX); + b.ctx->sched.priority = I915_PRIORITY_MAX; for_each_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; @@ -2419,11 +2413,9 @@ err_wedged: static int live_suppress_self_preempt(void *arg) { + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct intel_gt *gt = arg; struct intel_engine_cs *engine; - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX) - }; struct preempt_client a, b; enum intel_engine_id id; int err = -ENOMEM; @@ -2554,9 +2546,7 @@ static int live_chain_preempt(void *arg) goto err_client_hi; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct igt_live_test t; struct i915_request *rq; int ring_size, count, i; @@ -2975,9 +2965,7 @@ static int live_preempt_gang(void *arg) return -EIO; do { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(prio++), - }; + struct i915_sched_attr attr = { .priority = prio++ }; err = create_gang(engine, &rq); if (err) @@ -3013,7 +3001,7 @@ static int live_preempt_gang(void *arg) drm_info_printer(engine->i915->drm.dev); pr_err("Failed to flush chain of %d requests, at %d\n", - prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT); + prio, rq_prio(rq)); intel_engine_dump(engine, &p, "%s\n", engine->name); @@ -3383,14 +3371,12 @@ static int live_preempt_timeout(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) goto err_spin_lo; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; for_each_engine(engine, gt, id) { unsigned long saved_timeout; diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index 9a7657bb002e..bc2fa84f98a8 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -24,9 +24,6 @@ enum { I915_PRIORITY_DISPLAY, }; -#define I915_USER_PRIORITY_SHIFT 0 -#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) - /* Smallest priority value that cannot be bumped. */ #define I915_PRIORITY_INVALID (INT_MIN) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index d9f4cafe5a74..efa638c3acc7 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -71,7 +71,6 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) lockdep_assert_held(&engine->active.lock); assert_priolists(execlists); - prio >>= I915_USER_PRIORITY_SHIFT; if (unlikely(execlists->no_priolist)) prio = I915_PRIORITY_NORMAL; -- cgit v1.2.3 From 536f77b1caa0c50b90b762cc79cf01c447fbd785 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 21 Jan 2021 15:49:50 +0000 Subject: drm/i915/gt: Call stop_ring() from ring resume, again For reasons I cannot explain, except to say this is Sandybridge after all, call stop_ring() again dring ring resume in order to prevent mysterious hard hangs. Testcase: igt/i915_selftest/hangcheck # snb Signed-off-by: Chris Wilson Cc: Mika Kuoppala Acked-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210121154950.19898-3-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 108 ++++++++++++------------ 1 file changed, 56 insertions(+), 52 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 4984ff565424..e4db4318f634 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -183,15 +183,36 @@ static void set_pp_dir(struct intel_engine_cs *engine) } } +static bool stop_ring(struct intel_engine_cs *engine) +{ + /* Empty the ring by skipping to the end */ + ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL)); + ENGINE_POSTING_READ(engine, RING_HEAD); + + /* The ring must be empty before it is disabled */ + ENGINE_WRITE_FW(engine, RING_CTL, 0); + ENGINE_POSTING_READ(engine, RING_CTL); + + /* Then reset the disabled ring */ + ENGINE_WRITE_FW(engine, RING_HEAD, 0); + ENGINE_WRITE_FW(engine, RING_TAIL, 0); + + return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0; +} + static int xcs_resume(struct intel_engine_cs *engine) { - struct drm_i915_private *dev_priv = engine->i915; struct intel_ring *ring = engine->legacy.ring; ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", ring->head, ring->tail); - if (HWS_NEEDS_PHYSICAL(dev_priv)) + /* Double check the ring is empty & disabled before we resume */ + synchronize_hardirq(engine->i915->drm.irq); + if (!stop_ring(engine)) + goto err; + + if (HWS_NEEDS_PHYSICAL(engine->i915)) ring_setup_phys_status_page(engine); else ring_setup_status_page(engine); @@ -228,21 +249,10 @@ static int xcs_resume(struct intel_engine_cs *engine) if (__intel_wait_for_register_fw(engine->uncore, RING_CTL(engine->mmio_base), RING_VALID, RING_VALID, - 5000, 0, NULL)) { - drm_err(&dev_priv->drm, - "%s initialization failed; " - "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", - engine->name, - ENGINE_READ(engine, RING_CTL), - ENGINE_READ(engine, RING_CTL) & RING_VALID, - ENGINE_READ(engine, RING_HEAD), ring->head, - ENGINE_READ(engine, RING_TAIL), ring->tail, - ENGINE_READ(engine, RING_START), - i915_ggtt_offset(ring->vma)); - return -EIO; - } + 5000, 0, NULL)) + goto err; - if (INTEL_GEN(dev_priv) > 2) + if (INTEL_GEN(engine->i915) > 2) ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); @@ -255,6 +265,19 @@ static int xcs_resume(struct intel_engine_cs *engine) /* Papering over lost _interrupts_ immediately following the restart */ intel_engine_signal_breadcrumbs(engine); return 0; + +err: + drm_err(&engine->i915->drm, + "%s initialization failed; " + "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", + engine->name, + ENGINE_READ(engine, RING_CTL), + ENGINE_READ(engine, RING_CTL) & RING_VALID, + ENGINE_READ(engine, RING_HEAD), ring->head, + ENGINE_READ(engine, RING_TAIL), ring->tail, + ENGINE_READ(engine, RING_START), + i915_ggtt_offset(ring->vma)); + return -EIO; } static void sanitize_hwsp(struct intel_engine_cs *engine) @@ -290,23 +313,6 @@ static void xcs_sanitize(struct intel_engine_cs *engine) clflush_cache_range(engine->status_page.addr, PAGE_SIZE); } -static bool stop_ring(struct intel_engine_cs *engine) -{ - /* Empty the ring by skipping to the end */ - ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL)); - ENGINE_POSTING_READ(engine, RING_HEAD); - - /* The ring must be empty before it is disabled */ - ENGINE_WRITE_FW(engine, RING_CTL, 0); - ENGINE_POSTING_READ(engine, RING_CTL); - - /* Then reset the disabled ring */ - ENGINE_WRITE_FW(engine, RING_HEAD, 0); - ENGINE_WRITE_FW(engine, RING_TAIL, 0); - - return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0; -} - static void reset_prepare(struct intel_engine_cs *engine) { /* @@ -329,25 +335,23 @@ static void reset_prepare(struct intel_engine_cs *engine) if (!stop_ring(engine)) { /* G45 ring initialization often fails to reset head to zero */ - drm_dbg(&engine->i915->drm, - "%s head not reset to zero " - "ctl %08x head %08x tail %08x start %08x\n", - engine->name, - ENGINE_READ_FW(engine, RING_CTL), - ENGINE_READ_FW(engine, RING_HEAD), - ENGINE_READ_FW(engine, RING_TAIL), - ENGINE_READ_FW(engine, RING_START)); - } - - if (!stop_ring(engine)) { - drm_err(&engine->i915->drm, - "failed to set %s head to zero " - "ctl %08x head %08x tail %08x start %08x\n", - engine->name, - ENGINE_READ_FW(engine, RING_CTL), - ENGINE_READ_FW(engine, RING_HEAD), - ENGINE_READ_FW(engine, RING_TAIL), - ENGINE_READ_FW(engine, RING_START)); + ENGINE_TRACE(engine, + "HEAD not reset to zero, " + "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n", + ENGINE_READ_FW(engine, RING_CTL), + ENGINE_READ_FW(engine, RING_HEAD), + ENGINE_READ_FW(engine, RING_TAIL), + ENGINE_READ_FW(engine, RING_START)); + if (!stop_ring(engine)) { + drm_err(&engine->i915->drm, + "failed to set %s head to zero " + "ctl %08x head %08x tail %08x start %08x\n", + engine->name, + ENGINE_READ_FW(engine, RING_CTL), + ENGINE_READ_FW(engine, RING_HEAD), + ENGINE_READ_FW(engine, RING_TAIL), + ENGINE_READ_FW(engine, RING_START)); + } } } -- cgit v1.2.3 From 56afa701514a9043a58533b43e16016662800178 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 21 Jan 2021 16:19:36 +0000 Subject: drm/i915: Decrease number of subplatform bits Commit 6ce1c33d6c36 ("drm/i915: Kill INTEL_SUBPLATFORM_AML") removed the only platform which used bit 2 so could also decrease the INTEL_SUBPLATFORM_BITS definition. This is not a fixes material but still lets make it precise. v2: * Fix assert in intel_device_info_subplatform_init by introducing INTEL_SUBPLATFORM_MASK. (Chris) * Update intel_subplatform(). Signed-off-by: Tvrtko Ursulin References: 6ce1c33d6c36 ("drm/i915: Kill INTEL_SUBPLATFORM_AML") Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210121161936.746591-2-tvrtko.ursulin@linux.intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b8c5c7d867bb..479970e2d822 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1298,7 +1298,7 @@ intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) { const unsigned int pi = __platform_mask_index(info, p); - return info->platform_mask[pi] & ((1 << INTEL_SUBPLATFORM_BITS) - 1); + return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; } static __always_inline bool diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 8aaa0f8f6cfd..aeb28d589b2b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -223,7 +223,7 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915) } } - GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); + GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); RUNTIME_INFO(i915)->platform_mask[pi] |= mask; } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index efd138761e14..d44f64b57b7a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -93,7 +93,8 @@ enum intel_platform { * it is fine for the same bit to be used on multiple parent platforms. */ -#define INTEL_SUBPLATFORM_BITS (3) +#define INTEL_SUBPLATFORM_BITS (2) +#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) /* HSW/BDW/SKL/KBL/CFL */ #define INTEL_SUBPLATFORM_ULT (0) -- cgit v1.2.3 From 24f90d66887e904cd0ae47173d29ce6ad3f894dd Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:04 +0000 Subject: drm/i915/gt: SPDX cleanup Clean up the SPDX licence declarations to comply with checkpatch. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/debugfs_gt.c | 1 - drivers/gpu/drm/i915/gt/gen6_renderstate.c | 20 +--------------- drivers/gpu/drm/i915/gt/gen7_renderstate.c | 20 +--------------- drivers/gpu/drm/i915/gt/gen8_renderstate.c | 20 +--------------- drivers/gpu/drm/i915/gt/gen9_renderstate.c | 20 +--------------- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 23 ++---------------- drivers/gpu/drm/i915/gt/intel_context.c | 3 +-- drivers/gpu/drm/i915/gt/intel_context.h | 3 +-- drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 21 +--------------- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_pm.h | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_user.c | 3 +-- drivers/gpu/drm/i915/gt/intel_engine_user.h | 3 +-- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 20 +--------------- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 21 +--------------- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 3 +-- .../gpu/drm/i915/gt/intel_gt_buffer_pool_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +-- drivers/gpu/drm/i915/gt/intel_gt_requests.h | 3 +-- drivers/gpu/drm/i915/gt/intel_llc.c | 3 +-- drivers/gpu/drm/i915/gt/intel_llc.h | 3 +-- drivers/gpu/drm/i915/gt/intel_llc_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 3 +-- drivers/gpu/drm/i915/gt/intel_mocs.c | 21 ++-------------- drivers/gpu/drm/i915/gt/intel_mocs.h | 22 ++--------------- drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +-- drivers/gpu/drm/i915/gt/intel_rc6.h | 3 +-- drivers/gpu/drm/i915/gt/intel_rc6_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_renderstate.c | 24 +------------------ drivers/gpu/drm/i915/gt/intel_renderstate.h | 20 +--------------- drivers/gpu/drm/i915/gt/intel_reset.c | 3 +-- drivers/gpu/drm/i915/gt/intel_reset.h | 3 +-- drivers/gpu/drm/i915/gt/intel_ring.c | 3 +-- drivers/gpu/drm/i915/gt/intel_ring.h | 3 +-- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 28 ++-------------------- drivers/gpu/drm/i915/gt/intel_ring_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_rps.c | 3 +-- drivers/gpu/drm/i915/gt/intel_rps.h | 3 +-- drivers/gpu/drm/i915/gt/intel_rps_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_sseu.c | 3 +-- drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +-- drivers/gpu/drm/i915/gt/intel_timeline.c | 3 +-- drivers/gpu/drm/i915/gt/intel_timeline.h | 21 +--------------- drivers/gpu/drm/i915/gt/intel_timeline_types.h | 3 +-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +-- drivers/gpu/drm/i915/gt/intel_workarounds.h | 3 +-- drivers/gpu/drm/i915/gt/intel_workarounds_types.h | 3 +-- drivers/gpu/drm/i915/gt/mock_engine.c | 21 +--------------- drivers/gpu/drm/i915/gt/mock_engine.h | 21 +--------------- drivers/gpu/drm/i915/gt/selftest_context.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_engine.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_engine.h | 3 +-- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 3 +-- .../gpu/drm/i915/gt/selftest_engine_heartbeat.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_execlists.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 4 +--- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 21 +--------------- drivers/gpu/drm/i915/gt/selftest_llc.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_llc.h | 3 +-- drivers/gpu/drm/i915/gt/selftest_mocs.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_rc6.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 +-- drivers/gpu/drm/i915/gt/selftest_timeline.c | 3 +-- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +-- 75 files changed, 78 insertions(+), 459 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c b/drivers/gpu/drm/i915/gt/debugfs_gt.c index 3a21cf63b3f0..aa18d3b22bed 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: MIT - /* * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/gen6_renderstate.c b/drivers/gpu/drm/i915/gt/gen6_renderstate.c index 11c8e7b3dd7c..555e83f3a93a 100644 --- a/drivers/gpu/drm/i915/gt/gen6_renderstate.c +++ b/drivers/gpu/drm/i915/gt/gen6_renderstate.c @@ -1,25 +1,7 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * * Generated by: intel-gpu-tools-1.8-220-g01153e7 */ diff --git a/drivers/gpu/drm/i915/gt/gen7_renderstate.c b/drivers/gpu/drm/i915/gt/gen7_renderstate.c index 655180646152..c36e84d30d24 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderstate.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderstate.c @@ -1,25 +1,7 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * * Generated by: intel-gpu-tools-1.8-220-g01153e7 */ diff --git a/drivers/gpu/drm/i915/gt/gen8_renderstate.c b/drivers/gpu/drm/i915/gt/gen8_renderstate.c index 95288a34c15d..ef9d7b0dd2da 100644 --- a/drivers/gpu/drm/i915/gt/gen8_renderstate.c +++ b/drivers/gpu/drm/i915/gt/gen8_renderstate.c @@ -1,25 +1,7 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * * Generated by: intel-gpu-tools-1.8-220-g01153e7 */ diff --git a/drivers/gpu/drm/i915/gt/gen9_renderstate.c b/drivers/gpu/drm/i915/gt/gen9_renderstate.c index 7d3ac02f0177..428b724ded3e 100644 --- a/drivers/gpu/drm/i915/gt/gen9_renderstate.c +++ b/drivers/gpu/drm/i915/gt/gen9_renderstate.c @@ -1,25 +1,7 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * * Generated by: intel-gpu-tools-1.19-177-g68e2eab2 */ diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index 34a645d6babd..38cc42783dfb 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -1,25 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * Copyright © 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * + * Copyright © 2015-2021 Intel Corporation */ #include diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 349e7fa1488d..17cf2640b082 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index d24ab6fa0ee5..f83a73a2b39f 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index e10d78601bbd..db25919543bb 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 40024f448c1c..156b85d7fdb8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1,25 +1,6 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #include diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index ed03c08737f5..778bcae5ef2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h index a7b8c0f9e005..a488ea3e84a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c index e67d09259dd0..6372d7826bc9 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h index 418df0a13145..70ea46d6cfb0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index d2346b425547..883bafc44902 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 34e6096f196e..1cbd84eb24e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.h b/drivers/gpu/drm/i915/gt/intel_engine_user.h index f845ea1cbfaa..3dc7e8ab9fbc 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index a357bb431815..f3498e2b9920 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -1,24 +1,6 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2008-2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. */ #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h index 9eef679e1311..25340be5ecf0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h @@ -1,25 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #ifndef __INTEL_GGTT_FENCING_H__ diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 534e435f20bc..14e2ffb6c0e5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT*/ /* - * SPDX-License-Identifier: MIT - * * Copyright � 2003-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h index d8d82c890da8..c49b84fe5164 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2014-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 9830342aa6f4..9fc6c912a4e5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index 886c5cf408a2..f667e976fb2b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index c94e8ac884eb..aef3084e8b16 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h index 63846a856e7e..d0588d8aaa44 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c index babe866126d7..811a11ed181c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h index b29816a04809..ff766966d6fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c index dc06c78c9eeb..14c7b18090f3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h b/drivers/gpu/drm/i915/gt/intel_gt_requests.h index dbac53baf1cb..fcc30a6e4fe9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c index e3f637b3650e..075d741644ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_llc.c +++ b/drivers/gpu/drm/i915/gt/intel_llc.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_llc.h b/drivers/gpu/drm/i915/gt/intel_llc.h index ef09a890d2b7..0e2e3871c919 100644 --- a/drivers/gpu/drm/i915/gt/intel_llc.h +++ b/drivers/gpu/drm/i915/gt/intel_llc.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_llc_types.h b/drivers/gpu/drm/i915/gt/intel_llc_types.h index ecad4687b930..ca5bdf166a23 100644 --- a/drivers/gpu/drm/i915/gt/intel_llc_types.h +++ b/drivers/gpu/drm/i915/gt/intel_llc_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index 65fe76738335..e1bd92ef595f 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2014-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 8acb84960cd0..b14138fd505c 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -1,23 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * Copyright (c) 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. + * Copyright © 2015 Intel Corporation */ #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h index 83371f3e6ba1..d83274f5163b 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.h +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h @@ -1,24 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright (c) 2015 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. + * Copyright © 2015 Intel Corporation */ #ifndef INTEL_MOCS_H diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 9843e1d4327f..9c1c4e955d5d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h index 9f0f23fca8af..e119ec4a0bcc 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h index bfbb623f7a4f..e747492b2f46 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index ca816ba22197..87d2da8fe516 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -1,28 +1,6 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Mika Kuoppala - * */ #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.h b/drivers/gpu/drm/i915/gt/intel_renderstate.h index 713aa1e86c80..48f009203917 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.h +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.h @@ -1,24 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2014 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. */ #ifndef _INTEL_RENDERSTATE_H_ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index afe0342dcd47..416415b4bbe3 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2008-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index 7dbf5cc8a333..adc734e67387 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2008-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 78d1360caa0f..29c87b3c23bc 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index 1700579bdc93..44e902945e80 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index e4db4318f634..79c2f003e6f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -1,30 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * Copyright © 2008-2010 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Eric Anholt - * Zou Nan hai - * Xiang Hai hao - * + * Copyright © 2008-2021 Intel Corporation */ #include "gen2_engine_cs.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ring_types.h b/drivers/gpu/drm/i915/gt/intel_ring_types.h index 1a189ea00fd8..49ccb76dda3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_types.h +++ b/drivers/gpu/drm/i915/gt/intel_ring_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index ee5835c29c03..405d814e9040 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index 8d3c9d663662..1d2cfc98b510 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h b/drivers/gpu/drm/i915/gt/intel_rps_types.h index 029fe13cf303..3941d8551f52 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 8a72e0fe34ca..0d9f74aec8fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 23ba6c2ebe70..4cd1a8a7298a 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 037b0e3ccbed..491b8df174c2 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2016-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h index dcdee692a80e..b1f81d947f8d 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.h +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h @@ -1,25 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #ifndef I915_TIMELINE_H diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h index e360f50706bf..9f677c9b7d06 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h +++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2016 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 8c0c050c4af9..fe26da2f84b2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2014-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h index 8c9c769c2204..15abb68b6c00 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2014-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h index d166a7145720..c214111ea367 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2014-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index 4b4f03b70df7..df7c1b1acc32 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -1,25 +1,6 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #include "gem/i915_gem_context.h" diff --git a/drivers/gpu/drm/i915/gt/mock_engine.h b/drivers/gpu/drm/i915/gt/mock_engine.h index 3f9b698c49d2..cc5ab6e1f37e 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.h +++ b/drivers/gpu/drm/i915/gt/mock_engine.h @@ -1,25 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #ifndef __MOCK_ENGINE_H__ diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c index db738d400168..a02fd70644e2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_context.c +++ b/drivers/gpu/drm/i915/gt/selftest_context.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * SPDX-License-Identifier: GPL-2.0 - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine.c b/drivers/gpu/drm/i915/gt/selftest_engine.c index f65b118e261d..262764f6d90a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * SPDX-License-Identifier: GPL-2.0 - * * Copyright © 2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine.h b/drivers/gpu/drm/i915/gt/selftest_engine.h index ab32d09ec5a1..c6feb3bd2ccc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine.h +++ b/drivers/gpu/drm/i915/gt/selftest_engine.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * SPDX-License-Identifier: GPL-2.0 - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index 439c8984f5fa..84d883de30ee 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * SPDX-License-Identifier: GPL-2.0 - * * Copyright © 2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 223ab88f7e57..b0bae6676140 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index c3d965279fc3..41dc1a542cd6 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * SPDX-License-Identifier: GPL-2.0 - * * Copyright © 2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 7240a61ccb78..4f2853a83075 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c index 5d911f724ebe..c0845bf72dd3 100644 --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c @@ -1,7 +1,5 @@ - +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 463bb6a700c8..d6ce4075602c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1,25 +1,6 @@ +// SPDX-License-Identifier: MIT /* * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * */ #include diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c index a912159693fd..94006f117bbd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_llc.c +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.h b/drivers/gpu/drm/i915/gt/selftest_llc.h index 873f896e72f2..88ee9480022a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_llc.h +++ b/drivers/gpu/drm/i915/gt/selftest_llc.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index cf373c72359e..e6f6807487d4 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 61abc0556601..f097e420ac45 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h index 762fd442d7b2..daf0927909bc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.h +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h @@ -1,6 +1,5 @@ +/* SPDX-License-Identifier: MIT */ /* - * SPDX-License-Identifier: MIT - * * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index 6f3a3687ef0f..d283dce5b4ac 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2017-2018 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 2070b91cb607..37ea46907a7d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -1,6 +1,5 @@ +// SPDX-License-Identifier: MIT /* - * SPDX-License-Identifier: MIT - * * Copyright © 2018 Intel Corporation */ -- cgit v1.2.3 From 2f8aa3b80eb45411c8174acdb6802b71c29f8841 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:05 +0000 Subject: drm/i915/gt: Add some missing blank lines after declaration Trivial checkpatch cleanup. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/debugfs_gt.c | 1 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 3 +++ drivers/gpu/drm/i915/gt/intel_renderstate.c | 1 + drivers/gpu/drm/i915/gt/intel_ring.h | 1 + 5 files changed, 7 insertions(+) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c b/drivers/gpu/drm/i915/gt/debugfs_gt.c index aa18d3b22bed..591eb60785db 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c @@ -36,6 +36,7 @@ void intel_gt_debugfs_register_files(struct dentry *root, { while (count--) { umode_t mode = files->fops->write ? 0644 : 0444; + if (!files->eval || files->eval(data)) debugfs_create_file(files->name, mode, root, data, diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 755522ced60d..03a9d4396373 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -145,6 +145,7 @@ static unsigned int gen8_pt_count(u64 start, u64 end) static unsigned int gen8_pd_top_count(const struct i915_address_space *vm) { unsigned int shift = __gen8_pte_shift(vm->top); + return (vm->total + (1ull << shift) - 1) >> shift; } diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index f3498e2b9920..e891552611d5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -580,6 +580,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) } } else { u32 dimm_c0, dimm_c1; + dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0); dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1); dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; @@ -769,10 +770,12 @@ i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, i = 0; for_each_sgt_page(page, sgt_iter, pages) { char new_bit_17 = page_to_phys(page) >> 17; + if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) { swizzle_page(page); set_page_dirty(page); } + i++; } } diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 87d2da8fe516..8335a43471a9 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -62,6 +62,7 @@ static int render_state_setup(struct intel_renderstate *so, if (i * 4 == rodata->reloc[reloc_index]) { u64 r = s + so->vma->node.start; + s = lower_32_bits(r); if (HAS_64BIT_RELOC(i915)) { if (i + 1 >= rodata->batch_items || diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index 44e902945e80..dbf5f14a136f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -81,6 +81,7 @@ static inline u32 intel_ring_offset(const struct i915_request *rq, void *addr) { /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ u32 offset = addr - rq->ring->vaddr; + GEM_BUG_ON(offset > rq->ring->size); return intel_ring_wrap(rq->ring, offset); } -- cgit v1.2.3 From 1ca9b8da0fdc04f75bd601b3dc986ee69a68f400 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:06 +0000 Subject: drm/i915/gt: Remove repeated words from comments Checkpatch spotted a few repeated words in the comment, genuine mistakes. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-3-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index b31ce0d60028..9f8f8e4b5270 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -3108,7 +3108,7 @@ static void execlists_release(struct intel_engine_cs *engine) static void logical_ring_default_vfuncs(struct intel_engine_cs *engine) { - /* Default vfuncs which can be overriden by each engine. */ + /* Default vfuncs which can be overridden by each engine. */ engine->resume = execlists_resume; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index ec2bf963ced9..fc399ac16eda 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -92,7 +92,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915) } /* - * Certain Gen5 chipsets require require idling the GPU before + * Certain Gen5 chipsets require idling the GPU before * unmapping anything from the GTT when VT-d is enabled. */ static bool needs_idle_maps(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/gt/intel_reset_types.h b/drivers/gpu/drm/i915/gt/intel_reset_types.h index add6b86d9d03..9312b29f5a97 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset_types.h +++ b/drivers/gpu/drm/i915/gt/intel_reset_types.h @@ -32,7 +32,7 @@ struct intel_reset { * * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no * longer use the GPU - similar to #I915_WEDGED bit. The difference in - * in the way we're handling "forced" unwedged (e.g. through debugfs), + * the way we're handling "forced" unwedged (e.g. through debugfs), * which is not allowed in case we failed to initialize. * * #I915_WEDGED_ON_FINI - Similar to #I915_WEDGED_ON_INIT, except we diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index fe26da2f84b2..912e020888d4 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -280,7 +280,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); /* Use Force Non-Coherent whenever executing a 3D context. This is a - * workaround for for a possible hang in the unlikely event a TLB + * workaround for a possible hang in the unlikely event a TLB * invalidation occurs during a PSD flush. */ /* WaForceEnableNonCoherent:bdw,chv */ diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 4f2853a83075..6cfa9a89d891 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -2864,7 +2864,7 @@ static int __live_preempt_ring(struct intel_engine_cs *engine, err = wait_for_submit(engine, rq, HZ / 2); i915_request_put(rq); if (err) { - pr_err("%s: preemption request was not submited\n", + pr_err("%s: preemption request was not submitted\n", engine->name); err = -ETIME; } -- cgit v1.2.3 From 7898843c44221cd058884b2071211260a71d9770 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:07 +0000 Subject: drm/i915/gt: Fixup misaligned function parameters Remember to align parameters to the '(', thanks checkpatch Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-4-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 9f8f8e4b5270..d9fc9533f190 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -3349,8 +3349,8 @@ static int virtual_context_alloc(struct intel_context *ce) } static int virtual_context_pre_pin(struct intel_context *ce, - struct i915_gem_ww_ctx *ww, - void **vaddr) + struct i915_gem_ww_ctx *ww, + void **vaddr) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 912e020888d4..0676239e9344 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1111,11 +1111,10 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || - IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { + IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); - } } static void -- cgit v1.2.3 From ec450576f8f92f0eda9457d26fa61fd14a7fcee1 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:08 +0000 Subject: drm/i915/gt: Remove a bonus newline Trailing newlines before closing the function are best forgotten, or else checkpatch moans. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-5-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 1 - drivers/gpu/drm/i915/gt/intel_rc6.c | 1 - 2 files changed, 2 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index a4242ca8dcd7..582fcaee11aa 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -165,7 +165,6 @@ void intel_gt_init_clock_frequency(struct intel_gt *gt) gt->clock_period_ns, div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX), USEC_PER_SEC)); - } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 9c1c4e955d5d..3b7e62debe7e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -175,7 +175,6 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) /* 3a: Enable RC6 */ set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ - rc6->ctl_enable = GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_RC6_ENABLE | -- cgit v1.2.3 From cbdeab13ad1a2da2189820cae5b8737b8bb941bf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:09 +0000 Subject: drm/i915/gt: Wrap macro arg in () Checkpatch noticed that ppgtt->pd should have been (ppgtt)->pd to avoid issues with macros. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-6-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index e1bd92ef595f..41e5350a7a05 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -39,7 +39,7 @@ #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ u32 *reg_state__ = (reg_state); \ - const u64 addr__ = px_dma(ppgtt->pd); \ + const u64 addr__ = px_dma((ppgtt)->pd); \ (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \ (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \ } while (0) -- cgit v1.2.3 From 512114178eb970d2759bb0ba90f5e5feda75283d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:10 +0000 Subject: drm/i915/gt: Insert spaces into GEN3_L3LOG_SIZE/4 Checkpatch wants spaces, let's give it some spaces. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-7-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 79c2f003e6f6..6771819abb9a 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -741,13 +741,14 @@ static int mi_set_context(struct i915_request *rq, static int remap_l3_slice(struct i915_request *rq, int slice) { +#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32)) u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; int i; if (!remap_info) return 0; - cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); + cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2); if (IS_ERR(cs)) return PTR_ERR(cs); @@ -756,8 +757,8 @@ static int remap_l3_slice(struct i915_request *rq, int slice) * here because no other code should access these registers other than * at initialization time. */ - *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); - for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { + *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW); + for (i = 0; i < L3LOG_DW; i++) { *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); *cs++ = remap_info[i]; } @@ -765,6 +766,7 @@ static int remap_l3_slice(struct i915_request *rq, int slice) intel_ring_advance(rq, cs); return 0; +#undef L3LOG_DW } static int remap_l3(struct i915_request *rq) -- cgit v1.2.3 From 70b0f07770ea7b2949b47b6b8d22c0ad8d533d96 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:11 +0000 Subject: drm/i915/gt: Replace unnecessary ',' with '; ' Checkpatch spotted a couple of commas where we can use the more common ';', and so not worry about the subtle implications of sequence points. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-8-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 ++-- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h index 3357228f3304..6a61a5c3a85a 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h @@ -59,9 +59,9 @@ static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) for (iter = gen6_pde_index(start); \ length > 0 && iter < I915_PDES && \ (pt = i915_pt_entry(pd, iter), true); \ - ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ + ({ u32 temp = ALIGN(start + 1, 1 << GEN6_PDE_SHIFT); \ temp = min(temp - start, length); \ - start += temp, length -= temp; }), ++iter) + start += temp; length -= temp; }), ++iter) #define gen6_for_all_pdes(pt, pd, iter) \ for (iter = 0; \ diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index e326d3c0bc10..08bcb15b47b0 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -115,7 +115,7 @@ intel_setup_fake_lmem(struct drm_i915_private *i915) /* Your mappable aperture belongs to me now! */ mappable_end = pci_resource_len(pdev, 2); - io_start = pci_resource_start(pdev, 2), + io_start = pci_resource_start(pdev, 2); start = i915->params.fake_lmem_start; mem = intel_memory_region_create(i915, -- cgit v1.2.3 From 32ce590bdd34f7603ca8e2b490c9227aa52fb5a6 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:12 +0000 Subject: drm/i915/gt: Add a space before '(' Checkpatch noticed a while(0) and complains about the lack of space. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-9-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 8335a43471a9..0f7c0a148b80 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -43,7 +43,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine) if ((i) >= PAGE_SIZE / sizeof(u32)) \ goto out; \ (batch)[(i)++] = (val); \ - } while(0) + } while (0) static int render_state_setup(struct intel_renderstate *so, struct drm_i915_private *i915) -- cgit v1.2.3 From 041b7f07628969e2c266565d7ecf5b6e44979027 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 22 Jan 2021 19:29:13 +0000 Subject: drm/i915/gt: Replace 'return' with a fall-through Checkpatch worries that the 'return' before an else clause might be redundant. In this case, it is avoiding hitting the MISSING_CASE() warning. Let us appease checkpatch by falling through to the end of the function, which typically means that we then clean up the unused wa_list. Signed-off-by: Chris Wilson Reviewed-by: Michal Wajdeczko Link: https://patchwork.freedesktop.org/patch/msgid/20210122192913.4518-10-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 0676239e9344..3b4a7da60f0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -757,7 +757,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, else if (IS_GEN(i915, 6)) gen6_ctx_workarounds_init(engine, wal); else if (INTEL_GEN(i915) < 8) - return; + ; else MISSING_CASE(INTEL_GEN(i915)); @@ -1209,7 +1209,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) else if (IS_GEN(i915, 4)) gen4_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) - return; + ; else MISSING_CASE(INTEL_GEN(i915)); } @@ -1584,7 +1584,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) else if (IS_SKYLAKE(i915)) skl_whitelist_build(engine); else if (INTEL_GEN(i915) <= 8) - return; + ; else MISSING_CASE(INTEL_GEN(i915)); -- cgit v1.2.3 From f63f452ea6846867b7e775dcc0542b94fb9b1369 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 22 Jan 2021 18:15:13 +0000 Subject: drm/i915/gem: don't trust the dma_buf->size At least for the time being, we need to limit our object sizes such that the number of pages can fit within a 32b signed int. It looks like we should also apply the same restriction to any imported dma-buf. Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210122181514.541436-1-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 04e9c04545ad..dc11497f830b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -244,6 +244,16 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, } } + /* + * XXX: There is a prevalence of the assumption that we fit the + * object's page count inside a 32bit _signed_ variable. Let's document + * this and catch if we ever need to fix it. In the meantime, if you do + * spot such a local variable, please consider fixing! + */ + + if (dma_buf->size >> PAGE_SHIFT > INT_MAX) + return ERR_PTR(-E2BIG); + /* need to attach */ attach = dma_buf_attach(dma_buf, dev->dev); if (IS_ERR(attach)) -- cgit v1.2.3 From ae2fb480f32f657d896d78b6214c2efebfa61993 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 22 Jan 2021 18:15:14 +0000 Subject: drm/i915/gem: consolidate 2big error checking for object sizes Throw it into a simple helper, and throw a warning if we encounter an object which has been initialised with an object size that exceeds our limit of INT_MAX pages. Suggested-by: Chris Wilson Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210122181514.541436-2-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 +-------- drivers/gpu/drm/i915/gem/i915_gem_object.h | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_region.c | 12 +----------- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 16 +--------------- 4 files changed, 29 insertions(+), 34 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index dc11497f830b..5cc8a0b2387f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -244,14 +244,7 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, } } - /* - * XXX: There is a prevalence of the assumption that we fit the - * object's page count inside a 32bit _signed_ variable. Let's document - * this and catch if we ever need to fix it. In the meantime, if you do - * spot such a local variable, please consider fixing! - */ - - if (dma_buf->size >> PAGE_SHIFT > INT_MAX) + if (i915_gem_object_size_2big(dma_buf->size)) return ERR_PTR(-E2BIG); /* need to attach */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index d0ae834d787a..3411ad197fa6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -16,6 +16,32 @@ #include "i915_gem_gtt.h" #include "i915_vma_types.h" +/* + * XXX: There is a prevalence of the assumption that we fit the + * object's page count inside a 32bit _signed_ variable. Let's document + * this and catch if we ever need to fix it. In the meantime, if you do + * spot such a local variable, please consider fixing! + * + * Aside from our own locals (for which we have no excuse!): + * - sg_table embeds unsigned int for num_pages + * - get_user_pages*() mixed ints with longs + */ +#define GEM_CHECK_SIZE_OVERFLOW(sz) \ + GEM_WARN_ON((sz) >> PAGE_SHIFT > INT_MAX) + +static inline bool i915_gem_object_size_2big(u64 size) +{ + struct drm_i915_gem_object *obj; + + if (GEM_CHECK_SIZE_OVERFLOW(size)) + return true; + + if (overflows_type(size, obj->base.size)) + return true; + + return false; +} + void i915_gem_init__objects(struct drm_i915_private *i915); struct drm_i915_gem_object *i915_gem_object_alloc(void); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c index 3e3dad22a683..77dfa908f156 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c @@ -161,17 +161,7 @@ i915_gem_object_create_region(struct intel_memory_region *mem, GEM_BUG_ON(!size); GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT)); - /* - * XXX: There is a prevalence of the assumption that we fit the - * object's page count inside a 32bit _signed_ variable. Let's document - * this and catch if we ever need to fix it. In the meantime, if you do - * spot such a local variable, please consider fixing! - */ - - if (size >> PAGE_SHIFT > INT_MAX) - return ERR_PTR(-E2BIG); - - if (overflows_type(size, obj->base.size)) + if (i915_gem_object_size_2big(size)) return ERR_PTR(-E2BIG); obj = i915_gem_object_alloc(); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index f2eaed6aca3d..3e4785c2dfa2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -770,21 +770,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, I915_USERPTR_UNSYNCHRONIZED)) return -EINVAL; - /* - * XXX: There is a prevalence of the assumption that we fit the - * object's page count inside a 32bit _signed_ variable. Let's document - * this and catch if we ever need to fix it. In the meantime, if you do - * spot such a local variable, please consider fixing! - * - * Aside from our own locals (for which we have no excuse!): - * - sg_table embeds unsigned int for num_pages - * - get_user_pages*() mixed ints with longs - */ - - if (args->user_size >> PAGE_SHIFT > INT_MAX) - return -E2BIG; - - if (overflows_type(args->user_size, obj->base.size)) + if (i915_gem_object_size_2big(args->user_size)) return -E2BIG; if (!args->user_size) -- cgit v1.2.3 From 310528114f7860dbf71ad7766b19c74e30e2b9be Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 25 Jan 2021 14:00:56 +0000 Subject: drm/i915/selftests: Check for engine-reset errors in the middle of workarounds As we reset the engine between verifying the workarounds remain intact, report an engine reset failure. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20210125140136.10494-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 37ea46907a7d..af33a720dbf8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -1219,7 +1219,11 @@ live_engine_reset_workarounds(void *arg) goto err; } - intel_engine_reset(engine, "live_workarounds:idle"); + ret = intel_engine_reset(engine, "live_workarounds:idle"); + if (ret) { + pr_err("%s: Reset failed while idle\n", engine->name); + goto err; + } ok = verify_wa_lists(gt, &lists, "after idle reset"); if (!ok) { @@ -1240,12 +1244,18 @@ live_engine_reset_workarounds(void *arg) ret = request_add_spin(rq, &spin); if (ret) { - pr_err("Spinner failed to start\n"); + pr_err("%s: Spinner failed to start\n", engine->name); igt_spinner_fini(&spin); goto err; } - intel_engine_reset(engine, "live_workarounds:active"); + ret = intel_engine_reset(engine, "live_workarounds:active"); + if (ret) { + pr_err("%s: Reset failed on an active spinner\n", + engine->name); + igt_spinner_fini(&spin); + goto err; + } igt_spinner_end(&spin); igt_spinner_fini(&spin); -- cgit v1.2.3 From b3f0c15a8ef16ce402a2a51f98b43b485c2e0c6d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 25 Jan 2021 14:00:57 +0000 Subject: drm/i915/gt: Move the defer_request waiter active assertion In defer_request() we start with the request we just unsubmitted (that should be the active request on the gpu) and then defer all of its waiters. No waiter should be ahead of the active request, so none should be marked as active. That assert failed. Of particular note this machine was undergoing persistent GPU resets due to underlying HW issues, so that may be a clue. A request is also marked as active when it is retired, regardless of current queue status, and so this assertion failure may be a result of the queue being completed by the reset and then subsequently processed by the tasklet. We can filter out retired requests here by doing the assertion check after the is-ready check (active is a subset of being ready). Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2978 Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20210125140136.10494-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index d9fc9533f190..6fc040d504b4 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1063,7 +1063,6 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) __i915_request_has_started(w) && !__i915_request_is_complete(rq)); - GEM_BUG_ON(i915_request_is_active(w)); if (!i915_request_is_ready(w)) continue; @@ -1071,6 +1070,7 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) continue; GEM_BUG_ON(rq_prio(w) > rq_prio(rq)); + GEM_BUG_ON(i915_request_is_active(w)); list_move_tail(&w->sched.link, &list); } -- cgit v1.2.3 From a29a22917d4cf14ad4e7a8c4c503629d5a771f06 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Tue, 26 Jan 2021 10:30:19 +0000 Subject: drm/i915/buddy: document the unused header bits The largest possible order is (63-PAGE_SHIFT), given that our min chunk size is PAGE_SIZE. With that we should only need at most 6 bits to represent all possible orders, giving us back 4 bits for other potential uses. Include a simple selftest to verify this. Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210126103019.177622-1-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_buddy.c | 3 ++ drivers/gpu/drm/i915/i915_buddy.h | 7 +++-- drivers/gpu/drm/i915/selftests/i915_buddy.c | 48 +++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/i915_buddy.c b/drivers/gpu/drm/i915/i915_buddy.c index 20babbdb297d..3a2f6eecb2fc 100644 --- a/drivers/gpu/drm/i915/i915_buddy.c +++ b/drivers/gpu/drm/i915/i915_buddy.c @@ -48,6 +48,8 @@ static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_block *parent { struct i915_buddy_block *block; + GEM_BUG_ON(order > I915_BUDDY_MAX_ORDER); + block = kmem_cache_zalloc(global.slab_blocks, GFP_KERNEL); if (!block) return NULL; @@ -56,6 +58,7 @@ static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_block *parent block->header |= order; block->parent = parent; + GEM_BUG_ON(block->header & I915_BUDDY_HEADER_UNUSED); return block; } diff --git a/drivers/gpu/drm/i915/i915_buddy.h b/drivers/gpu/drm/i915/i915_buddy.h index ed41f3507cdc..9ce5200f4001 100644 --- a/drivers/gpu/drm/i915/i915_buddy.h +++ b/drivers/gpu/drm/i915/i915_buddy.h @@ -15,7 +15,9 @@ struct i915_buddy_block { #define I915_BUDDY_ALLOCATED (1 << 10) #define I915_BUDDY_FREE (2 << 10) #define I915_BUDDY_SPLIT (3 << 10) -#define I915_BUDDY_HEADER_ORDER GENMASK_ULL(9, 0) +/* Free to be used, if needed in the future */ +#define I915_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6) +#define I915_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) u64 header; struct i915_buddy_block *left; @@ -34,7 +36,8 @@ struct i915_buddy_block { struct list_head tmp_link; }; -#define I915_BUDDY_MAX_ORDER I915_BUDDY_HEADER_ORDER +/* Order-zero must be at least PAGE_SIZE */ +#define I915_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) /* * Binary Buddy System. diff --git a/drivers/gpu/drm/i915/selftests/i915_buddy.c b/drivers/gpu/drm/i915/selftests/i915_buddy.c index 632b912b0bc9..f0f5c4df8dbc 100644 --- a/drivers/gpu/drm/i915/selftests/i915_buddy.c +++ b/drivers/gpu/drm/i915/selftests/i915_buddy.c @@ -727,6 +727,53 @@ err_fini: return err; } +static int igt_buddy_alloc_limit(void *arg) +{ + struct i915_buddy_block *block; + struct i915_buddy_mm mm; + const u64 size = U64_MAX; + int err; + + err = i915_buddy_init(&mm, size, PAGE_SIZE); + if (err) + return err; + + if (mm.max_order != I915_BUDDY_MAX_ORDER) { + pr_err("mm.max_order(%d) != %d\n", + mm.max_order, I915_BUDDY_MAX_ORDER); + err = -EINVAL; + goto out_fini; + } + + block = i915_buddy_alloc(&mm, mm.max_order); + if (IS_ERR(block)) { + err = PTR_ERR(block); + goto out_fini; + } + + if (i915_buddy_block_order(block) != mm.max_order) { + pr_err("block order(%d) != %d\n", + i915_buddy_block_order(block), mm.max_order); + err = -EINVAL; + goto out_free; + } + + if (i915_buddy_block_size(&mm, block) != + BIT_ULL(mm.max_order) * PAGE_SIZE) { + pr_err("block size(%llu) != %llu\n", + i915_buddy_block_size(&mm, block), + BIT_ULL(mm.max_order) * PAGE_SIZE); + err = -EINVAL; + goto out_free; + } + +out_free: + i915_buddy_free(&mm, block); +out_fini: + i915_buddy_fini(&mm); + return err; +} + int i915_buddy_mock_selftests(void) { static const struct i915_subtest tests[] = { @@ -735,6 +782,7 @@ int i915_buddy_mock_selftests(void) SUBTEST(igt_buddy_alloc_pathological), SUBTEST(igt_buddy_alloc_smoke), SUBTEST(igt_buddy_alloc_range), + SUBTEST(igt_buddy_alloc_limit), }; return i915_subtests(tests, NULL); -- cgit v1.2.3 From 2913fa4d7d4236f92a0a90810e9f239fe2781131 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 26 Jan 2021 16:01:55 +0100 Subject: drm/i915/gt: use new tasklet API for execution list This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") v2: Fix up selftests/execlists. Signed-off-by: Emil Renner Berthing Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210126150155.1617-1-kernel@esmil.dk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++-- .../gpu/drm/i915/gt/intel_execlists_submission.c | 28 +++++++++++----------- drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 ++++---- 4 files changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 156b85d7fdb8..0090872964d8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1220,14 +1220,14 @@ void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync) { struct tasklet_struct *t = &engine->execlists.tasklet; - if (!t->func) + if (!t->callback) return; local_bh_disable(); if (tasklet_trylock(t)) { /* Must wait for any GPU reset in progress. */ if (__tasklet_is_enabled(t)) - t->func(t->data); + t->callback(t); tasklet_unlock(t); } local_bh_enable(); diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 6fc040d504b4..8b61c958c031 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2334,9 +2334,10 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) * Check the unread Context Status Buffers and manage the submission of new * contexts to the ELSP accordingly. */ -static void execlists_submission_tasklet(unsigned long data) +static void execlists_submission_tasklet(struct tasklet_struct *t) { - struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + struct intel_engine_cs * const engine = + from_tasklet(engine, t, execlists.tasklet); struct i915_request *post[2 * EXECLIST_MAX_PORTS]; struct i915_request **inactive; @@ -2914,9 +2915,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled) rcu_read_unlock(); } -static void nop_submission_tasklet(unsigned long data) +static void nop_submission_tasklet(struct tasklet_struct *t) { - struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + struct intel_engine_cs * const engine = + from_tasklet(engine, t, execlists.tasklet); /* The driver is wedged; don't process any more events. */ WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN); @@ -3000,7 +3002,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) execlists->queue = RB_ROOT_CACHED; GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); - execlists->tasklet.func = nop_submission_tasklet; + execlists->tasklet.callback = nop_submission_tasklet; spin_unlock_irqrestore(&engine->active.lock, flags); rcu_read_unlock(); @@ -3061,7 +3063,7 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = execlists_submit_request; engine->schedule = i915_schedule; - engine->execlists.tasklet.func = execlists_submission_tasklet; + engine->execlists.tasklet.callback = execlists_submission_tasklet; engine->reset.prepare = execlists_reset_prepare; engine->reset.rewind = execlists_reset_rewind; @@ -3184,8 +3186,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) struct intel_uncore *uncore = engine->uncore; u32 base = engine->mmio_base; - tasklet_init(&engine->execlists.tasklet, - execlists_submission_tasklet, (unsigned long)engine); + tasklet_setup(&engine->execlists.tasklet, execlists_submission_tasklet); timer_setup(&engine->execlists.timer, execlists_timeslice, 0); timer_setup(&engine->execlists.preempt, execlists_preempt, 0); @@ -3427,9 +3428,10 @@ static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) return mask; } -static void virtual_submission_tasklet(unsigned long data) +static void virtual_submission_tasklet(struct tasklet_struct *t) { - struct virtual_engine * const ve = (struct virtual_engine *)data; + struct virtual_engine * const ve = + from_tasklet(ve, t, base.execlists.tasklet); const int prio = READ_ONCE(ve->base.execlists.queue_priority_hint); intel_engine_mask_t mask; unsigned int n; @@ -3639,9 +3641,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings, INIT_LIST_HEAD(virtual_queue(ve)); ve->base.execlists.queue_priority_hint = INT_MIN; - tasklet_init(&ve->base.execlists.tasklet, - virtual_submission_tasklet, - (unsigned long)ve); + tasklet_setup(&ve->base.execlists.tasklet, virtual_submission_tasklet); intel_context_init(&ve->context, &ve->base); @@ -3669,7 +3669,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings, * layering if we handle cloning of the requests and * submitting a copy into each backend. */ - if (sibling->execlists.tasklet.func != + if (sibling->execlists.tasklet.callback != execlists_submission_tasklet) { err = -ENODEV; goto err_put; diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 6cfa9a89d891..5d7fac383add 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -608,7 +608,7 @@ static int live_hold_reset(void *arg) } tasklet_disable(&engine->execlists.tasklet); - engine->execlists.tasklet.func(engine->execlists.tasklet.data); + engine->execlists.tasklet.callback(&engine->execlists.tasklet); GEM_BUG_ON(execlists_active(&engine->execlists) != rq); i915_request_get(rq); @@ -4594,7 +4594,7 @@ static int reset_virtual_engine(struct intel_gt *gt, } tasklet_disable(&engine->execlists.tasklet); - engine->execlists.tasklet.func(engine->execlists.tasklet.data); + engine->execlists.tasklet.callback(&engine->execlists.tasklet); GEM_BUG_ON(execlists_active(&engine->execlists) != rq); /* Fake a preemption event; failed of course */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 3124d8794d87..92688a9b6717 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -237,9 +237,10 @@ done: execlists->active = execlists->inflight; } -static void guc_submission_tasklet(unsigned long data) +static void guc_submission_tasklet(struct tasklet_struct *t) { - struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + struct intel_engine_cs * const engine = + from_tasklet(engine, t, execlists.tasklet); struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port, *rq; unsigned long flags; @@ -608,7 +609,7 @@ static void guc_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = guc_submit_request; engine->schedule = i915_schedule; - engine->execlists.tasklet.func = guc_submission_tasklet; + engine->execlists.tasklet.callback = guc_submission_tasklet; engine->reset.prepare = guc_reset_prepare; engine->reset.rewind = guc_reset_rewind; @@ -700,8 +701,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine) */ GEM_BUG_ON(INTEL_GEN(i915) < 11); - tasklet_init(&engine->execlists.tasklet, - guc_submission_tasklet, (unsigned long)engine); + tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet); guc_default_vfuncs(engine); guc_default_irqs(engine); -- cgit v1.2.3 From 2dfcc7f4e91ff853beab44ce62eeb1163a220e2f Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 27 Jan 2021 13:14:10 +0000 Subject: drm/i915: make local-memory probing a GT operation Device local memory is very much a GT thing, therefore it should be the responsibility of the GT to setup the device local memory region. Suggested-by: Tvrtko Ursulin Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-1-matthew.auld@intel.com [danvet: Rebase conflict.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_gt.c | 32 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +++++++-- drivers/gpu/drm/i915/gt/intel_region_lmem.h | 4 ++-- drivers/gpu/drm/i915/i915_drv.c | 4 ++++ drivers/gpu/drm/i915/intel_memory_region.c | 5 ++--- 6 files changed, 49 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d8e1ab412634..edbee9991248 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -39,6 +39,38 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) intel_uc_init_early(>->uc); } +int intel_gt_probe_lmem(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_memory_region *mem; + int id; + int err; + + mem = intel_gt_setup_fake_lmem(gt); + if (IS_ERR(mem)) { + err = PTR_ERR(mem); + if (err == -ENODEV) + return 0; + + drm_err(&i915->drm, + "Failed to setup region(%d) type=%d\n", + err, INTEL_MEMORY_LOCAL); + return err; + } + + id = INTEL_REGION_LMEM; + + mem->id = id; + mem->type = INTEL_MEMORY_LOCAL; + mem->instance = 0; + + GEM_BUG_ON(!HAS_REGION(i915, id)); + GEM_BUG_ON(i915->mm.regions[id]); + i915->mm.regions[id] = mem; + + return 0; +} + void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) { gt->ggtt = ggtt; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 9157c7411f60..a17bd8b3195f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -36,6 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc) void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915); void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt); +int intel_gt_probe_lmem(struct intel_gt *gt); int intel_gt_init_mmio(struct intel_gt *gt); int __must_check intel_gt_init_hw(struct intel_gt *gt); int intel_gt_init(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 08bcb15b47b0..86f5dca37ef3 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -102,16 +102,22 @@ static const struct intel_memory_region_ops intel_region_lmem_ops = { }; struct intel_memory_region * -intel_setup_fake_lmem(struct drm_i915_private *i915) +intel_gt_setup_fake_lmem(struct intel_gt *gt) { + struct drm_i915_private *i915 = gt->i915; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); struct intel_memory_region *mem; resource_size_t mappable_end; resource_size_t io_start; resource_size_t start; + if (!HAS_LMEM(i915)) + return ERR_PTR(-ENODEV); + + if (!i915->params.fake_lmem_start) + return ERR_PTR(-ENODEV); + GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt)); - GEM_BUG_ON(!i915->params.fake_lmem_start); /* Your mappable aperture belongs to me now! */ mappable_end = pci_resource_len(pdev, 2); diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.h b/drivers/gpu/drm/i915/gt/intel_region_lmem.h index 8ea43e538dab..a4baa0f077a1 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.h +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.h @@ -6,9 +6,9 @@ #ifndef __INTEL_REGION_LMEM_H #define __INTEL_REGION_LMEM_H -struct drm_i915_private; +struct intel_gt; struct intel_memory_region * -intel_setup_fake_lmem(struct drm_i915_private *i915); +intel_gt_setup_fake_lmem(struct intel_gt *gt); #endif /* !__INTEL_REGION_LMEM_H */ diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 43ac73861a4c..a32d847892e0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -566,6 +566,10 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt); + ret = intel_gt_probe_lmem(&dev_priv->gt); + if (ret) + goto err_mem_regions; + ret = i915_ggtt_enable_hw(dev_priv); if (ret) { drm_err(&dev_priv->drm, "failed to enable GGTT\n"); diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c index 1bfcdd89b241..b1b610bfff09 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c @@ -258,9 +258,8 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915) case INTEL_MEMORY_STOLEN: mem = i915_gem_stolen_setup(i915); break; - case INTEL_MEMORY_LOCAL: - mem = intel_setup_fake_lmem(i915); - break; + default: + continue; } if (IS_ERR(mem)) { -- cgit v1.2.3 From a50ca39fbd018889dc48f9bf17ca924546645dbc Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 27 Jan 2021 13:14:11 +0000 Subject: drm/i915: setup the LMEM region Hook up the LMEM region. Addresses will start from zero, and for CPU access we get LMEM_BAR which is just a 1:1 mapping of said region. Based on a patch from Michel Thierry. v2 by Jani: - use intel_uncore_read/intel_uncore_write - remove trailing blank line v3: s/drm_info/drm_dbg for info which in non-pertinent for the user Cc: Lucas De Marchi Cc: Joonas Lahtinen Cc: Rodrigo Vivi Signed-off-by: Matthew Auld Signed-off-by: Lucas De Marchi Signed-off-by: Jani Nikula Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-2-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 36 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_region_lmem.h | 2 ++ 3 files changed, 41 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index edbee9991248..9ac67e0534b7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -46,7 +46,9 @@ int intel_gt_probe_lmem(struct intel_gt *gt) int id; int err; - mem = intel_gt_setup_fake_lmem(gt); + mem = intel_gt_setup_lmem(gt); + if (mem == ERR_PTR(-ENODEV)) + mem = intel_gt_setup_fake_lmem(gt); if (IS_ERR(mem)) { err = PTR_ERR(mem); if (err == -ENODEV) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 86f5dca37ef3..d74e22313e88 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -142,3 +142,39 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) return mem; } + +static struct intel_memory_region *setup_lmem(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct pci_dev *pdev = i915->drm.pdev; + struct intel_memory_region *mem; + resource_size_t io_start; + resource_size_t size; + + if (!IS_DGFX(i915)) + return ERR_PTR(-ENODEV); + + io_start = pci_resource_start(pdev, 2); + size = pci_resource_len(pdev, 2); + + mem = intel_memory_region_create(i915, + 0, + size, + I915_GTT_PAGE_SIZE_4K, + io_start, + &intel_region_lmem_ops); + if (IS_ERR(mem)) + return mem; + + drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region); + drm_dbg(&i915->drm, "Local memory IO start: %pa\n", + &mem->io_start); + drm_info(&i915->drm, "Local memory available: %pa\n", &size); + + return mem; +} + +struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt) +{ + return setup_lmem(gt); +} diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.h b/drivers/gpu/drm/i915/gt/intel_region_lmem.h index a4baa0f077a1..062d0542ae34 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.h +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.h @@ -8,6 +8,8 @@ struct intel_gt; +struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt); + struct intel_memory_region * intel_gt_setup_fake_lmem(struct intel_gt *gt); -- cgit v1.2.3 From 7f2aa5b3014a5f294b968283695b48acf6dbe883 Mon Sep 17 00:00:00 2001 From: CQ Tang Date: Wed, 27 Jan 2021 13:14:12 +0000 Subject: drm/i915: reserve stolen for LMEM region The lmem region needs to remove the stolen part, which should just be a case of snipping it off the end. Signed-off-by: CQ Tang Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-3-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 14 ++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 12 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index d74e22313e88..8ec244b02422 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -146,20 +146,25 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) static struct intel_memory_region *setup_lmem(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = gt->uncore; struct pci_dev *pdev = i915->drm.pdev; struct intel_memory_region *mem; resource_size_t io_start; - resource_size_t size; + resource_size_t lmem_size; if (!IS_DGFX(i915)) return ERR_PTR(-ENODEV); + /* Stolen starts from GSMBASE on DG1 */ + lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); + io_start = pci_resource_start(pdev, 2); - size = pci_resource_len(pdev, 2); + if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) + return ERR_PTR(-ENODEV); mem = intel_memory_region_create(i915, 0, - size, + lmem_size, I915_GTT_PAGE_SIZE_4K, io_start, &intel_region_lmem_ops); @@ -169,7 +174,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region); drm_dbg(&i915->drm, "Local memory IO start: %pa\n", &mem->io_start); - drm_info(&i915->drm, "Local memory available: %pa\n", &size); + drm_info(&i915->drm, "Local memory available: %pa\n", + &lmem_size); return mem; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 765ba64442ab..cbf7a60afe54 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12187,6 +12187,8 @@ enum skl_power_gate { #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ +#define GEN12_GSMBASE _MMIO(0x108100) + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ -- cgit v1.2.3 From adeca641bcb64f9e4fd477c0d1fe482f18934e90 Mon Sep 17 00:00:00 2001 From: Abdiel Janulgue Date: Wed, 27 Jan 2021 13:14:13 +0000 Subject: drm/i915: introduce mem->reserved In the following patch we need to reserve regions unaccessible to the driver during initialization, so add mem->reserved for collecting such regions. v2: turn into an actual intel_memory_region_reserve api Cc: Imre Deak Signed-off-by: Abdiel Janulgue Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-4-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_memory_region.c | 14 ++++ drivers/gpu/drm/i915/intel_memory_region.h | 5 ++ .../gpu/drm/i915/selftests/intel_memory_region.c | 77 ++++++++++++++++++++++ 3 files changed, 96 insertions(+) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c index b1b610bfff09..49d306b5532f 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c @@ -156,9 +156,22 @@ int intel_memory_region_init_buddy(struct intel_memory_region *mem) void intel_memory_region_release_buddy(struct intel_memory_region *mem) { + i915_buddy_free_list(&mem->mm, &mem->reserved); i915_buddy_fini(&mem->mm); } +int intel_memory_region_reserve(struct intel_memory_region *mem, + u64 offset, u64 size) +{ + int ret; + + mutex_lock(&mem->mm_lock); + ret = i915_buddy_alloc_range(&mem->mm, &mem->reserved, offset, size); + mutex_unlock(&mem->mm_lock); + + return ret; +} + struct intel_memory_region * intel_memory_region_create(struct drm_i915_private *i915, resource_size_t start, @@ -185,6 +198,7 @@ intel_memory_region_create(struct drm_i915_private *i915, mutex_init(&mem->objects.lock); INIT_LIST_HEAD(&mem->objects.list); INIT_LIST_HEAD(&mem->objects.purgeable); + INIT_LIST_HEAD(&mem->reserved); mutex_init(&mem->mm_lock); diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h index 6ffc0673f005..d17e4fe3123c 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.h +++ b/drivers/gpu/drm/i915/intel_memory_region.h @@ -89,6 +89,8 @@ struct intel_memory_region { unsigned int id; char name[8]; + struct list_head reserved; + dma_addr_t remap_addr; struct { @@ -113,6 +115,9 @@ void __intel_memory_region_put_pages_buddy(struct intel_memory_region *mem, struct list_head *blocks); void __intel_memory_region_put_block_buddy(struct i915_buddy_block *block); +int intel_memory_region_reserve(struct intel_memory_region *mem, + u64 offset, u64 size); + struct intel_memory_region * intel_memory_region_create(struct drm_i915_private *i915, resource_size_t start, diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index ce7adfa3bca0..64348528e1d5 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -144,6 +144,82 @@ static bool is_contiguous(struct drm_i915_gem_object *obj) return true; } +static int igt_mock_reserve(void *arg) +{ + struct intel_memory_region *mem = arg; + resource_size_t avail = resource_size(&mem->region); + struct drm_i915_gem_object *obj; + const u32 chunk_size = SZ_32M; + u32 i, offset, count, *order; + u64 allocated, cur_avail; + I915_RND_STATE(prng); + LIST_HEAD(objects); + int err = 0; + + if (!list_empty(&mem->reserved)) { + pr_err("%s region reserved list is not empty\n", __func__); + return -EINVAL; + } + + count = avail / chunk_size; + order = i915_random_order(count, &prng); + if (!order) + return 0; + + /* Reserve a bunch of ranges within the region */ + for (i = 0; i < count; ++i) { + u64 start = order[i] * chunk_size; + u64 size = i915_prandom_u32_max_state(chunk_size, &prng); + + /* Allow for some really big holes */ + if (!size) + continue; + + size = round_up(size, PAGE_SIZE); + offset = igt_random_offset(&prng, 0, chunk_size, size, + PAGE_SIZE); + + err = intel_memory_region_reserve(mem, start + offset, size); + if (err) { + pr_err("%s failed to reserve range", __func__); + goto out_close; + } + + /* XXX: maybe sanity check the block range here? */ + avail -= size; + } + + /* Try to see if we can allocate from the remaining space */ + allocated = 0; + cur_avail = avail; + do { + u32 size = i915_prandom_u32_max_state(cur_avail, &prng); + + size = max_t(u32, round_up(size, PAGE_SIZE), PAGE_SIZE); + obj = igt_object_create(mem, &objects, size, 0); + if (IS_ERR(obj)) { + if (PTR_ERR(obj) == -ENXIO) + break; + + err = PTR_ERR(obj); + goto out_close; + } + cur_avail -= size; + allocated += size; + } while (1); + + if (allocated != avail) { + pr_err("%s mismatch between allocation and free space", __func__); + err = -EINVAL; + } + +out_close: + kfree(order); + close_objects(mem, &objects); + i915_buddy_free_list(&mem->mm, &mem->reserved); + return err; +} + static int igt_mock_contiguous(void *arg) { struct intel_memory_region *mem = arg; @@ -930,6 +1006,7 @@ static int perf_memcpy(void *arg) int intel_memory_region_mock_selftests(void) { static const struct i915_subtest tests[] = { + SUBTEST(igt_mock_reserve), SUBTEST(igt_mock_fill), SUBTEST(igt_mock_contiguous), SUBTEST(igt_mock_splintered_region), -- cgit v1.2.3 From 7c5cc941330df5a1868da6c8fb3710d804c11bc8 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 27 Jan 2021 13:14:14 +0000 Subject: drm/i915/dg1: Reserve first 1MB of local memory On DG1 A0/B0 steppings the first 1MB of local memory must be reserved. One reason for this is that the 0xA0000-0xB0000 range is not accessible by the display, probably since this region is redirected to another memory location for legacy VGA compatibility. BSpec: 50586 Testcase: igt/kms_big_fb/linear-64bpp-rotate-0 v2: - Reserve the memory on B0 as well. v3: replace DRM_DEBUG/DRM_ERROR with drm_dbg/drm_err v4: fix the insanity Signed-off-by: Imre Deak Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-5-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 8ec244b02422..8c498e96b01d 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -143,6 +143,38 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) return mem; } +static bool get_legacy_lowmem_region(struct intel_uncore *uncore, + u64 *start, u32 *size) +{ + if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0)) + return false; + + *start = 0; + *size = SZ_1M; + + drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n", + *start, *start + *size); + + return true; +} + +static int reserve_lowmem_region(struct intel_uncore *uncore, + struct intel_memory_region *mem) +{ + u64 reserve_start; + u32 reserve_size; + int ret; + + if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size)) + return 0; + + ret = intel_memory_region_reserve(mem, reserve_start, reserve_size); + if (ret) + drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n"); + + return ret; +} + static struct intel_memory_region *setup_lmem(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; @@ -151,6 +183,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_memory_region *mem; resource_size_t io_start; resource_size_t lmem_size; + int err; if (!IS_DGFX(i915)) return ERR_PTR(-ENODEV); @@ -171,6 +204,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (IS_ERR(mem)) return mem; + err = reserve_lowmem_region(uncore, mem); + if (err) + goto err_region_put; + drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region); drm_dbg(&i915->drm, "Local memory IO start: %pa\n", &mem->io_start); @@ -178,6 +215,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) &lmem_size); return mem; + +err_region_put: + intel_memory_region_put(mem); + return ERR_PTR(err); } struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt) -- cgit v1.2.3 From ba485bc8edf1a29eaea8343102c0824f45d8252b Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 27 Jan 2021 13:14:15 +0000 Subject: drm/i915: allocate context from LMEM Prefer allocating the context from LMEM on dgfx. Based on a patch from Michel Thierry. v2: flatten the chain Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-6-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 94f485b591af..1eb11b756b95 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3,6 +3,8 @@ * Copyright © 2014 Intel Corporation */ +#include "gem/i915_gem_lmem.h" + #include "gen8_engine_cs.h" #include "i915_drv.h" #include "i915_perf.h" @@ -808,7 +810,9 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) context_size += PAGE_SIZE; } - obj = i915_gem_object_create_shmem(engine->i915, context_size); + obj = i915_gem_object_create_lmem(engine->i915, context_size, 0); + if (IS_ERR(obj)) + obj = i915_gem_object_create_shmem(engine->i915, context_size); if (IS_ERR(obj)) return ERR_CAST(obj); -- cgit v1.2.3 From 772d5bdf2ba7ce390b685c0a5934cf524854ecbc Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 27 Jan 2021 13:14:16 +0000 Subject: drm/i915: move engine scratch to LMEM Prefer allocating the engine scratch from LMEM on dgfx. v2: flatten the chain Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-7-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_gt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 9ac67e0534b7..35ff68ada4f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -4,6 +4,8 @@ */ #include "debugfs_gt.h" + +#include "gem/i915_gem_lmem.h" #include "i915_drv.h" #include "intel_context.h" #include "intel_gt.h" @@ -378,11 +380,13 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) struct i915_vma *vma; int ret; - obj = i915_gem_object_create_stolen(i915, size); + obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE); + if (IS_ERR(obj)) + obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); if (IS_ERR(obj)) { - DRM_ERROR("Failed to allocate scratch page\n"); + drm_err(&i915->drm, "Failed to allocate scratch page\n"); return PTR_ERR(obj); } -- cgit v1.2.3 From d712f4ce25d3935d6e124a84f7f8d640ab0da611 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Wed, 27 Jan 2021 13:14:17 +0000 Subject: drm/i915: allocate cmd ring in lmem Prefer allocating the cmd ring from LMEM on dgfx. Signed-off-by: Michel Thierry Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210127131417.393872-8-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_ring.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 29c87b3c23bc..aee0a77c77e0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -3,6 +3,7 @@ * Copyright © 2019 Intel Corporation */ +#include "gem/i915_gem_lmem.h" #include "gem/i915_gem_object.h" #include "i915_drv.h" @@ -108,8 +109,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct drm_i915_gem_object *obj; struct i915_vma *vma; - obj = ERR_PTR(-ENODEV); - if (i915_ggtt_has_aperture(ggtt)) + obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE); + if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt)) obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); -- cgit v1.2.3 From c10e4a7960f3032b0313c4b684e0b4025b4c138d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 1 Feb 2021 08:56:22 +0000 Subject: drm/i915: Protect against request freeing during cancellation on wedging As soon as we mark a request as completed, it may be retired. So when cancelling a request and marking it complete, make sure we first keep a reference to the request. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210201085715.27435-4-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 19 +++++++++++-------- drivers/gpu/drm/i915/gt/intel_reset.c | 15 ++++++--------- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/mock_engine.c | 8 +++++--- drivers/gpu/drm/i915/i915_request.c | 9 +++++++-- drivers/gpu/drm/i915/i915_request.h | 2 +- 6 files changed, 31 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 8b61c958c031..08a7f5b671e3 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2954,7 +2954,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) /* Mark all executing requests as skipped. */ list_for_each_entry(rq, &engine->active.requests, sched.link) - i915_request_mark_eio(rq); + i915_request_put(i915_request_mark_eio(rq)); intel_engine_signal_breadcrumbs(engine); /* Flush the queued requests to the timeline list (for retiring). */ @@ -2962,8 +2962,10 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) struct i915_priolist *p = to_priolist(rb); priolist_for_each_request_consume(rq, rn, p) { - i915_request_mark_eio(rq); - __i915_request_submit(rq); + if (i915_request_mark_eio(rq)) { + __i915_request_submit(rq); + i915_request_put(rq); + } } rb_erase_cached(&p->node, &execlists->queue); @@ -2972,7 +2974,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) /* On-hold requests will be flushed to timeline upon their release */ list_for_each_entry(rq, &engine->active.hold, sched.link) - i915_request_mark_eio(rq); + i915_request_put(i915_request_mark_eio(rq)); /* Cancel all attached virtual engines */ while ((rb = rb_first_cached(&execlists->virtual))) { @@ -2985,10 +2987,11 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) spin_lock(&ve->base.active.lock); rq = fetch_and_zero(&ve->request); if (rq) { - i915_request_mark_eio(rq); - - rq->engine = engine; - __i915_request_submit(rq); + if (i915_request_mark_eio(rq)) { + rq->engine = engine; + __i915_request_submit(rq); + i915_request_put(rq); + } i915_request_put(rq); ve->base.execlists.queue_priority_hint = INT_MIN; diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 416415b4bbe3..c8cf3981ad7f 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -786,18 +786,15 @@ static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake) static void nop_submit_request(struct i915_request *request) { - struct intel_engine_cs *engine = request->engine; - unsigned long flags; - RQ_TRACE(request, "-EIO\n"); - i915_request_set_error_once(request, -EIO); - spin_lock_irqsave(&engine->active.lock, flags); - __i915_request_submit(request); - i915_request_mark_complete(request); - spin_unlock_irqrestore(&engine->active.lock, flags); + request = i915_request_mark_eio(request); + if (request) { + i915_request_submit(request); + intel_engine_signal_breadcrumbs(request->engine); - intel_engine_signal_breadcrumbs(engine); + i915_request_put(request); + } } static void __intel_gt_set_wedged(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 6771819abb9a..f9933e8646c3 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -411,7 +411,7 @@ static void reset_cancel(struct intel_engine_cs *engine) /* Mark all submitted requests as skipped. */ list_for_each_entry(request, &engine->active.requests, sched.link) - i915_request_mark_eio(request); + i915_request_put(i915_request_mark_eio(request)); intel_engine_signal_breadcrumbs(engine); /* Remaining _unready_ requests will be nop'ed when submitted */ diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index df7c1b1acc32..cf1269e74998 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -239,13 +239,15 @@ static void mock_reset_cancel(struct intel_engine_cs *engine) /* Mark all submitted requests as skipped. */ list_for_each_entry(rq, &engine->active.requests, sched.link) - i915_request_mark_eio(rq); + i915_request_put(i915_request_mark_eio(rq)); intel_engine_signal_breadcrumbs(engine); /* Cancel and submit all pending requests. */ list_for_each_entry(rq, &mock->hw_queue, mock.link) { - i915_request_mark_eio(rq); - __i915_request_submit(rq); + if (i915_request_mark_eio(rq)) { + __i915_request_submit(rq); + i915_request_put(rq); + } } INIT_LIST_HEAD(&mock->hw_queue); diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 22e39d938f17..8b4223325188 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -514,15 +514,20 @@ void i915_request_set_error_once(struct i915_request *rq, int error) } while (!try_cmpxchg(&rq->fence.error, &old, error)); } -void i915_request_mark_eio(struct i915_request *rq) +struct i915_request *i915_request_mark_eio(struct i915_request *rq) { if (__i915_request_is_complete(rq)) - return; + return NULL; GEM_BUG_ON(i915_request_signaled(rq)); + /* As soon as the request is completed, it may be retired */ + rq = i915_request_get(rq); + i915_request_set_error_once(rq, -EIO); i915_request_mark_complete(rq); + + return rq; } bool __i915_request_submit(struct i915_request *request) diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 1bfe214a47e9..c0bd4cb8786a 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -311,7 +311,7 @@ i915_request_create(struct intel_context *ce); void __i915_request_skip(struct i915_request *rq); void i915_request_set_error_once(struct i915_request *rq, int error); -void i915_request_mark_eio(struct i915_request *rq); +struct i915_request *i915_request_mark_eio(struct i915_request *rq); struct i915_request *__i915_request_commit(struct i915_request *request); void __i915_request_queue(struct i915_request *rq, -- cgit v1.2.3 From 8bb92516da076968411c65100ea9d11c9440b783 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 1 Feb 2021 10:04:48 +0000 Subject: drm/i915/selftests: Use a single copy of the mocs table Instead of copying the whole table to each category (mocs, l3cc), use a single table with a pointer to it if the category is enabled. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210201100448.9802-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/selftest_mocs.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index e6f6807487d4..44609d1c7780 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -12,8 +12,9 @@ #include "selftests/igt_spinner.h" struct live_mocs { - struct drm_i915_mocs_table mocs; - struct drm_i915_mocs_table l3cc; + struct drm_i915_mocs_table table; + struct drm_i915_mocs_table *mocs; + struct drm_i915_mocs_table *l3cc; struct i915_vma *scratch; void *vaddr; }; @@ -58,21 +59,20 @@ static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt) { - struct drm_i915_mocs_table table; unsigned int flags; int err; memset(arg, 0, sizeof(*arg)); - flags = get_mocs_settings(gt->i915, &table); + flags = get_mocs_settings(gt->i915, &arg->table); if (!flags) return -EINVAL; if (flags & HAS_RENDER_L3CC) - arg->l3cc = table; + arg->l3cc = &arg->table; if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS)) - arg->mocs = table; + arg->mocs = &arg->table; arg->scratch = __vm_create_scratch_for_read(>->ggtt->vm, PAGE_SIZE); if (IS_ERR(arg->scratch)) @@ -130,6 +130,9 @@ static int read_mocs_table(struct i915_request *rq, { u32 addr; + if (!table) + return 0; + if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) addr = global_mocs_offset(); else @@ -144,6 +147,9 @@ static int read_l3cc_table(struct i915_request *rq, { u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); + if (!table) + return 0; + return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); } @@ -154,6 +160,9 @@ static int check_mocs_table(struct intel_engine_cs *engine, unsigned int i; u32 expect; + if (!table) + return 0; + for_each_mocs(expect, table, i) { if (**vaddr != expect) { pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n", @@ -185,6 +194,9 @@ static int check_l3cc_table(struct intel_engine_cs *engine, unsigned int i; u32 expect; + if (!table) + return 0; + for_each_l3cc(expect, table, i) { if (!mcr_range(engine->i915, reg) && **vaddr != expect) { pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n", @@ -222,9 +234,9 @@ static int check_mocs_engine(struct live_mocs *arg, /* Read the mocs tables back using SRM */ offset = i915_ggtt_offset(vma); if (!err) - err = read_mocs_table(rq, &arg->mocs, &offset); + err = read_mocs_table(rq, arg->mocs, &offset); if (!err && ce->engine->class == RENDER_CLASS) - err = read_l3cc_table(rq, &arg->l3cc, &offset); + err = read_l3cc_table(rq, arg->l3cc, &offset); offset -= i915_ggtt_offset(vma); GEM_BUG_ON(offset > PAGE_SIZE); @@ -235,9 +247,9 @@ static int check_mocs_engine(struct live_mocs *arg, /* Compare the results against the expected tables */ vaddr = arg->vaddr; if (!err) - err = check_mocs_table(ce->engine, &arg->mocs, &vaddr); + err = check_mocs_table(ce->engine, arg->mocs, &vaddr); if (!err && ce->engine->class == RENDER_CLASS) - err = check_l3cc_table(ce->engine, &arg->l3cc, &vaddr); + err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); if (err) return err; -- cgit v1.2.3 From c9a995e5a768c10a2d09d1fe196c69e7736ed9c3 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 1 Feb 2021 16:42:22 +0000 Subject: drm/i915/gt: Retire unexpected starting state error dumping We have not seen an occurrence of the false restart state recenty, and if we did see such an event from inside engine-reset, it would deadlock on trying to suspend the tasklet to read the register state (from inside the tasklet). Instead, we inspect the context state before submission which will alert us to any issues prior to execution on HW. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Andi Shyti Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20210201164222.14455-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 08a7f5b671e3..2603a82b7a2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2720,31 +2720,11 @@ static void enable_execlists(struct intel_engine_cs *engine) enable_error_interrupt(engine); } -static bool unexpected_starting_state(struct intel_engine_cs *engine) -{ - bool unexpected = false; - - if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) { - drm_dbg(&engine->i915->drm, - "STOP_RING still set in RING_MI_MODE\n"); - unexpected = true; - } - - return unexpected; -} - static int execlists_resume(struct intel_engine_cs *engine) { intel_mocs_init_engine(engine); - intel_breadcrumbs_reset(engine->breadcrumbs); - if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { - struct drm_printer p = drm_debug_printer(__func__); - - intel_engine_dump(engine, &p, NULL); - } - enable_execlists(engine); return 0; -- cgit v1.2.3 From c538d54e49d8890e9df987c35919ea6a5f963dc9 Mon Sep 17 00:00:00 2001 From: Zbigniew Kempczyński Date: Wed, 3 Feb 2021 17:12:29 +0000 Subject: drm/i915: Distinction of memory regions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for Xe HP multi-tile architecture with multiple memory regions, we need to be able differentiate multiple instances of device local-memory. Note that the region name is just to give it a human friendly identifier, instead of using class/instance which also uniquely identifies the region. So far the region name is only for our own internal debugging in the kernel(like in the selftests), or debugfs which prints the list of regions, including the regions name. v2: add commentary for our current region name use Signed-off-by: Zbigniew Kempczyński Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210203171231.551338-1-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 35ff68ada4f1..ca76f93bc03d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -68,6 +68,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt) mem->type = INTEL_MEMORY_LOCAL; mem->instance = 0; + intel_memory_region_set_name(mem, "local%u", mem->instance); + GEM_BUG_ON(!HAS_REGION(i915, id)); GEM_BUG_ON(i915->mm.regions[id]); i915->mm.regions[id] = mem; diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 8c498e96b01d..be6f2c8f5184 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -90,8 +90,6 @@ region_lmem_init(struct intel_memory_region *mem) if (ret) io_mapping_fini(&mem->iomap); - intel_memory_region_set_name(mem, "local"); - return ret; } -- cgit v1.2.3 From 11724eea0d57c5bf82bf1d0082819d407f1c886e Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 3 Feb 2021 17:12:30 +0000 Subject: drm/i915/gtt/dg1: add PTE_LM plumbing for ppGTT For the PTEs we get an LM bit, to signal whether the page resides in SMEM or LMEM. BSpec: 45040 v2: just use gen8_pte_encode for dg1 Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Venkata Sandeep Dhanalakota Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210203171231.551338-2-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +++++++++++- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gt/intel_ppgtt.c | 4 ++++ 3 files changed, 18 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 03a9d4396373..176c19633412 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -5,6 +5,8 @@ #include +#include "gem/i915_gem_lmem.h" + #include "gen8_ppgtt.h" #include "i915_scatterlist.h" #include "i915_trace.h" @@ -35,6 +37,9 @@ static u64 gen8_pte_encode(dma_addr_t addr, if (unlikely(flags & PTE_READ_ONLY)) pte &= ~_PAGE_RW; + if (flags & PTE_LM) + pte |= GEN12_PPGTT_PTE_LM; + switch (level) { case I915_CACHE_NONE: pte |= PPAT_UNCACHED; @@ -558,6 +563,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm, static int gen8_init_scratch(struct i915_address_space *vm) { + u32 pte_flags; int ret; int i; @@ -581,9 +587,13 @@ static int gen8_init_scratch(struct i915_address_space *vm) if (ret) return ret; + pte_flags = vm->has_read_only; + if (i915_gem_object_is_lmem(vm->scratch[0])) + pte_flags |= PTE_LM; + vm->scratch[0]->encode = gen8_pte_encode(px_dma(vm->scratch[0]), - I915_CACHE_LLC, vm->has_read_only); + I915_CACHE_LLC, pte_flags); for (i = 1; i <= vm->top; i++) { struct drm_i915_gem_object *obj; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 29c10fde8ce3..0eef625dd787 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -85,6 +85,8 @@ typedef u64 gen8_pte_t; #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) #define BYT_PTE_WRITEABLE REG_BIT(1) +#define GEN12_PPGTT_PTE_LM BIT_ULL(11) + /* * Cacheability Control is a 4-bit value. The low three bits are stored in bits * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. @@ -264,6 +266,7 @@ struct i915_address_space { enum i915_cache_level level, u32 flags); /* Create a valid PTE */ #define PTE_READ_ONLY BIT(0) +#define PTE_LM BIT(1) void (*allocate_va_range)(struct i915_address_space *vm, struct i915_vm_pt_stash *stash, diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index 3f940ae27028..a91955af50a6 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -5,6 +5,8 @@ #include +#include "gem/i915_gem_lmem.h" + #include "i915_trace.h" #include "intel_gtt.h" #include "gen6_ppgtt.h" @@ -192,6 +194,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm, pte_flags = 0; if (i915_gem_object_is_readonly(vma->obj)) pte_flags |= PTE_READ_ONLY; + if (i915_gem_object_is_lmem(vma->obj)) + pte_flags |= PTE_LM; vm->insert_entries(vm, vma, cache_level, pte_flags); wmb(); -- cgit v1.2.3 From e762bdf582af5b4c9af654553b3c5efc84c7ff65 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Wed, 3 Feb 2021 17:12:31 +0000 Subject: drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT For the PTEs we get an LM bit, to signal whether the page resides in SMEM or LMEM. Based on a patch from Michel Thierry. BSpec: 45015 Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210203171231.551338-3-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 +++++++++++++++++++----- drivers/gpu/drm/i915/gt/intel_gtt.h | 4 +++- 2 files changed, 22 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index fc399ac16eda..b0b8ded834f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -10,6 +10,8 @@ #include +#include "gem/i915_gem_lmem.h" + #include "intel_gt.h" #include "i915_drv.h" #include "i915_scatterlist.h" @@ -189,7 +191,12 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t addr, enum i915_cache_level level, u32 flags) { - return addr | _PAGE_PRESENT; + gen8_pte_t pte = addr | _PAGE_PRESENT; + + if (flags & PTE_LM) + pte |= GEN12_GGTT_PTE_LM; + + return pte; } static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) @@ -201,13 +208,13 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, dma_addr_t addr, u64 offset, enum i915_cache_level level, - u32 unused) + u32 flags) { struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); gen8_pte_t __iomem *pte = (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0)); + gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags)); ggtt->invalidate(ggtt); } @@ -217,7 +224,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, enum i915_cache_level level, u32 flags) { - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0); + const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags); struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); gen8_pte_t __iomem *gte; gen8_pte_t __iomem *end; @@ -459,6 +466,8 @@ static void ggtt_bind_vma(struct i915_address_space *vm, pte_flags = 0; if (i915_gem_object_is_readonly(obj)) pte_flags |= PTE_READ_ONLY; + if (i915_gem_object_is_lmem(obj)) + pte_flags |= PTE_LM; vm->insert_entries(vm, vma, cache_level, pte_flags); vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; @@ -794,6 +803,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) struct drm_i915_private *i915 = ggtt->vm.i915; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); phys_addr_t phys_addr; + u32 pte_flags; int ret; /* For Modern GENs the PTEs and register space are split in the BAR */ @@ -823,9 +833,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return ret; } + pte_flags = 0; + if (i915_gem_object_is_lmem(ggtt->vm.scratch[0])) + pte_flags |= PTE_LM; + ggtt->vm.scratch[0]->encode = ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]), - I915_CACHE_NONE, 0); + I915_CACHE_NONE, pte_flags); return 0; } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 0eef625dd787..24b5808df16d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -85,7 +85,9 @@ typedef u64 gen8_pte_t; #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) #define BYT_PTE_WRITEABLE REG_BIT(1) -#define GEN12_PPGTT_PTE_LM BIT_ULL(11) +#define GEN12_PPGTT_PTE_LM BIT_ULL(11) + +#define GEN12_GGTT_PTE_LM BIT_ULL(1) /* * Cacheability Control is a 4-bit value. The low three bits are stored in bits -- cgit v1.2.3 From 10c5585b5172921c9e4ccbae57637205abd5bda1 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 4 Feb 2021 21:13:02 +0000 Subject: drm/i915/selftests: Restore previous heartbeat interval Use the defaults we store on the engine when resetting the heartbeat as we may have had to adjust it from the config value during initialisation. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210204211303.21347-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index b0bae6676140..b2c369317bf1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -11,6 +11,12 @@ #include "i915_selftest.h" #include "selftest_engine_heartbeat.h" +static void reset_heartbeat(struct intel_engine_cs *engine) +{ + intel_engine_set_heartbeat(engine, + engine->defaults.heartbeat_interval_ms); +} + static int timeline_sync(struct intel_timeline *tl) { struct dma_fence *fence; @@ -269,7 +275,7 @@ static int __live_heartbeat_fast(struct intel_engine_cs *engine) err = -EINVAL; } - intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL); + reset_heartbeat(engine); err_pm: intel_engine_pm_put(engine); intel_context_put(ce); @@ -284,7 +290,7 @@ static int live_heartbeat_fast(void *arg) int err = 0; /* Check that the heartbeat ticks at the desired rate. */ - if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) + if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL)) return 0; for_each_engine(engine, gt, id) { @@ -332,7 +338,7 @@ static int __live_heartbeat_off(struct intel_engine_cs *engine) } err_beat: - intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL); + reset_heartbeat(engine); err_pm: intel_engine_pm_put(engine); return err; @@ -346,7 +352,7 @@ static int live_heartbeat_off(void *arg) int err = 0; /* Check that we can turn off heartbeat and not interrupt VIP */ - if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) + if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL)) return 0; for_each_engine(engine, gt, id) { -- cgit v1.2.3 From 2827ce6e543086deb24a46ddedc5a8a072275670 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 4 Feb 2021 21:13:03 +0000 Subject: drm/i915/gt: Double check heartbeat timeout before resetting Check that we have actually passed the heartbeat interval since last checking the request before resetting the device. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2780 Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20210204211303.21347-2-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index 778bcae5ef2c..dbbae29e4874 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -31,7 +31,7 @@ static bool next_heartbeat(struct intel_engine_cs *engine) delay = msecs_to_jiffies_timeout(delay); if (delay >= HZ) delay = round_jiffies_up_relative(delay); - mod_delayed_work(system_highpri_wq, &engine->heartbeat.work, delay); + mod_delayed_work(system_highpri_wq, &engine->heartbeat.work, delay + 1); return true; } @@ -103,6 +103,13 @@ static void heartbeat(struct work_struct *wrk) goto out; if (engine->heartbeat.systole) { + long delay = READ_ONCE(engine->props.heartbeat_interval_ms); + + /* Safeguard against too-fast worker invocations */ + if (!time_after(jiffies, + rq->emitted_jiffies + msecs_to_jiffies(delay))) + goto out; + if (!i915_sw_fence_signaled(&rq->submit)) { /* * Not yet submitted, system is stalled. @@ -140,6 +147,8 @@ static void heartbeat(struct work_struct *wrk) "stopped heartbeat on %s", engine->name); } + + rq->emitted_jiffies = jiffies; goto out; } -- cgit v1.2.3 From 8ec8ad0f2f8e3e17e6a1f73ca18901097a90e6c4 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 5 Feb 2021 10:20:25 +0000 Subject: drm/i915: cleanup the region class/instance encoding Get rid of the strange REGION_MAP encoding stuff and just use an explicit class/instance pair for each region. This better matches our future uAPI where all queryable regions are identified with a u16 class and u16 instance. v2: fix whitespace Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210205102026.806699-1-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_memory_region.c | 33 +++++++++++++++++++----------- drivers/gpu/drm/i915/intel_memory_region.h | 11 +++------- 2 files changed, 24 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c index 49d306b5532f..048b6d6b5af2 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c @@ -6,14 +6,22 @@ #include "intel_memory_region.h" #include "i915_drv.h" -/* XXX: Hysterical raisins. BIT(inst) needs to just be (inst) at some point. */ -#define REGION_MAP(type, inst) \ - BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst) - -static const u32 intel_region_map[] = { - [INTEL_REGION_SMEM] = REGION_MAP(INTEL_MEMORY_SYSTEM, 0), - [INTEL_REGION_LMEM] = REGION_MAP(INTEL_MEMORY_LOCAL, 0), - [INTEL_REGION_STOLEN] = REGION_MAP(INTEL_MEMORY_STOLEN, 0), +static const struct { + u16 class; + u16 instance; +} intel_region_map[] = { + [INTEL_REGION_SMEM] = { + .class = INTEL_MEMORY_SYSTEM, + .instance = 0, + }, + [INTEL_REGION_LMEM] = { + .class = INTEL_MEMORY_LOCAL, + .instance = 0, + }, + [INTEL_REGION_STOLEN] = { + .class = INTEL_MEMORY_STOLEN, + .instance = 0, + }, }; struct intel_memory_region * @@ -259,12 +267,13 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915) for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) { struct intel_memory_region *mem = ERR_PTR(-ENODEV); - u32 type; + u16 type, instance; if (!HAS_REGION(i915, BIT(i))) continue; - type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]); + type = intel_region_map[i].class; + instance = intel_region_map[i].instance; switch (type) { case INTEL_MEMORY_SYSTEM: mem = i915_gem_shmem_setup(i915); @@ -284,9 +293,9 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915) goto out_cleanup; } - mem->id = intel_region_map[i]; + mem->id = i; mem->type = type; - mem->instance = MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]); + mem->instance = instance; i915->mm.regions[i] = mem; } diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h index d17e4fe3123c..8baf2536d7a5 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.h +++ b/drivers/gpu/drm/i915/intel_memory_region.h @@ -39,11 +39,6 @@ enum intel_region_id { #define REGION_LMEM BIT(INTEL_REGION_LMEM) #define REGION_STOLEN BIT(INTEL_REGION_STOLEN) -#define INTEL_MEMORY_TYPE_SHIFT 16 - -#define MEMORY_TYPE_FROM_REGION(r) (ilog2((r) >> INTEL_MEMORY_TYPE_SHIFT)) -#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2((r) & 0xffff)) - #define I915_ALLOC_MIN_PAGE_SIZE BIT(0) #define I915_ALLOC_CONTIGUOUS BIT(1) @@ -84,9 +79,9 @@ struct intel_memory_region { resource_size_t total; resource_size_t avail; - unsigned int type; - unsigned int instance; - unsigned int id; + u16 type; + u16 instance; + enum intel_region_id id; char name[8]; struct list_head reserved; -- cgit v1.2.3 From dc4304001230557e30cf5eae52b4d7caa6473855 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 5 Feb 2021 10:20:26 +0000 Subject: drm/i915: give stolen system memory its own class In some future patches we will need to also support a stolen region carved from device local memory, on platforms like DG1. To handle this we can simply describe each in terms of its own memory class. Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20210205102026.806699-2-matthew.auld@intel.com Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++-- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_memory_region.c | 6 +++--- drivers/gpu/drm/i915/intel_memory_region.h | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index a1e197a6e999..c5f85296a45f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -686,7 +686,7 @@ struct drm_i915_gem_object * i915_gem_object_create_stolen(struct drm_i915_private *i915, resource_size_t size) { - return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_STOLEN], + return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_STOLEN_SMEM], size, I915_BO_ALLOC_CONTIGUOUS); } @@ -726,7 +726,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915, resource_size_t stolen_offset, resource_size_t size) { - struct intel_memory_region *mem = i915->mm.regions[INTEL_REGION_STOLEN]; + struct intel_memory_region *mem = i915->mm.regions[INTEL_REGION_STOLEN_SMEM]; struct drm_i915_gem_object *obj; struct drm_mm_node *stolen; int ret; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a32d847892e0..2a780ee76697 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -807,7 +807,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 && i915->params.fake_lmem_start) { mkwrite_device_info(i915)->memory_regions = - REGION_SMEM | REGION_LMEM | REGION_STOLEN; + REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM; GEM_BUG_ON(!HAS_LMEM(i915)); } } diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 9a481ad5a8f6..a9f24f2bda33 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -154,7 +154,7 @@ .page_sizes = I915_GTT_PAGE_SIZE_4K #define GEN_DEFAULT_REGIONS \ - .memory_regions = REGION_SMEM | REGION_STOLEN + .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM #define I830_FEATURES \ GEN(2), \ diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c index 048b6d6b5af2..bf837b6bb185 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c @@ -18,8 +18,8 @@ static const struct { .class = INTEL_MEMORY_LOCAL, .instance = 0, }, - [INTEL_REGION_STOLEN] = { - .class = INTEL_MEMORY_STOLEN, + [INTEL_REGION_STOLEN_SMEM] = { + .class = INTEL_MEMORY_STOLEN_SYSTEM, .instance = 0, }, }; @@ -278,7 +278,7 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915) case INTEL_MEMORY_SYSTEM: mem = i915_gem_shmem_setup(i915); break; - case INTEL_MEMORY_STOLEN: + case INTEL_MEMORY_STOLEN_SYSTEM: mem = i915_gem_stolen_setup(i915); break; default: diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h index 8baf2536d7a5..edd49067c8ca 100644 --- a/drivers/gpu/drm/i915/intel_memory_region.h +++ b/drivers/gpu/drm/i915/intel_memory_region.h @@ -25,19 +25,19 @@ struct sg_table; enum intel_memory_type { INTEL_MEMORY_SYSTEM = 0, INTEL_MEMORY_LOCAL, - INTEL_MEMORY_STOLEN, + INTEL_MEMORY_STOLEN_SYSTEM, }; enum intel_region_id { INTEL_REGION_SMEM = 0, INTEL_REGION_LMEM, - INTEL_REGION_STOLEN, + INTEL_REGION_STOLEN_SMEM, INTEL_REGION_UNKNOWN, /* Should be last */ }; #define REGION_SMEM BIT(INTEL_REGION_SMEM) #define REGION_LMEM BIT(INTEL_REGION_LMEM) -#define REGION_STOLEN BIT(INTEL_REGION_STOLEN) +#define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM) #define I915_ALLOC_MIN_PAGE_SIZE BIT(0) #define I915_ALLOC_CONTIGUOUS BIT(1) -- cgit v1.2.3 From 985458d706bd86c16234bfc155535da2a64a9dde Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 5 Feb 2021 11:29:12 +0000 Subject: drm/i915/selftest: Synchronise with the GPU timestamp Wait for the GPU to wake up from the semaphore before measuring the time, so that we coordinate the sampling on both the CPU and GPU for more accurate comparisons. v2: Switch to local_irq_disable() as once suggested by Mika. Reported-by: Bruce Chang Signed-off-by: Chris Wilson Cc: CQ Tang Reviewed-by: Bruce Chang Link: https://patchwork.freedesktop.org/patch/msgid/20210205112912.22978-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 41dc1a542cd6..2c898622bdfb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -110,13 +110,15 @@ static int __measure_timestamps(struct intel_context *ce, cpu_relax(); /* Run the request for a 100us, sampling timestamps before/after */ - preempt_disable(); - *dt = local_clock(); + local_irq_disable(); write_semaphore(&sema[2], 0); + while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ + cpu_relax(); + *dt = local_clock(); udelay(100); *dt = local_clock() - *dt; write_semaphore(&sema[2], 1); - preempt_enable(); + local_irq_enable(); if (i915_request_wait(rq, 0, HZ / 2) < 0) { i915_request_put(rq); -- cgit v1.2.3 From 2da21daa7d93817fa82f703c29adfcb5eed7f77d Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 5 Feb 2021 17:43:57 +0000 Subject: drm/i915/gt: Always flush the submission queue on checking for idle We check for idle during debug prints and other debugging actions. Simplify the flow by not touching execlists state. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin Link: https://patchwork.freedesktop.org/patch/msgid/20210205174358.28465-1-chris@chris-wilson.co.uk Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 0090872964d8..eafe9be88786 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1254,14 +1254,8 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) return true; /* Waiting to drain ELSP? */ - if (execlists_active(&engine->execlists)) { - synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq); - - intel_engine_flush_submission(engine); - - if (execlists_active(&engine->execlists)) - return false; - } + synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq); + intel_engine_flush_submission(engine); /* ELSP is empty, but there are ready requests? E.g. after reset */ if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) -- cgit v1.2.3