From 684f741446f7a3108b4c167faf20214c42b7eeac Mon Sep 17 00:00:00 2001 From: Zhiwu Song Date: Tue, 30 Aug 2011 19:20:34 -0700 Subject: ARM: CSR: add rtc i/o bridge interface for SiRFprimaII The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song Signed-off-by: Barry Song Reviewed-by: Jamie Iles Acked-by: Arnd Bergmann --- include/linux/rtc/sirfsoc_rtciobrg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/linux/rtc/sirfsoc_rtciobrg.h (limited to 'include') diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h new file mode 100644 index 000000000000..2c92e1c8e055 --- /dev/null +++ b/include/linux/rtc/sirfsoc_rtciobrg.h @@ -0,0 +1,18 @@ +/* + * RTC I/O Bridge interfaces for CSR SiRFprimaII + * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ +#ifndef _SIRFSOC_RTC_IOBRG_H_ +#define _SIRFSOC_RTC_IOBRG_H_ + +extern void sirfsoc_rtc_iobrg_besyncing(void); + +extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); + +extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); + +#endif -- cgit v1.2.3