/* * Copyright 2015 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include "priv.h" #include "chan.h" #include "head.h" #include "ior.h" #include static const struct nvkm_ior_func gp100_sor = { .route = { .get = gm200_sor_route_get, .set = gm200_sor_route_set, }, .state = gf119_sor_state, .power = nv50_sor_power, .clock = gf119_sor_clock, .hdmi = { .ctrl = gk104_sor_hdmi_ctrl, .scdc = gm200_sor_hdmi_scdc, }, .dp = { .lanes = { 0, 1, 2, 3 }, .links = gf119_sor_dp_links, .power = g94_sor_dp_power, .pattern = gm107_sor_dp_pattern, .drive = gm200_sor_dp_drive, .vcpi = gf119_sor_dp_vcpi, .audio = gf119_sor_dp_audio, .audio_sym = gf119_sor_dp_audio_sym, .watermark = gf119_sor_dp_watermark, }, .hda = { .hpd = gf119_sor_hda_hpd, .eld = gf119_sor_hda_eld, .device_entry = gf119_sor_hda_device_entry, }, }; int gp100_sor_new(struct nvkm_disp *disp, int id) { struct nvkm_device *device = disp->engine.subdev.device; u32 hda; if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) hda = nvkm_rd32(device, 0x10ebb0) >> 8; return nvkm_ior_new_(&gp100_sor, disp, SOR, id, hda & BIT(id)); } static const struct nvkm_disp_func gp100_disp = { .oneinit = nv50_disp_oneinit, .init = gf119_disp_init, .fini = gf119_disp_fini, .intr = gf119_disp_intr, .intr_error = gf119_disp_intr_error, .super = gf119_disp_super, .uevent = &gf119_disp_chan_uevent, .head = { .cnt = gf119_head_cnt, .new = gf119_head_new }, .sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new }, .root = { 0,0,GP100_DISP }, .user = { {{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new }, {{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new }, {{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new }, {{0,0,GP100_DISP_CORE_CHANNEL_DMA }, gk104_disp_core_new }, {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new }, {} }, }; int gp100_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { return nvkm_disp_new_(&gp100_disp, device, type, inst, pdisp); }