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authorMichal Simek <monstr@monstr.eu>2010-03-22 20:37:23 +0100
committerMichal Simek <monstr@monstr.eu>2010-04-01 08:38:23 +0200
commit7a6bbdc9304b45cc759e03623cbe63d81aff7337 (patch)
tree42361021652ad0217317d5a7ee4e10f49832d839
parent708e7153d6fc4d2e5fe15c6ccc5d2907fe8a9c8d (diff)
microblaze: Prepare work for optimization in exception code
Any sync branch must follow mts instructions not mfs. Signed-off-by: Michal Simek <monstr@monstr.eu>
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S9
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 6651bb437db..ad6dbf029e6 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -562,7 +562,6 @@ ex_handler_done:
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop
/* If we are faulting a kernel address, we have to use the
@@ -679,18 +678,17 @@ ex_handler_done:
*/
handle_data_tlb_miss_exception:
/* Working registers already saved: R3, R4, R5, R6
- * R3 = ESR
+ * R3 = EAR, R4 = ESR
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop
/* If we are faulting a kernel address, we have to use the
* kernel page tables. */
- ori r4, r0, CONFIG_KERNEL_START
- cmpu r4, r3, r4
+ ori r6, r0, CONFIG_KERNEL_START
+ cmpu r4, r3, r6
bgti r4, ex5
ori r4, r0, swapper_pg_dir
mts rpid, r0 /* TLB will have 0 TID */
@@ -756,7 +754,6 @@ ex_handler_done:
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop