kbuild: call make once for all targets when O=.. is used

Change the invocations of make in the output directory Makefile and the
main Makefile for separate object trees to pass all goals to one $(MAKE)
via a new phony target "sub-make" and the existing target _all.

When compiling with separate object directories, a separate make is called
in the context of another directory (from the output directory the main
Makefile is called, the Makefile is then restarted with current directory
set to the object tree).  Before this patch, when multiple make command
goals are specified, each target results in a separate make invocation.
With make -j, these invocations may run in parallel, resulting in multiple
commands running in the same directory clobbering each others results.

I did not try to address make -j for mixed dot-config and no-dot-config
targets.  Because the order does matter, a solution was not obvious.
Perhaps a simple check for MAKEFLAGS having -j and refusing to run would
be appropriate.

Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>

1 files changed, 8 insertions, 3 deletions

diff --git a/Makefile b/Makefile
index 0ad6e8d9b0b..679094a9b2d 100644
--- a/Makefile
+++ b/Makefile
@@ -118,12 +118,17 @@ $(if $(KBUILD_OUTPUT),, \
 # Check that OUTPUT directory is not the same as where we have kernel src
 $(if $(filter-out $(KBUILD_OUTPUT),$(shell /bin/pwd)),, \
      $(error Output directory (O=...) specifies kernel src dir))
-PHONY += $(MAKECMDGOALS)
 
-$(filter-out _all,$(MAKECMDGOALS)) _all:
+PHONY += $(MAKECMDGOALS) sub-make
+
+$(filter-out _all sub-make,$(MAKECMDGOALS)) _all: sub-make
+	$(Q)@:
+
+sub-make: FORCE
 	$(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \
 	KBUILD_SRC=$(CURDIR) \
-	KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile $@
+	KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
+	$(filter-out _all sub-make,$(MAKECMDGOALS))
 
 # Leave processing to above invocation of make
 skip-makefile := 1