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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-08 08:29:31 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-08 08:29:31 -0700
commit6025974bab1c3da8662df79bdeb694588bc3eb93 (patch)
tree27a8fbd7544f7ddcedee541954ab2af04338db4a /arch/arm/include/asm/cache.h
parent33fa108ed1fa46a53a99dd853bdec7c8eaed4732 (diff)
parentaa853f85d9ed593672d0f24a98c72a2518cb63e6 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 5543/1: arm: serial amba: add missing declaration in serial.h [ARM] pxa: fix pxa27x_udc default pullup GPIO [ARM] pxa/imote2: fix UCAM sensor board ADC model number mx[23]: don't put clock lookups in __initdata fix oops when using console=ttymxcN with N > 0 [ARM] ARMv7 errata: only apply fixes when running on applicable CPU [ARM] 5534/1: kmalloc must return a cache line aligned buffer
Diffstat (limited to 'arch/arm/include/asm/cache.h')
-rw-r--r--arch/arm/include/asm/cache.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index cb7a9e97fd7..feaa75f0013 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -7,4 +7,20 @@
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+/*
+ * Memory returned by kmalloc() may be used for DMA, so we must make
+ * sure that all such allocations are cache aligned. Otherwise,
+ * unrelated code may cause parts of the buffer to be read into the
+ * cache before the transfer is done, causing old data to be seen by
+ * the CPU.
+ */
+#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+
+/*
+ * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
+ */
+#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
+#define ARCH_SLAB_MINALIGN 8
+#endif
+
#endif