diff options
author | Benoit Cousson <b-cousson@ti.com> | 2011-01-31 14:50:30 +0000 |
---|---|---|
committer | Benoit Cousson <b-cousson@ti.com> | 2011-02-17 18:25:36 +0100 |
commit | 4ddff4932b31b8f21d1c57155ca5d4088693ce4b (patch) | |
tree | ff391a93f482c96b9b5791840d2187b40a864f47 /arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |
parent | 8ca476da04e452a01d984dd5b5333b3a562207a7 (diff) |
OMAP4: hwmod data: Add McBSP
Add mcbsp data including a revision member in hwmod_class in
order to provide mcbsp revision information in different omap.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
[b-cousson@ti.com: Remove the mcbsp4 memory name, re-order
properly the structures]
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 293 |
1 files changed, 289 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 1488438e4b0..f108614f02f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -530,10 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * iss * kbd * mcasp - * mcbsp1 - * mcbsp2 - * mcbsp3 - * mcbsp4 * mcpdm * mmc1 * mmc2 @@ -2158,6 +2154,289 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = { }; /* + * 'mcbsp' class + * multi channel buffered serial port controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { + .sysc_offs = 0x008c, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { + .name = "mcbsp", + .sysc = &omap44xx_mcbsp_sysc, +}; + +/* mcbsp1 */ +static struct omap_hwmod omap44xx_mcbsp1_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { + { .irq = 17 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { + { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { + { + .pa_start = 0x40122000, + .pa_end = 0x401220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { + { + .pa_start = 0x49022000, + .pa_end = 0x490220ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp1 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp1_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp1_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { + &omap44xx_l4_abe__mcbsp1, + &omap44xx_l4_abe__mcbsp1_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp1_hwmod = { + .name = "mcbsp1", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), + .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), + .main_clk = "mcbsp1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp2 */ +static struct omap_hwmod omap44xx_mcbsp2_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { + { .irq = 22 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { + { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { + { + .pa_start = 0x40124000, + .pa_end = 0x401240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { + { + .pa_start = 0x49024000, + .pa_end = 0x490240ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp2 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp2_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp2_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { + &omap44xx_l4_abe__mcbsp2, + &omap44xx_l4_abe__mcbsp2_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp2_hwmod = { + .name = "mcbsp2", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), + .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), + .main_clk = "mcbsp2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp3 */ +static struct omap_hwmod omap44xx_mcbsp3_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { + { .irq = 23 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { + { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { + { + .pa_start = 0x40126000, + .pa_end = 0x401260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs), + .user = OCP_USER_MPU, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { + { + .pa_start = 0x49026000, + .pa_end = 0x490260ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> mcbsp3 (dma) */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_mcbsp3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_mcbsp3_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* mcbsp3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { + &omap44xx_l4_abe__mcbsp3, + &omap44xx_l4_abe__mcbsp3_dma, +}; + +static struct omap_hwmod omap44xx_mcbsp3_hwmod = { + .name = "mcbsp3", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), + .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), + .main_clk = "mcbsp3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* mcbsp4 */ +static struct omap_hwmod omap44xx_mcbsp4_hwmod; +static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { + { .irq = 16 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { + { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { + { + .pa_start = 0x48096000, + .pa_end = 0x480960ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> mcbsp4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_mcbsp4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_mcbsp4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mcbsp4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { + &omap44xx_l4_per__mcbsp4, +}; + +static struct omap_hwmod omap44xx_mcbsp4_hwmod = { + .name = "mcbsp4", + .class = &omap44xx_mcbsp_hwmod_class, + .mpu_irqs = omap44xx_mcbsp4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), + .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), + .main_clk = "mcbsp4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, + }, + }, + .slaves = omap44xx_mcbsp4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* * 'mcspi' class * multichannel serial port interface (mcspi) / master/slave synchronous serial * bus @@ -3697,6 +3976,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mailbox class */ &omap44xx_mailbox_hwmod, + /* mcbsp class */ + &omap44xx_mcbsp1_hwmod, + &omap44xx_mcbsp2_hwmod, + &omap44xx_mcbsp3_hwmod, + &omap44xx_mcbsp4_hwmod, + /* mcspi class */ &omap44xx_mcspi1_hwmod, &omap44xx_mcspi2_hwmod, |