mach-ux500: Fix PRCMU support on U5500 platforms for 3.0

Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>

2 files changed, 56 insertions, 6 deletions

diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
index 121a5178f67..ec4663046e3 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -17,10 +17,11 @@
 
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
 
+#define PRCM_SVACLK_MGT_OFF		0x008
+#define PRCM_SIACLK_MGT_OFF		0x00C
 #define PRCM_SGACLK_MGT_OFF		0x014
 #define PRCM_UARTCLK_MGT_OFF		0x018
 #define PRCM_MSP02CLK_MGT_OFF		0x01C
-#define PRCM_MSP1CLK_MGT_OFF		0x288
 #define PRCM_I2CCLK_MGT_OFF		0x020
 #define PRCM_SDMMCCLK_MGT_OFF		0x024
 #define PRCM_SLIMCLK_MGT_OFF		0x028
@@ -30,6 +31,9 @@
 #define PRCM_PER5CLK_MGT_OFF		0x038
 #define PRCM_PER6CLK_MGT_OFF		0x03C
 #define PRCM_PER7CLK_MGT_OFF		0x040
+#define PRCM_PWMCLK_MGT_OFF		0x044 /* for DB5500 */
+#define PRCM_IRDACLK_MGT_OFF		0x048 /* for DB5500 */
+#define PRCM_IRRCCLK_MGT_OFF		0x04C /* for DB5500 */
 #define PRCM_LCDCLK_MGT_OFF		0x044
 #define PRCM_BMLCLK_MGT_OFF		0x04C
 #define PRCM_HSITXCLK_MGT_OFF		0x050
@@ -47,6 +51,7 @@
 #define PRCM_SSPCLK_MGT_OFF		0x280
 #define PRCM_RNGCLK_MGT_OFF		0x284
 #define PRCM_UICCCLK_MGT_OFF		0x27C
+#define PRCM_MSP1CLK_MGT_OFF		0x288
 
 #define PRCM_ARM_PLLDIVPS	(_PRCMU_BASE + 0x118)
 #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE		0x3f
@@ -134,7 +139,12 @@
 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 #define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
 #define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
+
 #define PRCM_CLKOCR		   (_PRCMU_BASE + 0x1CC)
+#define PRCM_CLKOCR_CLKOUT0_REF_CLK	(1 << 0)
+#define PRCM_CLKOCR_CLKOUT0_MASK	BITS(0, 13)
+#define PRCM_CLKOCR_CLKOUT1_REF_CLK	(1 << 16)
+#define PRCM_CLKOCR_CLKOUT1_MASK	BITS(16, 29)
 
 /* ePOD and memory power signal control registers */
 #define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
@@ -179,4 +189,8 @@
 #define PRCM_CGATING_BYPASS		(_PRCMU_BASE + 0x134)
 #define PRCM_CGATING_BYPASS_ICN2	BIT(6)
 
+/* Miscellaneous unit registers */
+#define PRCM_RESOUTN_SET		(_PRCMU_BASE + 0x214)
+#define PRCM_RESOUTN_CLR		(_PRCMU_BASE + 0x218)
+
 #endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 71d9dee80ce..41f68f0f087 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -10,6 +10,7 @@
 
 #include <linux/interrupt.h>
 #include <linux/notifier.h>
+#include <asm/mach-types.h>
 
 /* PRCMU Wakeup defines */
 enum prcmu_wakeup_index {
@@ -198,11 +199,33 @@ enum ddr_opp {
 
 void __init prcmu_early_init(void);
 
-int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+		bool keep_ap_pll)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_set_power_state(state, keep_ulp_clk,
+			keep_ap_pll);
+	else
+		return db8500_prcmu_set_power_state(state, keep_ulp_clk,
+			keep_ap_pll);
+}
 
-int prcmu_set_epod(u16 epod_id, u8 epod_state);
+static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_set_epod(epod_id, epod_state);
+	else
+		return db8500_prcmu_set_epod(epod_id, epod_state);
+}
+
+static inline void prcmu_enable_wakeups(u32 wakeups)
+{
+	if (machine_is_u5500())
+		db5500_prcmu_enable_wakeups(wakeups);
+	else
+		db8500_prcmu_enable_wakeups(wakeups);
+}
 
-void prcmu_enable_wakeups(u32 wakeups);
 static inline void prcmu_disable_wakeups(void)
 {
 	prcmu_enable_wakeups(0);
@@ -213,7 +236,13 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 
 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 
-int prcmu_request_clock(u8 clock, bool enable);
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_request_clock(clock, enable);
+	else
+		return db8500_prcmu_request_clock(clock, enable);
+}
 
 int prcmu_set_ape_opp(u8 opp);
 int prcmu_get_ape_opp(void);
@@ -222,7 +251,14 @@ int prcmu_get_arm_opp(void);
 int prcmu_set_ddr_opp(u8 opp);
 int prcmu_get_ddr_opp(void);
 
-void prcmu_system_reset(u16 reset_code);
+static inline void prcmu_system_reset(u16 reset_code)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_system_reset(reset_code);
+	else
+		return db8500_prcmu_system_reset(reset_code);
+}
+
 u16 prcmu_get_reset_code(void);
 
 void prcmu_ac_wake_req(void);