diff options
| author | Rabin Vincent <rabin.vincent@stericsson.com> | 2011-05-16 12:18:51 +0530 |
|---|---|---|
| committer | said m bagheri <ebgheri@steludxu2848.(none)> | 2011-06-17 13:41:48 +0200 |
| commit | c77211bcffadf4c74895956835559f0ec820239f (patch) | |
| tree | 293ba7ad6755fd58f8e6cc8b1757b40db5c2e621 /arch/arm/mach-ux500/pm | |
| parent | b47bc963a0fdf2f197be9a4a7ecbd7a7a4f2a8be (diff) | |
ux500: fix 5500 ICN context
ST-Ericsson Linux next: -
ST-Ericsson ID: WP257121
ST-Ericsson FOSS-OUT ID: Trivial
Change-Id: I366f581e2829979d47b1b555cd11a1dd0d944801
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/23109
Tested-by: Rabin VINCENT <rabin.vincent@stericsson.com>
Reviewed-by: QATEST
Reviewed-by: Rickard ANDERSSON <rickard.andersson@stericsson.com>
Diffstat (limited to 'arch/arm/mach-ux500/pm')
| -rw-r--r-- | arch/arm/mach-ux500/pm/context-db5500.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/arch/arm/mach-ux500/pm/context-db5500.c b/arch/arm/mach-ux500/pm/context-db5500.c index f9a8376620f..78904d3486e 100644 --- a/arch/arm/mach-ux500/pm/context-db5500.c +++ b/arch/arm/mach-ux500/pm/context-db5500.c @@ -50,12 +50,14 @@ #define NODE_HIBW2_DDR_IN_0_PRIORITY 0xC00 #define NODE_HIBW2_DDR_IN_1_PRIORITY 0xC04 #define NODE_HIBW2_DDR_IN_2_PRIORITY 0xC08 +#define NODE_HIBW2_DDR_IN_3_PRIORITY 0xC0C -#define NODE_HIBW2_DDR_IN_0_LIMIT 0xC24 -#define NODE_HIBW2_DDR_IN_1_LIMIT 0xC28 -#define NODE_HIBW2_DDR_IN_2_LIMIT 0xC2C +#define NODE_HIBW2_DDR_IN_0_LIMIT 0xC30 +#define NODE_HIBW2_DDR_IN_1_LIMIT 0xC34 +#define NODE_HIBW2_DDR_IN_2_LIMIT 0xC38 +#define NODE_HIBW2_DDR_IN_3_LIMIT 0xC3C -#define NODE_HIBW2_DDR_OUT_0_PRIORITY 0xC30 +#define NODE_HIBW2_DDR_OUT_0_PRIORITY 0xC40 #define NODE_ESRAM0_IN_0_PRIORITY 0x1000 #define NODE_ESRAM0_IN_1_PRIORITY 0x1004 @@ -103,8 +105,8 @@ static struct { u32 hibw2_esram_in_pri[2]; u32 hibw2_esram_in0_arblimit[3]; u32 hibw2_esram_in1_arblimit[3]; - u32 hibw2_ddr_in_prio[3]; - u32 hibw2_ddr_in_limit[3]; + u32 hibw2_ddr_in_prio[4]; + u32 hibw2_ddr_in_limit[4]; u32 hibw2_ddr_out_prio_reg; /* ESRAM node registers */ @@ -187,6 +189,8 @@ void u5500_context_save_icn(void) readl(context_icn.base + NODE_HIBW2_DDR_IN_1_PRIORITY); context_icn.hibw2_ddr_in_prio[2] = readl(context_icn.base + NODE_HIBW2_DDR_IN_2_PRIORITY); + context_icn.hibw2_ddr_in_prio[3] = + readl(context_icn.base + NODE_HIBW2_DDR_IN_3_PRIORITY); context_icn.hibw2_ddr_in_limit[0] = readl(context_icn.base + NODE_HIBW2_DDR_IN_0_LIMIT); @@ -194,6 +198,8 @@ void u5500_context_save_icn(void) readl(context_icn.base + NODE_HIBW2_DDR_IN_1_LIMIT); context_icn.hibw2_ddr_in_limit[2] = readl(context_icn.base + NODE_HIBW2_DDR_IN_2_LIMIT); + context_icn.hibw2_ddr_in_limit[3] = + readl(context_icn.base + NODE_HIBW2_DDR_IN_3_LIMIT); context_icn.hibw2_ddr_out_prio_reg = readl(context_icn.base + NODE_HIBW2_DDR_OUT_0_PRIORITY); @@ -322,6 +328,8 @@ void u5500_context_restore_icn(void) context_icn.base + NODE_HIBW2_DDR_IN_1_PRIORITY); writel(context_icn.hibw2_ddr_in_prio[2], context_icn.base + NODE_HIBW2_DDR_IN_2_PRIORITY); + writel(context_icn.hibw2_ddr_in_prio[3], + context_icn.base + NODE_HIBW2_DDR_IN_3_PRIORITY); writel(context_icn.hibw2_ddr_in_limit[0], context_icn.base + NODE_HIBW2_DDR_IN_0_LIMIT); @@ -329,6 +337,8 @@ void u5500_context_restore_icn(void) context_icn.base + NODE_HIBW2_DDR_IN_1_LIMIT); writel(context_icn.hibw2_ddr_in_limit[2], context_icn.base + NODE_HIBW2_DDR_IN_2_LIMIT); + writel(context_icn.hibw2_ddr_in_limit[3], + context_icn.base + NODE_HIBW2_DDR_IN_3_LIMIT); writel(context_icn.hibw2_ddr_out_prio_reg, context_icn.base + NODE_HIBW2_DDR_OUT_0_PRIORITY); @@ -391,5 +401,5 @@ void u5500_context_restore_icn(void) void u5500_context_init(void) { - context_icn.base = ioremap(U5500_ICN_BASE, SZ_4K); + context_icn.base = ioremap(U5500_ICN_BASE, SZ_8K); } |