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authorNicolas Pitre <nicolas.pitre@linaro.org>2011-07-21 21:48:13 -0400
committerNicolas Pitre <nicolas.pitre@linaro.org>2011-07-21 21:48:13 -0400
commitf25718e8cff17b5c64ad11c2a6e9d2ee1b676eef (patch)
treee0368d1f4a4b21cfbc1a04f216580ae6b913d1ea /arch/arm/plat-mxc/tzic.c
parentc7e0c8535d73f8c5bf760926a2bd71c9840cf2ef (diff)
Revert "Merge remote-tracking branch 'arm-soc/for-next' into linaro-3.0"
This reverts commit c7e0c8535d73f8c5bf760926a2bd71c9840cf2ef, reversing changes made to dfee09c8acf18e84fe197bb5d821d1e4e02d020f. John Stultz reports that Panda doesn't boot anymore and 'git bisect' indicated the merge commit itself as the culprit. The resulting kernel log is: [ 1.734802] OMAP DSS rev 4.0 [ 1.740417] omap_hwmod: dss_core: _wait_target_disable failed [ 1.746429] omap_device: omapdss_dss.-1: new worst case deactivate latency 01 [ 1.755035] omapdss DISPC error: can't get dss_clk [ 1.760101] omapdss_dispc: probe of omapdss_dispc failed with error -2 [ 1.767333] omapdss HDMI error: can't get hdmi_clk [ 1.772399] omapdss_hdmi: probe of omapdss_hdmi failed with error -2 [ 1.780273] ------------[ cut here ]------------ [ 1.785125] WARNING: at drivers/video/omap2/dss/dispc.c:553dispc_runtime_ge) [ 1.793640] Modules linked in: [ 1.796905] ---[ end trace 6fcb132ac310d004 ]--- [ 1.801757] Unable to handle kernel NULL pointer dereference at virtualaddr0 [...] Revert it so a later version of the arm-soc merge result can be used instead.
Diffstat (limited to 'arch/arm/plat-mxc/tzic.c')
-rw-r--r--arch/arm/plat-mxc/tzic.c99
1 files changed, 72 insertions, 27 deletions
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index f257fccdc39..57f9395f87c 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -49,8 +49,6 @@
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
-#define TZIC_NUM_IRQS 128
-
#ifdef CONFIG_FIQ
static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
{
@@ -68,34 +66,78 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
return 0;
}
-#else
-#define tzic_set_irq_fiq NULL
#endif
-static unsigned int *wakeup_intr[4];
+/**
+ * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
+ *
+ * @param d interrupt source
+ */
+static void tzic_mask_irq(struct irq_data *d)
+{
+ int index, off;
+
+ index = d->irq >> 5;
+ off = d->irq & 0x1F;
+ __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
+}
-static __init void tzic_init_gc(unsigned int irq_start)
+/**
+ * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
+ *
+ * @param d interrupt source
+ */
+static void tzic_unmask_irq(struct irq_data *d)
{
- struct irq_chip_generic *gc;
- struct irq_chip_type *ct;
- int idx = irq_start >> 5;
-
- gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
- handle_level_irq);
- gc->private = tzic_set_irq_fiq;
- gc->wake_enabled = IRQ_MSK(32);
- wakeup_intr[idx] = &gc->wake_active;
-
- ct = gc->chip_types;
- ct->chip.irq_mask = irq_gc_mask_disable_reg;
- ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
- ct->chip.irq_set_wake = irq_gc_set_wake;
- ct->regs.disable = TZIC_ENCLEAR0(idx);
- ct->regs.enable = TZIC_ENSET0(idx);
-
- irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
+ int index, off;
+
+ index = d->irq >> 5;
+ off = d->irq & 0x1F;
+ __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
}
+static unsigned int wakeup_intr[4];
+
+/**
+ * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
+ *
+ * @param d interrupt source
+ * @param enable enable as wake-up if equal to non-zero
+ * disble as wake-up if equal to zero
+ *
+ * @return This function returns 0 on success.
+ */
+static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
+{
+ unsigned int index, off;
+
+ index = d->irq >> 5;
+ off = d->irq & 0x1F;
+
+ if (index > 3)
+ return -EINVAL;
+
+ if (enable)
+ wakeup_intr[index] |= (1 << off);
+ else
+ wakeup_intr[index] &= ~(1 << off);
+
+ return 0;
+}
+
+static struct mxc_irq_chip mxc_tzic_chip = {
+ .base = {
+ .name = "MXC_TZIC",
+ .irq_ack = tzic_mask_irq,
+ .irq_mask = tzic_mask_irq,
+ .irq_unmask = tzic_unmask_irq,
+ .irq_set_wake = tzic_set_wake_irq,
+ },
+#ifdef CONFIG_FIQ
+ .set_irq_fiq = tzic_set_irq_fiq,
+#endif
+};
+
/*
* This function initializes the TZIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
@@ -124,8 +166,11 @@ void __init tzic_init_irq(void __iomem *irqbase)
/* all IRQ no FIQ Warning :: No selection */
- for (i = 0; i < TZIC_NUM_IRQS; i += 32)
- tzic_init_gc(i);
+ for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
+ irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
+ handle_level_irq);
+ set_irq_flags(i, IRQF_VALID);
+ }
#ifdef CONFIG_FIQ
/* Initialize FIQ */
@@ -152,7 +197,7 @@ int tzic_enable_wake(int is_idle)
for (i = 0; i < 4; i++) {
v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
- *wakeup_intr[i];
+ wakeup_intr[i];
__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
}