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authorKukjin Kim <kgene.kim@samsung.com>2011-09-20 08:44:38 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 19:48:41 +0900
commitc0468b0244464a9d85e527fd0bfee91caed697a7 (patch)
tree5f5f33e08ebca698a1956f94bbf609265c35a547 /arch/arm/plat-samsung
parent4b2656fe4957a20edeecc0991616b9b96512839b (diff)
ARM: SAMSUNG: Consolidate plat/pwm-clock.h
Removed - arch/arm/plat-s3c24xx/include/mach/pwm-clock.h - arch/arm/mach-s3c64xx/include/mach/pwm-clock.h - arch/arm/mach-s5p64x0/include/mach/pwm-clock.h - arch/arm/mach-s5pc100/include/mach/pwm-clock.h - arch/arm/mach-s5pv210/include/mach/pwm-clock.h - arch/arm/mach-exynos4/include/mach/pwm-clock.h And created - arch/arm/plat-samsung/include/plat/pwm-clock.h Cc: Ben Dooks <ben-linux@fluff.org> [kgene.kim@samsung.com: changed title] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/include/plat/pwm-clock.h81
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c13
2 files changed, 92 insertions, 2 deletions
diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
new file mode 100644
index 00000000000..bf6a60eb623
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h
@@ -0,0 +1,81 @@
+/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * SAMSUNG - pwm clock and timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_PWM_CLOCK_H
+#define __ASM_PLAT_PWM_CLOCK_H __FILE__
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+ if (soc_is_s3c24xx())
+ return tcfg == S3C2410_TCFG1_MUX_TCLK;
+ else if (soc_is_s3c64xx() || soc_is_s5pc100())
+ return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+ else if (soc_is_s5p6440() || soc_is_s5p6450())
+ return 0;
+ else
+ return tcfg == S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+ if (soc_is_s3c24xx())
+ return 1 << (tcfg1 + 1);
+ else
+ return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+ if (soc_is_s3c24xx())
+ return 0;
+ else
+ return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+ if (soc_is_s3c24xx())
+ return ilog2(div) - 1;
+ else
+ return ilog2(div);
+}
+#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index f1bba88ed2f..a35ff3bcffe 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -27,7 +27,7 @@
#include <plat/cpu.h>
#include <plat/regs-timer.h>
-#include <mach/pwm-clock.h>
+#include <plat/pwm-clock.h>
/* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers.
@@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
unsigned long bits;
unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+ unsigned long mux_tclk;
+
+ if (soc_is_s3c24xx())
+ mux_tclk = S3C2410_TCFG1_MUX_TCLK;
+ else if (soc_is_s5p6440() || soc_is_s5p6450())
+ mux_tclk = 0;
+ else
+ mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
+
if (parent == s3c24xx_pwmclk_tclk(id))
- bits = S3C_TCFG1_MUX_TCLK << shift;
+ bits = mux_tclk << shift;
else if (parent == s3c24xx_pwmclk_tdiv(id))
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
else