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authorHeiko Stuebner <heiko@sntech.de>2011-12-24 10:52:19 +0900
committerKukjin Kim <kgene.kim@samsung.com>2012-02-07 08:03:42 +0900
commit25c1a2466008a75955e80df3cc0698410a0cec72 (patch)
treefe01954187996f69f99e6beb4a5817dd60415b90 /arch/arm/plat-samsung
parentd2524caac3e14af0b95bb428084e0ef355514c2f (diff)
rtc-s3c: add variants for S3C2443 and S3C2416
Especially the TICNT registers are different from the two rtc types that currently exists. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-rtc.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
index a7d944f4131..0f8263e93ee 100644
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -22,11 +22,28 @@
#define S3C2410_RTCCON_RTCEN (1 << 0)
#define S3C2410_RTCCON_CNTSEL (1 << 2)
#define S3C2410_RTCCON_CLKRST (1 << 3)
+#define S3C2443_RTCCON_TICSEL (1 << 4)
#define S3C64XX_RTCCON_TICEN (1 << 8)
#define S3C2410_TICNT S3C2410_RTCREG(0x44)
#define S3C2410_TICNT_ENABLE (1 << 7)
+/* S3C2443: tick count is 15 bit wide
+ * TICNT[6:0] contains upper 7 bits
+ * TICNT1[7:0] contains lower 8 bits
+ */
+#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8)
+#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C)
+#define S3C2443_TICNT1_PART(x) (x & 0xff)
+
+/* S3C2416: tick count is 32 bit wide
+ * TICNT[6:0] contains bits [14:8]
+ * TICNT1[7:0] contains lower 8 bits
+ * TICNT2[16:0] contains upper 17 bits
+ */
+#define S3C2416_TICNT2 S3C2410_RTCREG(0x48)
+#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15)
+
#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
#define S3C2410_RTCALM_ALMEN (1 << 6)
#define S3C2410_RTCALM_YEAREN (1 << 5)