diff options
| author | Guo-Fu Tseng <cooldavid@cooldavid.org> | 2008-10-08 19:48:58 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-10-08 19:51:31 -0700 |
| commit | a821ebe580c535e3e8e354c6ab10516a0e95e202 (patch) | |
| tree | b47d39b17146c16b358f8e01e1dc7709564b4ee8 /drivers/net/jme.h | |
| parent | 0ce2f03bade2046d6eb6184d52d065688382d7bd (diff) | |
jme: Added half-duplex mode and IPv6 RSS fix
1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
mode. Which the MAC processor generates CRS/COL by itself instead of
receive it from PHY processor.
2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
MAC processor working right while calculating IPv6 RSS in 10/100
mode.
3. Group the workaround codes all together.
Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/jme.h')
| -rw-r--r-- | drivers/net/jme.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/net/jme.h b/drivers/net/jme.h index b29688431a6..9fdf20a9a82 100644 --- a/drivers/net/jme.h +++ b/drivers/net/jme.h @@ -964,6 +964,36 @@ enum jme_gpreg0_vals { }; /* + * General Purpose REG-1 + * Note: All theses bits defined here are for + * Chip mode revision 0x11 only + */ +enum jme_gpreg1_masks { + GPREG1_INTRDELAYUNIT = 0x00000018, + GPREG1_INTRDELAYENABLE = 0x00000007, +}; + +enum jme_gpreg1_vals { + GPREG1_RSSPATCH = 0x00000040, + GPREG1_HALFMODEPATCH = 0x00000020, + + GPREG1_INTDLYUNIT_16NS = 0x00000000, + GPREG1_INTDLYUNIT_256NS = 0x00000008, + GPREG1_INTDLYUNIT_1US = 0x00000010, + GPREG1_INTDLYUNIT_16US = 0x00000018, + + GPREG1_INTDLYEN_1U = 0x00000001, + GPREG1_INTDLYEN_2U = 0x00000002, + GPREG1_INTDLYEN_3U = 0x00000003, + GPREG1_INTDLYEN_4U = 0x00000004, + GPREG1_INTDLYEN_5U = 0x00000005, + GPREG1_INTDLYEN_6U = 0x00000006, + GPREG1_INTDLYEN_7U = 0x00000007, + + GPREG1_DEFAULT = 0x00000000, +}; + +/* * Interrupt Status Bits */ enum jme_interrupt_bits { |