diff options
| author | Arend van Spriel <arend@broadcom.com> | 2011-08-15 15:34:25 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-08-23 13:08:06 -0700 |
| commit | 3bd8ef6799524fd48044a83aab38da57d9a98dbc (patch) | |
| tree | 53e1fe659080106e4e3b6ca15c297a6cf3febcbb /drivers/staging/brcm80211 | |
| parent | a87602e075126c9a7acad7ba999a40837f966e54 (diff) | |
staging: brcm80211: restrict register access method for bcm47xx
The driver contained conditional code for resolving issue with
dma transaction reordering. This code was conditionalized using
__mips__ macro, but it actually is specific to bcm47xx chips.
This patch replaces it for the more speficic CONFIG_BCM47XX macro.
Tested on BCM63281.
Reviewed-by: Henry Ptasinski <henryp@broadcom.com>
Reviewed-by: Roland Vossen <rvossen@broadcom.com>
Tested-by: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/brcm80211')
| -rw-r--r-- | drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c | 2 | ||||
| -rw-r--r-- | drivers/staging/brcm80211/brcmsmac/types.h | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c index c00178d18b5..448afae0d69 100644 --- a/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c +++ b/drivers/staging/brcm80211/brcmsmac/phy/phy_cmn.c @@ -380,7 +380,7 @@ void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val) regs = pi->regs; -#ifdef __mips__ +#ifdef CONFIG_BCM47XX W_REG_FLUSH(®s->phyregaddr, addr); W_REG(®s->phyregdata, val); if (addr == 0x72) diff --git a/drivers/staging/brcm80211/brcmsmac/types.h b/drivers/staging/brcm80211/brcmsmac/types.h index ad874a79cb4..d44db5674b3 100644 --- a/drivers/staging/brcm80211/brcmsmac/types.h +++ b/drivers/staging/brcm80211/brcmsmac/types.h @@ -362,7 +362,7 @@ do { \ } \ } while (0) -#ifdef __mips__ +#ifdef CONFIG_BCM47XX /* * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder * transactions. As a fix, a read after write is performed on certain places @@ -371,7 +371,7 @@ do { \ #define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); }) #else #define W_REG_FLUSH(r, v) W_REG((r), (v)) -#endif /* __mips__ */ +#endif /* CONFIG_BCM47XX */ #define AND_REG(r, v) W_REG((r), R_REG(r) & (v)) #define OR_REG(r, v) W_REG((r), R_REG(r) | (v)) |