diff options
| author | Sujith <Sujith.Manoharan@atheros.com> | 2009-02-16 13:23:12 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2009-02-27 14:52:37 -0500 |
| commit | 70768496db9ee27d53d3d03d50c93fbf4c0198a0 (patch) | |
| tree | 3ab32b158d56c420029a80d288ec739251f9b665 /drivers | |
| parent | 362695e11a09ff016ef00dc45b934b1daf862091 (diff) | |
ath9k: Program the RTC registers correctly
This patch programs the RTC registers of AR9100 chipsets
correctly during chip reset.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/ath9k/hw.c | 8 | ||||
| -rw-r--r-- | drivers/net/wireless/ath9k/reg.h | 8 |
2 files changed, 14 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index e33c53fb6b7..1c02358b31f 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -1482,6 +1482,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) u32 rst_flags; u32 tmpReg; + if (AR_SREV_9100(ah)) { + u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); + val &= ~AR_RTC_DERIVED_CLK_PERIOD; + val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); + REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); + (void)REG_READ(ah, AR_RTC_DERIVED_CLK); + } + REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index a471832308a..8d85106d6df 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h @@ -977,8 +977,6 @@ enum { #define AR_RTC_PLL_CLKSEL 0x00000300 #define AR_RTC_PLL_CLKSEL_S 8 - - #define AR_RTC_RESET \ ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) #define AR_RTC_RESET_EN (0x00000001) @@ -1015,6 +1013,12 @@ enum { #define AR_RTC_INTR_MASK \ ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) +/* RTC_DERIVED_* - only for AR9100 */ + +#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) +#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe +#define AR_RTC_DERIVED_CLK_PERIOD_S 1 + #define AR_SEQ_MASK 0x8060 #define AR_AN_RF2G1_CH0 0x7810 |