diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-11-08 18:02:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-11-15 23:21:49 +0000 |
| commit | f6771dbb27c704ce837ba3bb1dcaa53f48f76ea8 (patch) | |
| tree | efec5eacc34a9e412a193a79d575cbf3b90acf23 /include/asm-mips | |
| parent | efb9ca08b5a2374b29938cdcab417ce4feb14b54 (diff) | |
[MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore
systems. The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code. So fix
the allocator by ditching it. Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 94f1c817236..ed5c02c6afb 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -54,6 +54,7 @@ struct cpuinfo_mips { struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ + int srsets; /* Shadow register sets */ #if defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered |