diff options
| author | Mathieu Desnoyers <mathieu.desnoyers@efficios.com> | 2011-03-16 19:05:24 -0400 |
|---|---|---|
| committer | Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> | 2011-03-16 19:05:24 -0400 |
| commit | d43022c0918efc848aabef46e3c05454e2083fa7 (patch) | |
| tree | f14644615c767be432b500c209085f93594a435e /kernel | |
| parent | 3ba7a0e993e15778c45bf8ea9341eac65d41ae4b (diff) | |
trace-clock-32-to-64-add-compiler-barrier
trace clock 32 to 64 - add compiler barrier
Update-side need a compiler barrier to ensure interrupts never see the index
updated before the value.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/trace/trace-clock-32-to-64.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/trace/trace-clock-32-to-64.c b/kernel/trace/trace-clock-32-to-64.c index 701aeb1bcbb..6249d5ec03c 100644 --- a/kernel/trace/trace-clock-32-to-64.c +++ b/kernel/trace/trace-clock-32-to-64.c @@ -79,6 +79,12 @@ static void update_synthetic_tsc(void) cpu_synth->tsc[new_index].val = (SW_MS32(cpu_synth->tsc[cpu_synth->index].val) | (u64)tsc) + (1ULL << TC_HW_BITS); + /* + * Ensure the compiler does not reorder index write. It makes + * sure all nested interrupts will see the new value before the + * new index is written. + */ + barrier(); cpu_synth->index = new_index; /* atomic change of index */ } else { /* |