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-rw-r--r--drivers/net/dl2k.c40
-rw-r--r--drivers/net/dl2k.h40
2 files changed, 22 insertions, 58 deletions
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c
index 4468e0f5d16..2e13eaad170 100644
--- a/drivers/net/dl2k.c
+++ b/drivers/net/dl2k.c
@@ -1455,8 +1455,8 @@ mii_get_media (struct net_device *dev)
{
__u16 negotiate;
__u16 bmsr;
- MSCR_t mscr;
- MSSR_t mssr;
+ __u16 mscr;
+ __u16 mssr;
int phy_addr;
struct netdev_private *np;
@@ -1471,13 +1471,13 @@ mii_get_media (struct net_device *dev)
}
negotiate = mii_read (dev, phy_addr, MII_ANAR) &
mii_read (dev, phy_addr, MII_ANLPAR);
- mscr.image = mii_read (dev, phy_addr, MII_MSCR);
- mssr.image = mii_read (dev, phy_addr, MII_MSSR);
- if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
+ mscr = mii_read (dev, phy_addr, MII_MSCR);
+ mssr = mii_read (dev, phy_addr, MII_MSSR);
+ if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
np->speed = 1000;
np->full_duplex = 1;
printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
- } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
+ } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
np->speed = 1000;
np->full_duplex = 0;
printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
@@ -1539,7 +1539,7 @@ mii_get_media (struct net_device *dev)
static int
mii_set_media (struct net_device *dev)
{
- PHY_SCR_t pscr;
+ __u16 pscr;
__u16 bmcr;
__u16 bmsr;
__u16 anar;
@@ -1572,9 +1572,9 @@ mii_set_media (struct net_device *dev)
mii_write (dev, phy_addr, MII_ANAR, anar);
/* Enable Auto crossover */
- pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
- pscr.bits.mdi_crossover_mode = 3; /* 11'b */
- mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
+ pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
+ pscr |= 3 << 5; /* 11'b */
+ mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
/* Soft reset PHY */
mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
@@ -1584,9 +1584,9 @@ mii_set_media (struct net_device *dev)
} else {
/* Force speed setting */
/* 1) Disable Auto crossover */
- pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
- pscr.bits.mdi_crossover_mode = 0;
- mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
+ pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
+ pscr &= ~(3 << 5);
+ mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
/* 2) PHY Reset */
bmcr = mii_read (dev, phy_addr, MII_BMCR);
@@ -1617,9 +1617,9 @@ mii_set_media (struct net_device *dev)
}
#if 0
/* Set 1000BaseT Master/Slave setting */
- mscr.image = mii_read (dev, phy_addr, MII_MSCR);
- mscr.bits.cfg_enable = 1;
- mscr.bits.cfg_value = 0;
+ mscr = mii_read (dev, phy_addr, MII_MSCR);
+ mscr |= MII_MSCR_CFG_ENABLE;
+ mscr &= ~MII_MSCR_CFG_VALUE = 0;
#endif
mii_write (dev, phy_addr, MII_BMCR, bmcr);
mdelay(10);
@@ -1687,7 +1687,7 @@ static int
mii_set_media_pcs (struct net_device *dev)
{
__u16 bmcr;
- ESR_t esr;
+ __u16 esr;
__u16 anar;
int phy_addr;
struct netdev_private *np;
@@ -1697,13 +1697,13 @@ mii_set_media_pcs (struct net_device *dev)
/* Auto-Negotiation? */
if (np->an_enable) {
/* Advertise capabilities */
- esr.image = mii_read (dev, phy_addr, PCS_ESR);
+ esr = mii_read (dev, phy_addr, PCS_ESR);
anar = mii_read (dev, phy_addr, MII_ANAR) &
~PCS_ANAR_HALF_DUPLEX &
~PCS_ANAR_FULL_DUPLEX;
- if (esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD)
+ if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
anar |= PCS_ANAR_HALF_DUPLEX;
- if (esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD)
+ if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
anar |= PCS_ANAR_FULL_DUPLEX;
anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
mii_write (dev, phy_addr, MII_ANAR, anar);
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h
index c8aacf2ff8d..5f00ecb4a28 100644
--- a/drivers/net/dl2k.h
+++ b/drivers/net/dl2k.h
@@ -385,19 +385,6 @@ enum _mii_aner {
};
/* MASTER-SLAVE Control Register */
-typedef union t_MII_MSCR {
- u16 image;
- struct {
- u16 _bit_7_0:8; // bit 7:0
- u16 media_1000BT_HD:1; // bit 8
- u16 media_1000BT_FD:1; // bit 9
- u16 port_type:1; // bit 10
- u16 cfg_value:1; // bit 11
- u16 cfg_enable:1; // bit 12
- u16 test_mode:3; // bit 15:13
- } bits;
-} MSCR_t, *PMSCR_t;
-
enum _mii_mscr {
MII_MSCR_TEST_MODE = 0xe000,
MII_MSCR_CFG_ENABLE = 0x1000,
@@ -408,20 +395,6 @@ enum _mii_mscr {
};
/* MASTER-SLAVE Status Register */
-typedef union t_MII_MSSR {
- u16 image;
- struct {
- u16 idle_err_count:8; // bit 7:0
- u16 _bit_9_8:2; // bit 9:8
- u16 lp_1000BT_HD:1; // bit 10
- u16 lp_1000BT_FD:1; // bit 11
- u16 remote_rcv_status:1; // bit 12
- u16 local_rcv_status:1; // bit 13
- u16 cfg_resolution:1; // bit 14
- u16 cfg_fault:1; // bit 15
- } bits;
-} MSSR_t, *PMSSR_t;
-
enum _mii_mssr {
MII_MSSR_CFG_FAULT = 0x8000,
MII_MSSR_CFG_RES = 0x4000,
@@ -433,17 +406,6 @@ enum _mii_mssr {
};
/* IEEE Extened Status Register */
-typedef union t_MII_ESR {
- u16 image;
- struct {
- u16 _bit_11_0:12; // bit 11:0
- u16 media_1000BT_HD:2; // bit 12
- u16 media_1000BT_FD:1; // bit 13
- u16 media_1000BX_HD:1; // bit 14
- u16 media_1000BX_FD:1; // bit 15
- } bits;
-} ESR_t, *PESR_t;
-
enum _mii_esr {
MII_ESR_1000BX_FD = 0x8000,
MII_ESR_1000BX_HD = 0x4000,
@@ -451,6 +413,7 @@ enum _mii_esr {
MII_ESR_1000BT_HD = 0x1000,
};
/* PHY Specific Control Register */
+#if 0
typedef union t_MII_PHY_SCR {
u16 image;
struct {
@@ -468,6 +431,7 @@ typedef union t_MII_PHY_SCR {
u16 xmit_fifo_depth:2; // bit 15:14
} bits;
} PHY_SCR_t, *PPHY_SCR_t;
+#endif
typedef enum t_MII_ADMIN_STATUS {
adm_reset,
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-12 09:33:42 +0000