diff options
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r-- | arch/arm/mach-zynq/Makefile | 6 | ||||
-rw-r--r-- | arch/arm/mach-zynq/Makefile.boot | 3 | ||||
-rw-r--r-- | arch/arm/mach-zynq/board_dt.c | 0 | ||||
-rw-r--r-- | arch/arm/mach-zynq/common.c | 118 | ||||
-rw-r--r-- | arch/arm/mach-zynq/common.h | 24 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/clkdev.h | 32 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/debug-macro.S | 36 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/entry-macro.S | 30 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/hardware.h | 18 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/io.h | 33 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/irqs.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/memory.h | 22 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/system.h | 28 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/timex.h | 23 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/uart.h | 25 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/uncompress.h | 51 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/vmalloc.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-zynq/include/mach/zynq_soc.h | 48 | ||||
-rw-r--r-- | arch/arm/mach-zynq/timer.c | 298 |
19 files changed, 0 insertions, 836 deletions
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile deleted file mode 100644 index c550c67aa89..00000000000 --- a/arch/arm/mach-zynq/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Common support -obj-y := common.o timer.o board_dt.o diff --git a/arch/arm/mach-zynq/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot deleted file mode 100644 index 67039c3e0c4..00000000000 --- a/arch/arm/mach-zynq/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-zynq/board_dt.c b/arch/arm/mach-zynq/board_dt.c deleted file mode 100644 index e69de29bb2d..00000000000 --- a/arch/arm/mach-zynq/board_dt.c +++ /dev/null diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c deleted file mode 100644 index 73e93687b81..00000000000 --- a/arch/arm/mach-zynq/common.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file contains common code that is intended to be used across - * boards so that it's not replicated. - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/cpumask.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <linux/of.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach-types.h> -#include <asm/page.h> -#include <asm/hardware/gic.h> -#include <asm/hardware/cache-l2x0.h> - -#include <mach/zynq_soc.h> -#include <mach/clkdev.h> -#include "common.h" - -static struct of_device_id zynq_of_bus_ids[] __initdata = { - { .compatible = "simple-bus", }, - {} -}; - -/** - * xilinx_init_machine() - System specific initialization, intended to be - * called from board specific initialization. - */ -static void __init xilinx_init_machine(void) -{ -#ifdef CONFIG_CACHE_L2X0 - /* - * 64KB way size, 8-way associativity, parity disabled - */ - l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF); -#endif - - of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); -} - -/** - * xilinx_irq_init() - Interrupt controller initialization for the GIC. - */ -static void __init xilinx_irq_init(void) -{ - gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); -} - -/* The minimum devices needed to be mapped before the VM system is up and - * running include the GIC, UART and Timer Counter. - */ - -static struct map_desc io_desc[] __initdata = { - { - .virtual = TTC0_VIRT, - .pfn = __phys_to_pfn(TTC0_PHYS), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = SCU_PERIPH_VIRT, - .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = PL310_L2CC_VIRT, - .pfn = __phys_to_pfn(PL310_L2CC_PHYS), - .length = SZ_4K, - .type = MT_DEVICE, - }, - -#ifdef CONFIG_DEBUG_LL - { - .virtual = UART0_VIRT, - .pfn = __phys_to_pfn(UART0_PHYS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -#endif - -}; - -/** - * xilinx_map_io() - Create memory mappings needed for early I/O. - */ -static void __init xilinx_map_io(void) -{ - iotable_init(io_desc, ARRAY_SIZE(io_desc)); -} - -static const char *xilinx_dt_match[] = { - "xlnx,zynq-ep107", - NULL -}; - -MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") - .map_io = xilinx_map_io, - .init_irq = xilinx_irq_init, - .init_machine = xilinx_init_machine, - .timer = &xttcpss_sys_timer, - .dt_compat = xilinx_dt_match, -MACHINE_END diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h deleted file mode 100644 index a009644a155..00000000000 --- a/arch/arm/mach-zynq/common.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file contains common function prototypes to avoid externs - * in the c files. - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_ZYNQ_COMMON_H__ -#define __MACH_ZYNQ_COMMON_H__ - -#include <asm/mach/time.h> - -extern struct sys_timer xttcpss_sys_timer; - -#endif diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h deleted file mode 100644 index c6e73d81a45..00000000000 --- a/arch/arm/mach-zynq/include/mach/clkdev.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-zynq/include/mach/clkdev.h - * - * Copyright (C) 2011 Xilinx, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#include <plat/clock.h> - -struct clk { - unsigned long rate; - const struct clk_ops *ops; - const struct icst_params *params; - void __iomem *vcoreg; -}; - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/mach-zynq/include/mach/debug-macro.S deleted file mode 100644 index 9f664d5eb81..00000000000 --- a/arch/arm/mach-zynq/include/mach/debug-macro.S +++ /dev/null @@ -1,36 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mach/zynq_soc.h> -#include <mach/uart.h> - - .macro addruart, rp, rv - ldr \rp, =LL_UART_PADDR @ physical - ldr \rv, =LL_UART_VADDR @ virtual - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register - tst \rd, #UART_SR_TXFULL @ - bne 1002b @ wait if FIFO is full - .endm diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S deleted file mode 100644 index 3cfc01b3746..00000000000 --- a/arch/arm/mach-zynq/include/mach/entry-macro.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * arch/arm/mach-zynq/include/mach/entry-macro.S - * - * Low-level IRQ helper macros - * - * Copyright (C) 2011 Xilinx - * - * based on arch/plat-mxc/include/mach/entry-macro.S - * - * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mach/hardware.h> -#include <asm/hardware/entry-macro-gic.S> - - .macro disable_fiq - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h deleted file mode 100644 index d558d8a94be..00000000000 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ /dev/null @@ -1,18 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/hardware.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_HARDWARE_H__ -#define __MACH_HARDWARE_H__ - -#endif diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h deleted file mode 100644 index 39d9885e0e9..00000000000 --- a/arch/arm/mach-zynq/include/mach/io.h +++ /dev/null @@ -1,33 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/io.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_IO_H__ -#define __MACH_IO_H__ - -/* Allow IO space to be anywhere in the memory */ - -#define IO_SPACE_LIMIT 0xffff - -/* IO address mapping macros, nothing special at this time but required */ - -#ifdef __ASSEMBLER__ -#define IOMEM(x) (x) -#else -#define IOMEM(x) ((void __force __iomem *)(x)) -#endif - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/arch/arm/mach-zynq/include/mach/irqs.h b/arch/arm/mach-zynq/include/mach/irqs.h deleted file mode 100644 index 5fb04fd3bac..00000000000 --- a/arch/arm/mach-zynq/include/mach/irqs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/irqs.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define ARCH_NR_GPIOS 118 -#define NR_IRQS (128 + ARCH_NR_GPIOS) - -#endif diff --git a/arch/arm/mach-zynq/include/mach/memory.h b/arch/arm/mach-zynq/include/mach/memory.h deleted file mode 100644 index 35a92634dcc..00000000000 --- a/arch/arm/mach-zynq/include/mach/memory.h +++ /dev/null @@ -1,22 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/memory.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_MEMORY_H__ -#define __MACH_MEMORY_H__ - -#include <asm/sizes.h> - -#define PLAT_PHYS_OFFSET UL(0x0) - -#endif diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h deleted file mode 100644 index 1b84d705c67..00000000000 --- a/arch/arm/mach-zynq/include/mach/system.h +++ /dev/null @@ -1,28 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/system.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_SYSTEM_H__ -#define __MACH_SYSTEM_H__ - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - /* Add architecture specific reset processing here */ -} - -#endif diff --git a/arch/arm/mach-zynq/include/mach/timex.h b/arch/arm/mach-zynq/include/mach/timex.h deleted file mode 100644 index 6c0245e42a5..00000000000 --- a/arch/arm/mach-zynq/include/mach/timex.h +++ /dev/null @@ -1,23 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/timex.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_TIMEX_H__ -#define __MACH_TIMEX_H__ - -/* the following is needed for the system to build but will be removed - in the future, the value is not important but won't hurt -*/ -#define CLOCK_TICK_RATE (100 * HZ) - -#endif diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h deleted file mode 100644 index 5c47c97156f..00000000000 --- a/arch/arm/mach-zynq/include/mach/uart.h +++ /dev/null @@ -1,25 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/uart.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_UART_H__ -#define __MACH_UART_H__ - -#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ -#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ -#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ - -#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ -#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ - -#endif diff --git a/arch/arm/mach-zynq/include/mach/uncompress.h b/arch/arm/mach-zynq/include/mach/uncompress.h deleted file mode 100644 index af4e8447bfa..00000000000 --- a/arch/arm/mach-zynq/include/mach/uncompress.h +++ /dev/null @@ -1,51 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/uncompress.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_UNCOMPRESS_H__ -#define __MACH_UNCOMPRESS_H__ - -#include <linux/io.h> -#include <asm/processor.h> -#include <mach/zynq_soc.h> -#include <mach/uart.h> - -void arch_decomp_setup(void) -{ -} - -static inline void flush(void) -{ - /* - * Wait while the FIFO is not empty - */ - while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & - UART_SR_TXEMPTY)) - cpu_relax(); -} - -#define arch_decomp_wdog() - -static void putc(char ch) -{ - /* - * Wait for room in the FIFO, then write the char into the FIFO - */ - while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) & - UART_SR_TXFULL) - cpu_relax(); - - __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET)); -} - -#endif diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h deleted file mode 100644 index 2398eff1e8b..00000000000 --- a/arch/arm/mach-zynq/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/vmalloc.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_VMALLOC_H__ -#define __MACH_VMALLOC_H__ - -#define VMALLOC_END 0xE0000000UL - -#endif diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h deleted file mode 100644 index d0d3f8fb06d..00000000000 --- a/arch/arm/mach-zynq/include/mach/zynq_soc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* arch/arm/mach-zynq/include/mach/zynq_soc.h - * - * Copyright (C) 2011 Xilinx - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_XILINX_SOC_H__ -#define __MACH_XILINX_SOC_H__ - -#define PERIPHERAL_CLOCK_RATE 2500000 - -/* For now, all mappings are flat (physical = virtual) - */ -#define UART0_PHYS 0xE0000000 -#define UART0_VIRT UART0_PHYS - -#define TTC0_PHYS 0xF8001000 -#define TTC0_VIRT TTC0_PHYS - -#define PL310_L2CC_PHYS 0xF8F02000 -#define PL310_L2CC_VIRT PL310_L2CC_PHYS - -#define SCU_PERIPH_PHYS 0xF8F00000 -#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS - -/* The following are intended for the devices that are mapped early */ - -#define TTC0_BASE IOMEM(TTC0_VIRT) -#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) -#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100) -#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000) -#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT) - -/* - * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical - */ -#define LL_UART_PADDR UART0_PHYS -#define LL_UART_VADDR UART0_VIRT - -#endif diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c deleted file mode 100644 index c2c96cc7d6e..00000000000 --- a/arch/arm/mach-zynq/timer.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * This file contains driver for the Xilinx PS Timer Counter IP. - * - * Copyright (C) 2011 Xilinx - * - * based on arch/mips/kernel/time.c timer driver - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/types.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/io.h> - -#include <asm/mach/time.h> -#include <mach/zynq_soc.h> -#include "common.h" - -#define IRQ_TIMERCOUNTER0 42 - -/* - * This driver configures the 2 16-bit count-up timers as follows: - * - * T1: Timer 1, clocksource for generic timekeeping - * T2: Timer 2, clockevent source for hrtimers - * T3: Timer 3, <unused> - * - * The input frequency to the timer module for emulation is 2.5MHz which is - * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, - * the timers are clocked at 78.125KHz (12.8 us resolution). - * - * The input frequency to the timer module in silicon will be 200MHz. With the - * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution). - */ -#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */ -#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */ - -#define XTTCPSS_TIMER_BASE TTC0_BASE -#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1) -/* - * Timer Register Offset Definitions of Timer 1, Increment base address by 4 - * and use same offsets for Timer 2 - */ -#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ -#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ -#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */ -#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */ -#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */ -#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ -#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ - -#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1 - -/* Setup the timers to use pre-scaling */ - -#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32) - -/** - * struct xttcpss_timer - This definition defines local timer structure - * - * @base_addr: Base address of timer - **/ -struct xttcpss_timer { - void __iomem *base_addr; -}; - -static struct xttcpss_timer timers[2]; -static struct clock_event_device xttcpss_clockevent; - -/** - * xttcpss_set_interval - Set the timer interval value - * - * @timer: Pointer to the timer instance - * @cycles: Timer interval ticks - **/ -static void xttcpss_set_interval(struct xttcpss_timer *timer, - unsigned long cycles) -{ - u32 ctrl_reg; - - /* Disable the counter, set the counter value and re-enable counter */ - ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); - - __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET); - - /* Reset the counter (0x10) so that it starts from 0, one-shot - mode makes this needed for timing to be right. */ - ctrl_reg |= 0x10; - ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); -} - -/** - * xttcpss_clock_event_interrupt - Clock event timer interrupt handler - * - * @irq: IRQ number of the Timer - * @dev_id: void pointer to the xttcpss_timer instance - * - * returns: Always IRQ_HANDLED - success - **/ -static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &xttcpss_clockevent; - struct xttcpss_timer *timer = dev_id; - - /* Acknowledge the interrupt and call event handler */ - __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET), - timer->base_addr + XTTCPSS_ISR_OFFSET); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction event_timer_irq = { - .name = "xttcpss clockevent", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = xttcpss_clock_event_interrupt, -}; - -/** - * xttcpss_timer_hardware_init - Initialize the timer hardware - * - * Initialize the hardware to start the clock source, get the clock - * event timer ready to use, and hook up the interrupt. - **/ -static void __init xttcpss_timer_hardware_init(void) -{ - /* Setup the clock source counter to be an incrementing counter - * with no interrupt and it rolls over at 0xFFFF. Pre-scale - it by 32 also. Let it start running now. - */ - timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE; - - __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_IER_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - - /* Setup the clock event timer to be an interval timer which - * is prescaled by 32 using the interval interrupt. Leave it - * disabled for now. - */ - - timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4; - - __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_CLK_CNTRL_OFFSET); - __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr + - XTTCPSS_IER_OFFSET); - - /* Setup IRQ the clock event timer */ - event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT]; - setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq); -} - -/** - * __raw_readl_cycles - Reads the timer counter register - * - * returns: Current timer counter register value - **/ -static cycle_t __raw_readl_cycles(struct clocksource *cs) -{ - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE]; - - return (cycle_t)__raw_readl(timer->base_addr + - XTTCPSS_COUNT_VAL_OFFSET); -} - - -/* - * Instantiate and initialize the clock source structure - */ -static struct clocksource clocksource_xttcpss = { - .name = "xttcpss_timer1", - .rating = 200, /* Reasonable clock source */ - .read = __raw_readl_cycles, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - -/** - * xttcpss_set_next_event - Sets the time interval for next event - * - * @cycles: Timer interval ticks - * @evt: Address of clock event instance - * - * returns: Always 0 - success - **/ -static int xttcpss_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; - - xttcpss_set_interval(timer, cycles); - return 0; -} - -/** - * xttcpss_set_mode - Sets the mode of timer - * - * @mode: Mode to be set - * @evt: Address of clock event instance - **/ -static void xttcpss_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT]; - u32 ctrl_reg; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - xttcpss_set_interval(timer, TIMER_RATE / HZ); - break; - case CLOCK_EVT_MODE_ONESHOT: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - ctrl_reg = __raw_readl(timer->base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); - break; - case CLOCK_EVT_MODE_RESUME: - ctrl_reg = __raw_readl(timer->base_addr + - XTTCPSS_CNT_CNTRL_OFFSET); - ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK; - __raw_writel(ctrl_reg, - timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET); - break; - } -} - -/* - * Instantiate and initialize the clock event structure - */ -static struct clock_event_device xttcpss_clockevent = { - .name = "xttcpss_timer2", - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = xttcpss_set_next_event, - .set_mode = xttcpss_set_mode, - .rating = 200, -}; - -/** - * xttcpss_timer_init - Initialize the timer - * - * Initializes the timer hardware and register the clock source and clock event - * timers with Linux kernal timer framework - **/ -static void __init xttcpss_timer_init(void) -{ - xttcpss_timer_hardware_init(); - clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE); - - /* Calculate the parameters to allow the clockevent to operate using - integer math - */ - clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4); - - xttcpss_clockevent.max_delta_ns = - clockevent_delta2ns(0xfffe, &xttcpss_clockevent); - xttcpss_clockevent.min_delta_ns = - clockevent_delta2ns(1, &xttcpss_clockevent); - - /* Indicate that clock event is on 1st CPU as SMP boot needs it */ - - xttcpss_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&xttcpss_clockevent); -} - -/* - * Instantiate and initialize the system timer structure - */ -struct sys_timer xttcpss_sys_timer = { - .init = xttcpss_timer_init, -}; |