diff options
Diffstat (limited to 'arch')
126 files changed, 4431 insertions, 3458 deletions
diff --git a/arch/arm/include/asm/ioctls.h b/arch/arm/include/asm/ioctls.h index 0b30894b548..9c962981612 100644 --- a/arch/arm/include/asm/ioctls.h +++ b/arch/arm/include/asm/ioctls.h @@ -1,89 +1,8 @@ #ifndef __ASM_ARM_IOCTLS_H #define __ASM_ARM_IOCTLS_H -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define TIOCGRS485 0x542E -#define TIOCSRS485 0x542F - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 8533bf04284..9fde873f588 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -131,6 +131,7 @@ static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { static struct fsl_usb2_platform_data otg_device_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI, + .workaround = FLS_USB2_WORKAROUND_ENGCM09152, }; static int otg_mode_host; diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index f85c8da17e8..d547036aff3 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -375,6 +375,31 @@ static void __init am3517_evm_init_irq(void) omap_gpio_init(); } +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 500, +}; + +static __init void am3517_evm_musb_init(void) +{ + u32 devconf2; + + /* + * Set up USB clock/mode in the DEVCONF2 register. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + + /* USB2.0 PHY reference clock is 13 MHz */ + devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE); + devconf2 |= CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN + | CONF2_DATPOL; + + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + + usb_musb_init(&musb_board_data); +} + static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \ @@ -393,6 +418,8 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* USB OTG DRVVBUS offset = 0x212 */ + OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else @@ -459,6 +486,9 @@ static void __init am3517_evm_init(void) ARRAY_SIZE(am3517evm_i2c1_boardinfo)); /*Ethernet*/ am3517_evm_ethernet_init(&am3517_evm_emac_pdata); + + /* MUSB */ + am3517_evm_musb_init(); } MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 33a5cde1c22..72605584bff 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c @@ -28,6 +28,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/am35xx.h> #include <plat/usb.h> #ifdef CONFIG_USB_MUSB_SOC @@ -89,6 +90,9 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) { if (cpu_is_omap243x()) { musb_resources[0].start = OMAP243X_HS_BASE; + } else if (cpu_is_omap3517() || cpu_is_omap3505()) { + musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; + musb_resources[1].start = INT_35XX_USBOTG_IRQ; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 2a9427c8cc4..9feddacfe85 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -218,6 +218,27 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata) # define USBT2TLL5PI (1 << 17) # define USB0PUENACTLOI (1 << 16) # define USBSTANDBYCTRL (1 << 15) +/* AM35x */ +/* USB 2.0 PHY Control */ +#define CONF2_PHY_GPIOMODE (1 << 23) +#define CONF2_OTGMODE (3 << 14) +#define CONF2_NO_OVERRIDE (0 << 14) +#define CONF2_FORCE_HOST (1 << 14) +#define CONF2_FORCE_DEVICE (2 << 14) +#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) +#define CONF2_SESENDEN (1 << 13) +#define CONF2_VBDTCTEN (1 << 12) +#define CONF2_REFFREQ_24MHZ (2 << 8) +#define CONF2_REFFREQ_26MHZ (7 << 8) +#define CONF2_REFFREQ_13MHZ (6 << 8) +#define CONF2_REFFREQ (0xf << 8) +#define CONF2_PHYCLKGD (1 << 7) +#define CONF2_VBUSSENSE (1 << 6) +#define CONF2_PHY_PLLON (1 << 5) +#define CONF2_RESET (1 << 4) +#define CONF2_PHYPWRDN (1 << 3) +#define CONF2_OTGPWRDN (1 << 2) +#define CONF2_DATPOL (1 << 1) #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) u32 omap1_usb0_init(unsigned nwires, unsigned is_device); diff --git a/arch/avr32/include/asm/ioctls.h b/arch/avr32/include/asm/ioctls.h index b7dd324b46a..909cf66feaf 100644 --- a/arch/avr32/include/asm/ioctls.h +++ b/arch/avr32/include/asm/ioctls.h @@ -1,90 +1,6 @@ #ifndef __ASM_AVR32_IOCTLS_H #define __ASM_AVR32_IOCTLS_H -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define TIOCGRS485 0x542E -#define TIOCSRS485 0x542F - -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x5460 - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* __ASM_AVR32_IOCTLS_H */ diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 5a3152b75cd..d9a1cb7ec30 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -300,7 +300,7 @@ config BF_REV_0_1 config BF_REV_0_2 bool "0.2" - depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) + depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) config BF_REV_0_3 bool "0.3" @@ -356,7 +356,7 @@ config MEM_MT48LC8M32B2B5_7 config MEM_MT48LC32M16A2TG_75 bool - depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) + depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) default y config MEM_MT48H32M16LFCJ_75 @@ -426,6 +426,7 @@ config CLKIN_HZ default "25000000" # most people use this default "27000000" if BFIN533_EZKIT default "30000000" if BFIN561_EZKIT + default "24000000" if BFIN527_AD7160EVAL help The frequency of CLKIN crystal oscillator on the board in Hz. Warning: This value should match the crystal on the board. Otherwise, @@ -463,6 +464,7 @@ config VCO_MULT default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) default "20" if BFIN561_EZKIT default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) + default "25" if BFIN527_AD7160EVAL help This controls the frequency of the on-chip PLL. This can be between 1 and 64. PLL Frequency = (Crystal Frequency) * (this setting) @@ -926,6 +928,12 @@ config ROMKERNEL endchoice +# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both +config XIP_KERNEL + bool + default y + depends on ROMKERNEL + source "mm/Kconfig" config BFIN_GPTIMERS diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile index 3e65b0ffe08..46738d49b7c 100644 --- a/arch/blackfin/Makefile +++ b/arch/blackfin/Makefile @@ -101,9 +101,8 @@ KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y) KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y) # - we utilize the silicon rev from the toolchain, so move it over to the checkflags -# - the l1_text attribute is Blackfin specific, so fake it out as used to kill warnings CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }') -CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__ +CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__ head-y := arch/$(ARCH)/kernel/init_task.o diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig new file mode 100644 index 00000000000..08c55f6b8b7 --- /dev/null +++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig @@ -0,0 +1,105 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +# CONFIG_ELF_CORE is not set +# CONFIG_AIO is not set +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_PREEMPT=y +CONFIG_BF527=y +CONFIG_BF_REV_0_2=y +CONFIG_IRQ_TWI=7 +CONFIG_IRQ_PORTH_INTA=7 +CONFIG_IRQ_PORTH_INTB=7 +CONFIG_BFIN527_AD7160EVAL=y +CONFIG_BF527_SPORT0_PORTF=y +CONFIG_BF527_UART1_PORTG=y +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600" +CONFIG_CLKIN_HZ=24000000 +CONFIG_HZ_300=y +# CONFIG_CYCLES_CLOCKSOURCE is not set +CONFIG_IP_CHECKSUM_L1=y +CONFIG_SYSCALL_TAB_L1=y +CONFIG_CPLB_SWITCH_TAB_L1=y +CONFIG_BFIN_GPTIMERS=y +CONFIG_C_CDPRIO=y +CONFIG_BANK_1=0x5554 +CONFIG_BANK_3=0xFFC0 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_NET=y +CONFIG_UNIX=y +# CONFIG_WIRELESS is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_MISC_DEVICES is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7160=y +CONFIG_TOUCHSCREEN_AD7160_FW=y +# CONFIG_SERIO is not set +# CONFIG_BFIN_DMA_INTERFACE is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_UART0=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_BFIN_OTP is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400 +CONFIG_SPI=y +CONFIG_SPI_BFIN=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_FB=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_BLACKFIN_VGA16 is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_G_SERIAL=y +CONFIG_MMC=y +CONFIG_MMC_SPI=y +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set +CONFIG_EARLY_PRINTK=y +CONFIG_CPLB_INFO=y +CONFIG_SECURITY=y +CONFIG_CRC_CCITT=m diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig new file mode 100644 index 00000000000..92ded5edc86 --- /dev/null +++ b/arch/blackfin/configs/BF527-TLL6527M_defconfig @@ -0,0 +1,180 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_LOCALVERSION="DEV_0-1_pre2010" +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +# CONFIG_FUTEX is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_SLAB=y +CONFIG_MMAP_ALLOW_UNINITIALIZED=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BF527=y +CONFIG_BF_REV_0_2=y +CONFIG_BFIN527_TLL6527M=y +CONFIG_BF527_UART1_PORTG=y +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 +CONFIG_BOOT_LOAD=0x400000 +# CONFIG_CYCLES_CLOCKSOURCE is not set +# CONFIG_SCHEDULE_L1 is not set +# CONFIG_MEMSET_L1 is not set +# CONFIG_MEMCPY_L1 is not set +# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set +CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_BFIN_GPTIMERS=y +CONFIG_DMA_UNCACHED_2M=y +CONFIG_C_CDPRIO=y +CONFIG_BANK_0=0xFFC2 +CONFIG_BANK_1=0xFFC2 +CONFIG_BANK_2=0xFFC2 +CONFIG_BANK_3=0xFFC2 +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_IRDA=m +CONFIG_IRLAN=m +CONFIG_IRCOMM=m +CONFIG_IRTTY_SIR=m +CONFIG_BFIN_SIR=m +CONFIG_BFIN_SIR0=y +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_GPIO_ADDR=y +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=m +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_BFIN_MAC=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=y +CONFIG_INPUT_ADXL34X=y +# CONFIG_SERIO is not set +CONFIG_BFIN_PPI=m +CONFIG_BFIN_SIMPLE_TIMER=m +CONFIG_BFIN_SPORT=m +# CONFIG_CONSOLE_TRANSLATIONS is not set +# CONFIG_DEVKMEM is not set +CONFIG_BFIN_JTAG_COMM=m +CONFIG_SERIAL_BFIN=y +CONFIG_SERIAL_BFIN_CONSOLE=y +CONFIG_SERIAL_BFIN_UART1=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_SMBUS=y +CONFIG_I2C_BLACKFIN_TWI=y +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_BFIN_WDT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_BLACKFIN_CAM=m +CONFIG_OV9655=y +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_6x11=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_BLACKFIN_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_SOC=y +CONFIG_SND_BF5XX_I2S=y +CONFIG_SND_BF5XX_SOC_SSM2602=y +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=m +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_BFIN=y +CONFIG_EXT2_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_UTF8=m +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_MMRS=y +CONFIG_DEBUG_HWERR=y +CONFIG_EXACT_HWERR=y +CONFIG_DEBUG_DOUBLEFAULT=y +CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y +CONFIG_EARLY_PRINTK=y +CONFIG_CPLB_INFO=y +CONFIG_SECURITY=y +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC7=m diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index d9eb29e2555..9e7c5379d3f 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -1,4 +1,5 @@ include include/asm-generic/Kbuild.asm header-y += bfin_sport.h +header-y += cachectl.h header-y += fixed_code.h diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index 4223cf08ce8..0b5136e334b 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h @@ -41,6 +41,25 @@ #define BIT_STU_SENDOVER 0x0001 #define BIT_STU_RECVFULL 0x0020 +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin spi registers layout + */ +struct bfin_spi_regs { + __BFP(ctl); + __BFP(flg); + __BFP(stat); + __BFP(tdbr); + __BFP(rdbr); + __BFP(baud); + __BFP(shadow); +}; + #define MAX_CTRL_CS 8 /* cs in spi controller */ /* device.platform_data for SSP controller devices */ diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h index eec0076a385..b1492e0bcab 100644 --- a/arch/blackfin/include/asm/bfin_can.h +++ b/arch/blackfin/include/asm/bfin_can.h @@ -34,6 +34,7 @@ struct bfin_can_mask_regs { }; struct bfin_can_channel_regs { + /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */ u16 data[8]; __BFP(dlc); __BFP(tsv); @@ -83,16 +84,18 @@ struct bfin_can_regs { __BFP(gif); /* offset 0x9c */ __BFP(control); /* offset 0xa0 */ __BFP(intr); /* offset 0xa4 */ - u32 __pad3[1]; + __BFP(version); /* offset 0xa8 */ __BFP(mbtd); /* offset 0xac */ __BFP(ewr); /* offset 0xb0 */ __BFP(esr); /* offset 0xb4 */ - u32 __pad4[2]; + u32 __pad3[2]; __BFP(ucreg); /* offset 0xc0 */ __BFP(uccnt); /* offset 0xc4 */ __BFP(ucrc); /* offset 0xc8 */ __BFP(uccnf); /* offset 0xcc */ - u32 __pad5[12]; + u32 __pad4[1]; + __BFP(version2); /* offset 0xd4 */ + u32 __pad5[10]; /* * channel(mailbox) mask and message registers diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h new file mode 100644 index 00000000000..003900886f9 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_ppi.h @@ -0,0 +1,51 @@ +/* + * bfin_ppi.h - interface to Blackfin PPIs + * + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_PPI_H__ +#define __ASM_BFIN_PPI_H__ + +#include <linux/types.h> + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin ppi registers layout + */ +struct bfin_ppi_regs { + __BFP(control); + __BFP(status); + __BFP(count); + __BFP(delay); + __BFP(frame); +}; + +/* + * bfin eppi registers layout + */ +struct bfin_eppi_regs { + __BFP(status); + __BFP(hcount); + __BFP(hdelay); + __BFP(vcount); + __BFP(vdelay); + __BFP(frame); + __BFP(line); + __BFP(clkdiv); + u32 control; + u32 fs1w_hbl; + u32 fs1p_avpl; + u32 fs2w_lvb; + u32 fs2p_lavf; + u32 clip; +}; + +#endif diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h new file mode 100644 index 00000000000..03255df6c1e --- /dev/null +++ b/arch/blackfin/include/asm/cachectl.h @@ -0,0 +1,20 @@ +/* + * based on the mips/cachectl.h + * + * Copyright 2010 Analog Devices Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h index 6c39d94b44d..a1f6817687e 100644 --- a/arch/blackfin/include/asm/cdef_LPBlackfin.h +++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h @@ -172,16 +172,19 @@ #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) #define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) #if 0 #define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ #endif -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) +#if ANOMALY_05000481 +#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) +#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) +#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) +#endif + /* Event/Interrupt Registers*/ #define bfin_read_EVT0() bfin_read32(EVT0) diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h index aaa1c6c2bc1..832d7c009a2 100644 --- a/arch/blackfin/include/asm/ptrace.h +++ b/arch/blackfin/include/asm/ptrace.h @@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child); /* common code demands this function */ #define ptrace_disable(child) user_disable_single_step(child) +extern int is_user_addr_valid(struct task_struct *child, + unsigned long start, unsigned long len); + /* * Get the address of the live pt_regs for the specified task. * These are saved onto the top kernel stack when the process diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h index 94a4a12e3bf..a0cb0caff15 100644 --- a/arch/blackfin/include/asm/serial.h +++ b/arch/blackfin/include/asm/serial.h @@ -1,2 +1 @@ #include <asm-generic/serial.h> -#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 14fcd254b18..928ae975b87 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -392,8 +392,9 @@ #define __NR_fanotify_init 371 #define __NR_fanotify_mark 372 #define __NR_prlimit64 373 +#define __NR_cacheflush 374 -#define __NR_syscall 374 +#define __NR_syscall 375 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c index ca1c1f9debd..170cf90735b 100644 --- a/arch/blackfin/kernel/bfin_gpio.c +++ b/arch/blackfin/kernel/bfin_gpio.c @@ -1,7 +1,7 @@ /* * GPIO Abstraction Layer * - * Copyright 2006-2009 Analog Devices Inc. + * Copyright 2006-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later */ @@ -215,82 +215,91 @@ static void port_setup(unsigned gpio, unsigned short usage) } #ifdef BF537_FAMILY -static struct { - unsigned short res; - unsigned short offset; -} port_mux_lut[] = { - {.res = P_PPI0_D13, .offset = 11}, - {.res = P_PPI0_D14, .offset = 11}, - {.res = P_PPI0_D15, .offset = 11}, - {.res = P_SPORT1_TFS, .offset = 11}, - {.res = P_SPORT1_TSCLK, .offset = 11}, - {.res = P_SPORT1_DTPRI, .offset = 11}, - {.res = P_PPI0_D10, .offset = 10}, - {.res = P_PPI0_D11, .offset = 10}, - {.res = P_PPI0_D12, .offset = 10}, - {.res = P_SPORT1_RSCLK, .offset = 10}, - {.res = P_SPORT1_RFS, .offset = 10}, - {.res = P_SPORT1_DRPRI, .offset = 10}, - {.res = P_PPI0_D8, .offset = 9}, - {.res = P_PPI0_D9, .offset = 9}, - {.res = P_SPORT1_DRSEC, .offset = 9}, - {.res = P_SPORT1_DTSEC, .offset = 9}, - {.res = P_TMR2, .offset = 8}, - {.res = P_PPI0_FS3, .offset = 8}, - {.res = P_TMR3, .offset = 7}, - {.res = P_SPI0_SSEL4, .offset = 7}, - {.res = P_TMR4, .offset = 6}, - {.res = P_SPI0_SSEL5, .offset = 6}, - {.res = P_TMR5, .offset = 5}, - {.res = P_SPI0_SSEL6, .offset = 5}, - {.res = P_UART1_RX, .offset = 4}, - {.res = P_UART1_TX, .offset = 4}, - {.res = P_TMR6, .offset = 4}, - {.res = P_TMR7, .offset = 4}, - {.res = P_UART0_RX, .offset = 3}, - {.res = P_UART0_TX, .offset = 3}, - {.res = P_DMAR0, .offset = 3}, - {.res = P_DMAR1, .offset = 3}, - {.res = P_SPORT0_DTSEC, .offset = 1}, - {.res = P_SPORT0_DRSEC, .offset = 1}, - {.res = P_CAN0_RX, .offset = 1}, - {.res = P_CAN0_TX, .offset = 1}, - {.res = P_SPI0_SSEL7, .offset = 1}, - {.res = P_SPORT0_TFS, .offset = 0}, - {.res = P_SPORT0_DTPRI, .offset = 0}, - {.res = P_SPI0_SSEL2, .offset = 0}, - {.res = P_SPI0_SSEL3, .offset = 0}, +static const s8 port_mux[] = { + [GPIO_PF0] = 3, + [GPIO_PF1] = 3, + [GPIO_PF2] = 4, + [GPIO_PF3] = 4, + [GPIO_PF4] = 5, + [GPIO_PF5] = 6, + [GPIO_PF6] = 7, + [GPIO_PF7] = 8, + [GPIO_PF8 ... GPIO_PF15] = -1, + [GPIO_PG0 ... GPIO_PG7] = -1, + [GPIO_PG8] = 9, + [GPIO_PG9] = 9, + [GPIO_PG10] = 10, + [GPIO_PG11] = 10, + [GPIO_PG12] = 10, + [GPIO_PG13] = 11, + [GPIO_PG14] = 11, + [GPIO_PG15] = 11, + [GPIO_PH0 ... GPIO_PH15] = -1, + [PORT_PJ0 ... PORT_PJ3] = -1, + [PORT_PJ4] = 1, + [PORT_PJ5] = 1, + [PORT_PJ6 ... PORT_PJ9] = -1, + [PORT_PJ10] = 0, + [PORT_PJ11] = 0, }; -static void portmux_setup(unsigned short per) +static int portmux_group_check(unsigned short per) { - u16 y, offset, muxreg; + u16 ident = P_IDENT(per); u16 function = P_FUNCT2MUX(per); + s8 offset = port_mux[ident]; + u16 m, pmux, pfunc; - for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { - if (port_mux_lut[y].res == per) { - - /* SET PORTMUX REG */ - - offset = port_mux_lut[y].offset; - muxreg = bfin_read_PORT_MUX(); + if (offset < 0) + return 0; - if (offset != 1) - muxreg &= ~(1 << offset); - else - muxreg &= ~(3 << 1); + pmux = bfin_read_PORT_MUX(); + for (m = 0; m < ARRAY_SIZE(port_mux); ++m) { + if (m == ident) + continue; + if (port_mux[m] != offset) + continue; + if (!is_reserved(peri, m, 1)) + continue; - muxreg |= (function << offset); - bfin_write_PORT_MUX(muxreg); + if (offset == 1) + pfunc = (pmux >> offset) & 3; + else + pfunc = (pmux >> offset) & 1; + if (pfunc != function) { + pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", + ident, function, m, pfunc); + return -EINVAL; } } + + return 0; +} + +static void portmux_setup(unsigned short per) +{ + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + s8 offset = port_mux[ident]; + u16 pmux; + + if (offset == -1) + return; + + pmux = bfin_read_PORT_MUX(); + if (offset != 1) + pmux &= ~(1 << offset); + else + pmux &= ~(3 << 1); + pmux |= (function << offset); + bfin_write_PORT_MUX(pmux); } #elif defined(CONFIG_BF54x) inline void portmux_setup(unsigned short per) { - u32 pmux; u16 ident = P_IDENT(per); u16 function = P_FUNCT2MUX(per); + u32 pmux; pmux = gpio_array[gpio_bank(ident)]->port_mux; @@ -302,20 +311,54 @@ inline void portmux_setup(unsigned short per) inline u16 get_portmux(unsigned short per) { - u32 pmux; u16 ident = P_IDENT(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - + u32 pmux = gpio_array[gpio_bank(ident)]->port_mux; return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); } +static int portmux_group_check(unsigned short per) +{ + return 0; +} #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) +static int portmux_group_check(unsigned short per) +{ + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); + u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + u16 pin, gpiopin, pfunc; + + for (pin = 0; pin < GPIO_BANKSIZE; ++pin) { + if (offset != pmux_offset[gpio_bank(ident)][pin]) + continue; + + gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin; + if (gpiopin == ident) + continue; + if (!is_reserved(peri, gpiopin, 1)) + continue; + + pfunc = *port_mux[gpio_bank(ident)]; + pfunc = (pfunc >> offset) & 3; + if (pfunc != function) { + pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n", + ident, function, gpiopin, pfunc); + return -EINVAL; + } + } + + return 0; +} + inline void portmux_setup(unsigned short per) { - u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); + u16 ident = P_IDENT(per); + u16 function = P_FUNCT2MUX(per); u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; + u16 pmux; pmux = *port_mux[gpio_bank(ident)]; + if (((pmux >> offset) & 3) == function) + return; pmux &= ~(3 << offset); pmux |= (function & 3) << offset; *port_mux[gpio_bank(ident)] = pmux; @@ -323,6 +366,10 @@ inline void portmux_setup(unsigned short per) } #else # define portmux_setup(...) do { } while (0) +static int portmux_group_check(unsigned short per) +{ + return 0; +} #endif #ifndef CONFIG_BF54x @@ -735,6 +782,10 @@ int peripheral_request(unsigned short per, const char *label) } } + if (unlikely(portmux_group_check(per))) { + hard_local_irq_restore(flags); + return -EBUSY; + } anyway: reserve(peri, ident); diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c index c86a3ed5f48..cd0c090ebc5 100644 --- a/arch/blackfin/kernel/process.c +++ b/arch/blackfin/kernel/process.c @@ -493,6 +493,11 @@ int _access_ok(unsigned long addr, unsigned long size) return 1; #endif +#ifndef CONFIG_EXCEPTION_L1_SCRATCH + if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len)) + return 1; +#endif + aret = in_async(addr, size); if (aret < 2) return aret; diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 6ec77685df5..b3583935413 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c @@ -27,6 +27,7 @@ #include <asm/fixed_code.h> #include <asm/cacheflush.h> #include <asm/mem_map.h> +#include <asm/mmu_context.h> /* * does not yet catch signals sent when the child dies. @@ -113,8 +114,8 @@ put_reg(struct task_struct *task, long regno, unsigned long data) /* * check that an address falls within the bounds of the target process's memory mappings */ -static inline int is_user_addr_valid(struct task_struct *child, - unsigned long start, unsigned long len) +int +is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len) { struct vm_area_struct *vma; struct sram_list_struct *sraml; @@ -135,6 +136,13 @@ static inline int is_user_addr_valid(struct task_struct *child, if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END) return 0; +#ifdef CONFIG_APP_STACK_L1 + if (child->mm->context.l1_stack_save) + if (start >= (unsigned long)l1_stack_base && + start + len < (unsigned long)l1_stack_base + l1_stack_len) + return 0; +#endif + return -EIO; } diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c index bdc1e2f0da3..89448ed7065 100644 --- a/arch/blackfin/kernel/sys_bfin.c +++ b/arch/blackfin/kernel/sys_bfin.c @@ -21,6 +21,8 @@ #include <asm/cacheflush.h> #include <asm/dma.h> +#include <asm/cachectl.h> +#include <asm/ptrace.h> asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags) { @@ -70,3 +72,16 @@ asmlinkage int sys_bfin_spinlock(int *p) return ret; } + +SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op) +{ + if (is_user_addr_valid(current, addr, len) != 0) + return -EINVAL; + + if (op & DCACHE) + blackfin_dcache_flush_range(addr, addr + len); + if (op & ICACHE) + blackfin_icache_flush_range(addr, addr + len); + + return 0; +} diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 44d6d529902..f95e6096719 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c @@ -312,7 +312,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* SPI (0) */ static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 5, + .num_chipselect = 6, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -347,7 +347,7 @@ static struct platform_device bfin_spi0_device = { /* SPI (1) */ static struct bfin5xx_spi_master bfin_spi1_info = { - .num_chipselect = 5, + .num_chipselect = 6, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; @@ -525,6 +525,14 @@ static struct platform_device bfin_sir1_device = { #endif #endif +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) static struct resource bfin_twi0_resource[] = { [0] = { @@ -559,6 +567,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { .irq = IRQ_PF8, }, #endif +#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE) + { + I2C_BOARD_INFO("ssm2602", 0x1b), + }, +#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -736,6 +749,10 @@ static struct platform_device *stamp_devices[] __initdata = { &i2c_bfin_twi_device, #endif +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s, +#endif + #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART &bfin_sport0_uart_device, diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c index 9b72e5cb21f..bead810a654 100644 --- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c +++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c @@ -291,7 +291,7 @@ static struct platform_device bfin_spi0_device = { /* SPI (1) */ static struct bfin5xx_spi_master bfin_spi1_info = { - .num_chipselect = 5, + .num_chipselect = 6, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h index 29498e59e71..e16969f24ff 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h @@ -262,14 +262,14 @@ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) +#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) +#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) +#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) +#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) @@ -317,14 +317,14 @@ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) +#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) +#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) +#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) +#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index 037a51fd8e9..5f84913dcd9 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h @@ -748,51 +748,6 @@ #define FFE 0x20 /* Force Framing Error On Transmit */ -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig index b14c28810a4..1cc2667c10f 100644 --- a/arch/blackfin/mach-bf527/boards/Kconfig +++ b/arch/blackfin/mach-bf527/boards/Kconfig @@ -24,4 +24,14 @@ config BFIN526_EZBRD help BF526-EZBRD/EZKIT Lite board support. +config BFIN527_AD7160EVAL + bool "BF527-AD7160-EVAL" + help + BF527-AD7160-EVAL board support. + +config BFIN527_TLL6527M + bool "The Learning Labs TLL6527M" + help + TLL6527M V1.0 platform support + endchoice diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile index 51a5817c4a9..1d67da9f05a 100644 --- a/arch/blackfin/mach-bf527/boards/Makefile +++ b/arch/blackfin/mach-bf527/boards/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o +obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o +obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c new file mode 100644 index 00000000000..fc767ac7638 --- /dev/null +++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c @@ -0,0 +1,870 @@ +/* + * Copyright 2004-20010 Analog Devices Inc. + * 2005 National ICT Australia (NICTA) + * Aidan Williams <aidan@nicta.com.au> + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/i2c.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/usb/musb.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <asm/dma.h> +#include <asm/bfin5xx_spi.h> +#include <asm/reboot.h> +#include <asm/nand.h> +#include <asm/portmux.h> +#include <asm/dpmc.h> + + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "ADI BF527-AD7160EVAL"; + +/* + * Driver needs to know address, irq and flag pin. + */ + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) +static struct resource musb_resources[] = { + [0] = { + .start = 0xffc03800, + .end = 0xffc03cff, + .flags = IORESOURCE_MEM, + }, + [1] = { /* general IRQ */ + .start = IRQ_USB_INT0, + .end = IRQ_USB_INT0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, + [2] = { /* DMA IRQ */ + .start = IRQ_USB_DMA, + .end = IRQ_USB_DMA, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct musb_hdrc_config musb_config = { + .multipoint = 0, + .dyn_fifo = 0, + .soft_con = 1, + .dma = 1, + .num_eps = 8, + .dma_channels = 8, + .gpio_vrsel = GPIO_PG13, + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_OTG) + .mode = MUSB_OTG, +#elif defined(CONFIG_USB_MUSB_HDRC_HCD) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_PERIPHERAL, +#endif + .config = &musb_config, +}; + +static u64 musb_dmamask = ~(u32)0; + +static struct platform_device musb_device = { + .name = "musb_hdrc", + .id = 0, + .dev = { + .dma_mask = &musb_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &musb_plat, + }, + .num_resources = ARRAY_SIZE(musb_resources), + .resource = musb_resources, +}; +#endif + +#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE) +static struct resource bf52x_ra158z_resources[] = { + { + .start = IRQ_PPI_ERROR, + .end = IRQ_PPI_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf52x_ra158z_device = { + .name = "bfin-ra158z", + .id = -1, + .num_resources = ARRAY_SIZE(bf52x_ra158z_resources), + .resource = bf52x_ra158z_resources, +}; +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition ad7160eval_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0x40000, + .offset = 0, + }, { + .name = "linux kernel(nor)", + .size = 0x1C0000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(nor)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data ad7160eval_flash_data = { + .width = 2, + .parts = ad7160eval_partitions, + .nr_parts = ARRAY_SIZE(ad7160eval_partitions), +}; + +static struct resource ad7160eval_flash_resource = { + .start = 0x20000000, + .end = 0x203fffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ad7160eval_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ad7160eval_flash_data, + }, + .num_resources = 1, + .resource = &ad7160eval_flash_resource, +}; +#endif + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) +static struct mtd_partition partition_info[] = { + { + .name = "linux kernel(nand)", + .offset = 0, + .size = 4 * 1024 * 1024, + }, + { + .name = "file system(nand)", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct bf5xx_nand_platform bf5xx_nand_platform = { + .data_width = NFC_NWIDTH_8, + .partitions = partition_info, + .nr_partitions = ARRAY_SIZE(partition_info), + .rd_dly = 3, + .wr_dly = 3, +}; + +static struct resource bf5xx_nand_resources[] = { + { + .start = NFC_CTL, + .end = NFC_DATA_RD + 2, + .flags = IORESOURCE_MEM, + }, + { + .start = CH_NFC, + .end = CH_NFC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bf5xx_nand_device = { + .name = "bf5xx-nand", + .id = 0, + .num_resources = ARRAY_SIZE(bf5xx_nand_resources), + .resource = bf5xx_nand_resources, + .dev = { + .platform_data = &bf5xx_nand_platform, + }, +}; +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +#include <linux/bfin_mac.h> +static const unsigned short bfin_mac_peripherals[] = P_RMII0; + +static struct bfin_phydev_platform_data bfin_phydev_data[] = { + { + .addr = 1, + .irq = IRQ_MAC_PHYINT, + }, +}; + +static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { + .phydev_number = 1, + .phydev_data = bfin_phydev_data, + .phy_mode = PHY_INTERFACE_MODE_RMII, + .mac_peripherals = bfin_mac_peripherals, +}; + +static struct platform_device bfin_mii_bus = { + .name = "bfin_mii_bus", + .dev = { + .platform_data = &bfin_mii_bus_data, + } +}; + +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", + .dev = { + .platform_data = &bfin_mii_bus, + } +}; +#endif + + +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "bootloader(spi)", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_CAP_ROM + }, { + .name = "linux kernel(spi)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "m25p16", +}; + +/* SPI flash chip (m25p64) */ +static struct bfin5xx_spi_chip spi_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) +static struct bfin5xx_spi_chip ad1836_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +static struct bfin5xx_spi_chip mmc_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +static struct bfin5xx_spi_chip spidev_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) +static struct platform_device bfin_tdm = { + .name = "bfin-tdm", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) + { + .modalias = "ad183x", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 4, + .controller_data = &ad1836_spi_chip_info, + }, +#endif +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + { + .modalias = "mmc_spi", + .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = GPIO_PH3 + MAX_CTRL_CS, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + { + .modalias = "spidev", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &spidev_chip_info, + }, +#endif +}; + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* SPI controller data */ +static struct bfin5xx_spi_master bfin_spi0_info = { + .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_spi0_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bfin_spi0_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_THR, + .end = UART0_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART1_CTSRTS + { /* CTS pin */ + .start = GPIO_PF9, + .end = GPIO_PF9, + .flags = IORESOURCE_IO, + }, + { /* RTS pin */ + .start = GPIO_PF10, + .end = GPIO_PF10, + .flags = IORESOURCE_IO, + }, +#endif +}; + +unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; +#endif +#ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; +#endif +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE) +#include <linux/input/ad7160.h> +static const struct ad7160_platform_data bfin_ad7160_ts_info = { + .sensor_x_res = 854, + .sensor_y_res = 480, + .pressure = 100, + .filter_coef = 3, + .coord_pref = AD7160_ORIG_TOP_LEFT, + .first_touch_window = 5, + .move_window = 3, + .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID | + AD7160_EMIT_ABS_MT_PRESSURE | + AD7160_TRACKING_ID_ASCENDING, + .finger_act_ctrl = 0x64, + .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) | + AD7160_HAPTIC_SLOT_A_LVL_HIGH | + AD7160_HAPTIC_SLOT_B(60) | + AD7160_HAPTIC_SLOT_B_LVL_LOW, + + .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) | + AD7160_HAPTIC_SLOT_A_LVL_HIGH | + AD7160_HAPTIC_SLOT_B(80) | + AD7160_HAPTIC_SLOT_B_LVL_LOW | + AD7160_HAPTIC_SLOT_C(120) | + AD7160_HAPTIC_SLOT_C_LVL_HIGH | + AD7160_HAPTIC_SLOT_D(30) | + AD7160_HAPTIC_SLOT_D_LVL_LOW, +}; +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; +#endif + +static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_TOUCHSCREEN_AD7160) || defined(CONFIG_TOUCHSCREEN_AD7160_MODULE) + { + I2C_BOARD_INFO("ad7160", 0x33), + .irq = IRQ_PH1, + .platform_data = (void *)&bfin_ad7160_ts_info, + }, +#endif +}; + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 +}; + +static struct platform_device bfin_sport0_uart_device = { + .name = "bfin-sport-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 +}; + +static struct platform_device bfin_sport1_uart_device = { + .name = "bfin-sport-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#include <asm/bfin_rotary.h> + +static struct bfin_rotary_platform_data bfin_rotary_data = { + /*.rotary_up_key = KEY_UP,*/ + /*.rotary_down_key = KEY_DOWN,*/ + .rotary_rel_code = REL_WHEEL, + .rotary_button_key = KEY_ENTER, + .debounce = 10, /* 0..17 */ + .mode = ROT_QUAD_ENC | ROT_DEBE, +}; + +static struct resource bfin_rotary_resources[] = { + { + .start = IRQ_CNT, + .end = IRQ_CNT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_rotary_device = { + .name = "bfin-rotary", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_rotary_resources), + .resource = bfin_rotary_resources, + .dev = { + .platform_data = &bfin_rotary_data, + }, +}; +#endif + +static const unsigned int cclk_vlev_datasheet[] = { + VRPAIR(VLEV_100, 400000000), + VRPAIR(VLEV_105, 426000000), + VRPAIR(VLEV_110, 500000000), + VRPAIR(VLEV_115, 533000000), + VRPAIR(VLEV_120, 600000000), +}; + +static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { + .tuple_tab = cclk_vlev_datasheet, + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), + .vr_settling_time = 25 /* us */, +}; + +static struct platform_device bfin_dpmc = { + .name = "bfin dpmc", + .dev = { + .platform_data = &bfin_dmpc_vreg_data, + }, +}; + +static struct platform_device *stamp_devices[] __initdata = { + + &bfin_dpmc, + +#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) + &bf5xx_nand_device, +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) + &musb_device, +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) + &bfin_mii_bus, + &bfin_mac_device, +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &bfin_spi0_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_FB_BFIN_RA158Z) || defined(CONFIG_FB_BFIN_RA158Z_MODULE) + &bf52x_ra158z_device, +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif + +#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) + &bfin_rotary_device, +#endif + +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) + &ad7160eval_flash_device, +#endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s, +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) + &bfin_tdm, +#endif +}; + +static int __init ad7160eval_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __func__); + i2c_register_board_info(0, bfin_i2c_board_info, + ARRAY_SIZE(bfin_i2c_board_info)); + platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); + return 0; +} + +arch_initcall(ad7160eval_init); + +static struct platform_device *ad7160eval_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(ad7160eval_early_devices, + ARRAY_SIZE(ad7160eval_early_devices)); +} + +void native_machine_restart(char *cmd) +{ + /* workaround reboot hang when booting from SPI */ + if ((bfin_read_SYSCR() & 0x7) == 0x3) + bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); +} + +void bfin_get_ether_addr(char *addr) +{ + /* the MAC is stored in OTP memory page 0xDF */ + u32 ret; + u64 otp_mac; + u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; + + ret = otp_read(0xDF, 0x00, &otp_mac); + if (!(ret & 0x1)) { + char *otp_mac_p = (char *)&otp_mac; + for (ret = 0; ret < 6; ++ret) + addr[ret] = otp_mac_p[5 - ret]; + } +} +EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 645ba5c8077..38037c7e125 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -342,8 +342,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -420,13 +420,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index c975fe88eba..6cc64a1e78b 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c @@ -137,8 +137,12 @@ static struct platform_device ezbrd_flash_device = { #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) static struct mtd_partition partition_info[] = { { - .name = "linux kernel(nand)", + .name = "bootloader(nand)", .offset = 0, + .size = 0x40000, + }, { + .name = "linux kernel(nand)", + .offset = MTDPART_OFS_APPEND, .size = 4 * 1024 * 1024, }, { diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index 87b41e994ba..07c132dc412 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -222,8 +222,12 @@ static struct platform_device ezkit_flash_device = { #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) static struct mtd_partition partition_info[] = { { - .name = "linux kernel(nand)", + .name = "bootloader(nand)", .offset = 0, + .size = 0x40000, + }, { + .name = "linux kernel(nand)", + .offset = MTDPART_OFS_APPEND, .size = 4 * 1024 * 1024, }, { @@ -431,8 +435,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -547,13 +551,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -929,6 +933,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { I2C_BOARD_INFO("ssm2602", 0x1b), }, #endif +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("ad5252", 0x2f), + }, +#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c new file mode 100644 index 00000000000..ae4130e97c0 --- /dev/null +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -0,0 +1,986 @@ +/* File: arch/blackfin/mach-bf527/boards/tll6527m.c + * Based on: arch/blackfin/mach-bf527/boards/ezkit.c + * Author: Ashish Gupta + * + * Copyright: 2010 - The Learning Labs Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/i2c.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/usb/musb.h> +#include <linux/leds.h> +#include <linux/input.h> +#include <asm/dma.h> +#include <asm/bfin5xx_spi.h> +#include <asm/reboot.h> +#include <asm/nand.h> +#include <asm/portmux.h> +#include <asm/dpmc.h> + +#if defined(CONFIG_TOUCHSCREEN_AD7879) \ + || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) +#include <linux/spi/ad7879.h> +#define LCD_BACKLIGHT_GPIO 0x40 +/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for + * LCD Backlight Enable + */ +#endif + +/* + * Name the Board for the /proc/cpuinfo + */ +const char bfin_board_name[] = "TLL6527M"; +/* + * Driver needs to know address, irq and flag pin. + */ + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) +static struct resource musb_resources[] = { + [0] = { + .start = 0xffc03800, + .end = 0xffc03cff, + .flags = IORESOURCE_MEM, + }, + [1] = { /* general IRQ */ + .start = IRQ_USB_INT0, + .end = IRQ_USB_INT0, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, + [2] = { /* DMA IRQ */ + .start = IRQ_USB_DMA, + .end = IRQ_USB_DMA, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct musb_hdrc_config musb_config = { + .multipoint = 0, + .dyn_fifo = 0, + .soft_con = 1, + .dma = 1, + .num_eps = 8, + .dma_channels = 8, + /*.gpio_vrsel = GPIO_PG13,*/ + /* Some custom boards need to be active low, just set it to "0" + * if it is the case. + */ + .gpio_vrsel_active = 1, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_USB_MUSB_OTG) + .mode = MUSB_OTG, +#elif defined(CONFIG_USB_MUSB_HDRC_HCD) + .mode = MUSB_HOST, +#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) + .mode = MUSB_PERIPHERAL, +#endif + .config = &musb_config, +}; + +static u64 musb_dmamask = ~(u32)0; + +static struct platform_device musb_device = { + .name = "musb_hdrc", + .id = 0, + .dev = { + .dma_mask = &musb_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &musb_plat, + }, + .num_resources = ARRAY_SIZE(musb_resources), + .resource = musb_resources, +}; +#endif + +#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) +#include <asm/bfin-lq035q1.h> + +static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { + .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, + .ppi_mode = USE_RGB565_16_BIT_PPI, + .use_bl = 1, + .gpio_bl = LCD_BACKLIGHT_GPIO, +}; + +static struct resource bfin_lq035q1_resources[] = { + { + .start = IRQ_PPI_ERROR, + .end = IRQ_PPI_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_lq035q1_device = { + .name = "bfin-lq035q1", + .id = -1, + .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), + .resource = bfin_lq035q1_resources, + .dev = { + .platform_data = &bfin_lq035q1_data, + }, +}; +#endif + +#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) +static struct mtd_partition tll6527m_partitions[] = { + { + .name = "bootloader(nor)", + .size = 0xA0000, + .offset = 0, + }, { + .name = "linux kernel(nor)", + .size = 0xD00000, + .offset = MTDPART_OFS_APPEND, + }, { + .name = "file system(nor)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data tll6527m_flash_data = { + .width = 2, + .parts = tll6527m_partitions, + .nr_parts = ARRAY_SIZE(tll6527m_partitions), +}; + +static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 }; + +static struct resource tll6527m_flash_resource[] = { + { + .name = "cfi_probe", + .start = 0x20000000, + .end = 0x201fffff, + .flags = IORESOURCE_MEM, + }, { + .start = (unsigned long)tll6527m_flash_gpios, + .end = ARRAY_SIZE(tll6527m_flash_gpios), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device tll6527m_flash_device = { + .name = "gpio-addr-flash", + .id = 0, + .dev = { + .platform_data = &tll6527m_flash_data, + }, + .num_resources = ARRAY_SIZE(tll6527m_flash_resource), + .resource = tll6527m_flash_resource, +}; +#endif + +#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE) +/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented + * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0. + * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being + * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS + */ +#include <linux/gpio-decoder.h> +#define EXP_GPIO_SPISEL_BASE 0x64 +static unsigned gpio_addr_inputs[] = { + GPIO_PG1, GPIO_PH9, GPIO_PH10 +}; + +static struct gpio_decoder_platfrom_data spi_decoded_cs = { + .base = EXP_GPIO_SPISEL_BASE, + .input_addrs = gpio_addr_inputs, + .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs), + .default_output = 0, +/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */ +}; + +static struct platform_device spi_decoded_gpio = { + .name = "gpio-decoder", + .id = 0, + .dev = { + .platform_data = &spi_decoded_cs, + }, +}; + +#else +#define EXP_GPIO_SPISEL_BASE 0x0 + +#endif + +#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) +#include <linux/input/adxl34x.h> +static const struct adxl34x_platform_data adxl345_info = { + .x_axis_offset = 0, + .y_axis_offset = 0, + .z_axis_offset = 0, + .tap_threshold = 0x31, + .tap_duration = 0x10, + .tap_latency = 0x60, + .tap_window = 0xF0, + .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, + .act_axis_control = 0xFF, + .activity_threshold = 5, + .inactivity_threshold = 2, + .inactivity_time = 2, + .free_fall_threshold = 0x7, + .free_fall_time = 0x20, + .data_rate = 0x8, + .data_range = ADXL_FULL_RES, + + .ev_type = EV_ABS, + .ev_code_x = ABS_X, /* EV_REL */ + .ev_code_y = ABS_Y, /* EV_REL */ + .ev_code_z = ABS_Z, /* EV_REL */ + + .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + +/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ + .ev_code_act_inactivity = KEY_A, /* EV_KEY */ + .use_int2 = 1, + .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, + .fifo_mode = ADXL_FIFO_STREAM, +}; +#endif + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) +static struct platform_device rtc_device = { + .name = "rtc-bfin", + .id = -1, +}; +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) +static struct platform_device bfin_mii_bus = { + .name = "bfin_mii_bus", +}; + +static struct platform_device bfin_mac_device = { + .name = "bfin_mac", + .dev.platform_data = &bfin_mii_bus, +}; +#endif + +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) +static struct mtd_partition bfin_spi_flash_partitions[] = { + { + .name = "bootloader(spi)", + .size = 0x00040000, + .offset = 0, + .mask_flags = MTD_CAP_ROM + }, { + .name = "linux kernel(spi)", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct flash_platform_data bfin_spi_flash_data = { + .name = "m25p80", + .parts = bfin_spi_flash_partitions, + .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), + .type = "m25p16", +}; + +/* SPI flash chip (m25p64) */ +static struct bfin5xx_spi_chip spi_flash_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_BFIN_SPI_ADC) \ + || defined(CONFIG_BFIN_SPI_ADC_MODULE) +/* SPI ADC chip */ +static struct bfin5xx_spi_chip spi_adc_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ +/* + * tll6527m V1.0 does not support native spi slave selects + * hence DMA mode will not be useful since the ADC needs + * CS to toggle for each sample and cs_change_per_word + * seems to be removed from spi_bfin5xx.c + */ + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) +static struct bfin5xx_spi_chip mmc_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7879) \ + || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE) +static const struct ad7879_platform_data bfin_ad7879_ts_info = { + .model = 7879, /* Model = AD7879 */ + .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ + .pressure_max = 10000, + .pressure_min = 0, + .first_conversion_delay = 3, + /* wait 512us before do a first conversion */ + .acquisition_time = 1, /* 4us acquisition time per sample */ + .median = 2, /* do 8 measurements */ + .averaging = 1, + /* take the average of 4 middle samples */ + .pen_down_acc_interval = 255, /* 9.4 ms */ + .gpio_export = 1, /* configure AUX as GPIO output*/ + .gpio_base = LCD_BACKLIGHT_GPIO, +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \ + || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) +static struct bfin5xx_spi_chip spi_ad7879_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +static struct bfin5xx_spi_chip spidev_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) +static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE) +static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; + +static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; + +#include <linux/spi/mcp23s08.h> +static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { + .chip[0].is_present = true, + .base = 0x30, +}; +static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = { + .chip[2].is_present = true, + .base = 0x38, +}; +#endif + +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) \ + || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 25000000, + /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS, + /* Can be connected to TLL6527M GPIO connector */ + /* Either SPI_ADC or M25P80 FLASH can be installed at a time */ + .platform_data = &bfin_spi_flash_data, + .controller_data = &spi_flash_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_BFIN_SPI_ADC) + || defined(CONFIG_BFIN_SPI_ADC_MODULE) + { + .modalias = "bfin_spi_adc", + /* Name of spi_driver for this device */ + .max_speed_hz = 10000000, + /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS, + /* Framework chip select. */ + .platform_data = NULL, /* No spi_driver specific config */ + .controller_data = &spi_adc_chip_info, + .mode = SPI_MODE_0, + }, +#endif + +#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) + { + .modalias = "mmc_spi", +/* + * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to + * SPI buffer limitations + */ + .max_speed_hz = 10000000, + /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS, + .controller_data = &mmc_spi_chip_info, + .mode = SPI_MODE_0, + }, +#endif +#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \ + || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) + { + .modalias = "ad7879", + .platform_data = &bfin_ad7879_ts_info, + .irq = IRQ_PH14, + .max_speed_hz = 5000000, + /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, + .controller_data = &spi_ad7879_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, +#endif +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + { + .modalias = "spidev", + .max_speed_hz = 10000000, + /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */ + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, + .mode = SPI_CPHA | SPI_CPOL, + .controller_data = &spidev_chip_info, + }, +#endif +#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) + { + .modalias = "bfin-lq035q1-spi", + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, + .controller_data = &lq035q1_spi_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, +#endif +#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE) + { + .modalias = "mcp23s08", + .platform_data = &bfin_mcp23s08_sys_gpio_info, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, + .controller_data = &spi_mcp23s08_sys_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, + { + .modalias = "mcp23s08", + .platform_data = &bfin_mcp23s08_usr_gpio_info, + .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, + .controller_data = &spi_mcp23s08_usr_chip_info, + .mode = SPI_CPHA | SPI_CPOL, + }, +#endif +}; + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* SPI controller data */ +static struct bfin5xx_spi_master bfin_spi0_info = { + .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS, + /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */ + .enable_dma = 1, /* master has the ability to do dma transfer */ + .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, +}; + +/* SPI (0) */ +static struct resource bfin_spi0_resource[] = { + [0] = { + .start = SPI0_REGBASE, + .end = SPI0_REGBASE + 0xFF, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CH_SPI, + .end = CH_SPI, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = IRQ_SPI, + .end = IRQ_SPI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_spi0_device = { + .name = "bfin-spi", + .id = 0, /* Bus number */ + .num_resources = ARRAY_SIZE(bfin_spi0_resource), + .resource = bfin_spi0_resource, + .dev = { + .platform_data = &bfin_spi0_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 +static struct resource bfin_uart0_resources[] = { + { + .start = UART0_THR, + .end = UART0_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART0_ERROR, + .end = IRQ_UART0_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_TX, + .end = CH_UART0_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +unsigned short bfin_uart0_peripherals[] = { + P_UART0_TX, P_UART0_RX, 0 +}; + +static struct platform_device bfin_uart0_device = { + .name = "bfin-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_uart0_resources), + .resource = bfin_uart0_resources, + .dev = { + .platform_data = &bfin_uart0_peripherals, + /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 +static struct resource bfin_uart1_resources[] = { + { + .start = UART1_THR, + .end = UART1_GCTL+2, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_UART1_ERROR, + .end = IRQ_UART1_ERROR, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_TX, + .end = CH_UART1_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX, + .flags = IORESOURCE_DMA, + }, +#ifdef CONFIG_BFIN_UART1_CTSRTS + { /* CTS pin */ + .start = GPIO_PF9, + .end = GPIO_PF9, + .flags = IORESOURCE_IO, + }, + { /* RTS pin */ + .start = GPIO_PF10, + .end = GPIO_PF10, + .flags = IORESOURCE_IO, + }, +#endif +}; + +unsigned short bfin_uart1_peripherals[] = { + P_UART1_TX, P_UART1_RX, 0 +}; + +static struct platform_device bfin_uart1_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart1_resources), + .resource = bfin_uart1_resources, + .dev = { + .platform_data = &bfin_uart1_peripherals, + /* Passed to driver */ + }, +}; +#endif +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 +static struct resource bfin_sir0_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART0_RX, + .end = IRQ_UART0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART0_RX, + .end = CH_UART0_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir0_device = { + .name = "bfin_sir", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sir0_resources), + .resource = bfin_sir0_resources, +}; +#endif +#ifdef CONFIG_BFIN_SIR1 +static struct resource bfin_sir1_resources[] = { + { + .start = 0xFFC02000, + .end = 0xFFC020FF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_UART1_RX, + .end = IRQ_UART1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = CH_UART1_RX, + .end = CH_UART1_RX+1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device bfin_sir1_device = { + .name = "bfin_sir", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sir1_resources), + .resource = bfin_sir1_resources, +}; +#endif +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) +static struct resource bfin_twi0_resource[] = { + [0] = { + .start = TWI0_REGBASE, + .end = TWI0_REGBASE, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TWI, + .end = IRQ_TWI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device i2c_bfin_twi_device = { + .name = "i2c-bfin-twi", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_twi0_resource), + .resource = bfin_twi0_resource, +}; +#endif + +static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("pcf8574_lcd", 0x22), + }, +#endif + +#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) + { + I2C_BOARD_INFO("bfin-adv7393", 0x2B), + }, +#endif +#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) \ + || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE) + { + I2C_BOARD_INFO("ad7879", 0x2C), + .irq = IRQ_PH14, + .platform_data = (void *)&bfin_ad7879_ts_info, + }, +#endif +#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE) + { + I2C_BOARD_INFO("ssm2602", 0x1b), + }, +#endif + { + I2C_BOARD_INFO("adm1192", 0x2e), + }, + + { + I2C_BOARD_INFO("ltc3576", 0x09), + }, +#if defined(CONFIG_INPUT_ADXL34X_I2C) \ + || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) + { + I2C_BOARD_INFO("adxl34x", 0x53), + .irq = IRQ_PH13, + .platform_data = (void *)&adxl345_info, + }, +#endif +}; + +#if defined(CONFIG_SERIAL_BFIN_SPORT) \ + || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART +static struct resource bfin_sport0_uart_resources[] = { + { + .start = SPORT0_TCR1, + .end = SPORT0_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT0_RX, + .end = IRQ_SPORT0_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT0_ERROR, + .end = IRQ_SPORT0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +unsigned short bfin_sport0_peripherals[] = { + P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, + P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0 +}; + +static struct platform_device bfin_sport0_uart_device = { + .name = "bfin-sport-uart", + .id = 0, + .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), + .resource = bfin_sport0_uart_resources, + .dev = { + .platform_data = &bfin_sport0_peripherals, + /* Passed to driver */ + }, +}; +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART +static struct resource bfin_sport1_uart_resources[] = { + { + .start = SPORT1_TCR1, + .end = SPORT1_MRCS3+4, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_SPORT1_RX, + .end = IRQ_SPORT1_RX+1, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_SPORT1_ERROR, + .end = IRQ_SPORT1_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +unsigned short bfin_sport1_peripherals[] = { + P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, + P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0 +}; + +static struct platform_device bfin_sport1_uart_device = { + .name = "bfin-sport-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), + .resource = bfin_sport1_uart_resources, + .dev = { + .platform_data = &bfin_sport1_peripherals, + /* Passed to driver */ + }, +}; +#endif +#endif + +static const unsigned int cclk_vlev_datasheet[] = { + VRPAIR(VLEV_100, 400000000), + VRPAIR(VLEV_105, 426000000), + VRPAIR(VLEV_110, 500000000), + VRPAIR(VLEV_115, 533000000), + VRPAIR(VLEV_120, 600000000), +}; + +static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { + .tuple_tab = cclk_vlev_datasheet, + .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), + .vr_settling_time = 25 /* us */, +}; + +static struct platform_device bfin_dpmc = { + .name = "bfin dpmc", + .dev = { + .platform_data = &bfin_dmpc_vreg_data, + }, +}; + +static struct platform_device *tll6527m_devices[] __initdata = { + + &bfin_dpmc, + +#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) + &rtc_device, +#endif + +#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) + &musb_device, +#endif + +#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) + &bfin_mii_bus, + &bfin_mac_device, +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &bfin_spi0_device, +#endif + +#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) + &bfin_lq035q1_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) +#ifdef CONFIG_BFIN_SIR0 + &bfin_sir0_device, +#endif +#ifdef CONFIG_BFIN_SIR1 + &bfin_sir1_device, +#endif +#endif + +#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) + &i2c_bfin_twi_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT) \ + || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif + +#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE) + &tll6527m_flash_device, +#endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s, +#endif + +#if defined(CONFIG_GPIO_DECODER) || defined(CONFIG_GPIO_DECODER_MODULE) + &spi_decoded_gpio, +#endif +}; + +static int __init tll6527m_init(void) +{ + printk(KERN_INFO "%s(): registering device resources\n", __func__); + i2c_register_board_info(0, bfin_i2c_board_info, + ARRAY_SIZE(bfin_i2c_board_info)); + platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices)); + spi_register_board_info(bfin_spi_board_info, + ARRAY_SIZE(bfin_spi_board_info)); + return 0; +} + +arch_initcall(tll6527m_init); + +static struct platform_device *tll6527m_early_devices[] __initdata = { +#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) +#ifdef CONFIG_SERIAL_BFIN_UART0 + &bfin_uart0_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_UART1 + &bfin_uart1_device, +#endif +#endif + +#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) +#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART + &bfin_sport0_uart_device, +#endif +#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART + &bfin_sport1_uart_device, +#endif +#endif +}; + +void __init native_machine_early_platform_add_devices(void) +{ + printk(KERN_INFO "register early platform devices\n"); + early_platform_add_devices(tll6527m_early_devices, + ARRAY_SIZE(tll6527m_early_devices)); +} + +void native_machine_restart(char *cmd) +{ + /* workaround reboot hang when booting from SPI */ + if ((bfin_read_SYSCR() & 0x7) == 0x3) + bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); +} + +void bfin_get_ether_addr(char *addr) +{ + /* the MAC is stored in OTP memory page 0xDF */ + u32 ret; + u64 otp_mac; + u32 (*otp_read)(u32 page, u32 flags, + u64 *page_content) = (void *)0xEF00001A; + + ret = otp_read(0xDF, 0x00, &otp_mac); + if (!(ret & 0x1)) { + char *otp_mac_p = (char *)&otp_mac; + for (ret = 0; ret < 6; ++ret) + addr[ret] = otp_mac_p[5 - ret]; + } +} +EXPORT_SYMBOL(bfin_get_ether_addr); diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 11fb27bc427..3048b52bf46 100644 --- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -279,14 +279,14 @@ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) -#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) -#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) -#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) -#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) -#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) -#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) -#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) +#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) +#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val) +#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) +#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val) #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) @@ -334,14 +334,14 @@ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) -#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) -#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) -#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) -#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) -#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) -#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) -#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) +#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) +#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) +#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val) +#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) +#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val) #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 3e000756aac..09475034c6a 100644 --- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h @@ -749,51 +749,6 @@ #define FFE 0x20 /* Force Framing Error On Transmit */ -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c index 175371af069..2ce7b16faee 100644 --- a/arch/blackfin/mach-bf533/boards/H8606.c +++ b/arch/blackfin/mach-bf533/boards/H8606.c @@ -171,7 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -206,12 +206,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 16, .bus_num = 1, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -347,6 +347,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = { .membase = (void *)0x20200000, .mapbase = 0x20200000, .irq = IRQ_PF8, + .irqflags = IRQF_TRIGGER_HIGH, .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, .iotype = UPIO_MEM, .regshift = 1, @@ -355,6 +356,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = { .membase = (void *)0x20200010, .mapbase = 0x20200010, .irq = IRQ_PF8, + .irqflags = IRQF_TRIGGER_HIGH, .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE, .iotype = UPIO_MEM, .regshift = 1, diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 84a06f677df..20c102285be 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c @@ -368,8 +368,8 @@ static struct platform_device bfin_device_gpiokeys = { #include <linux/i2c-gpio.h> static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 8, - .scl_pin = 9, + .sda_pin = GPIO_PF8, + .scl_pin = GPIO_PF9, .sda_is_open_drain = 0, .scl_is_open_drain = 0, .udelay = 40, diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index fdcde61906d..adbe62a81e2 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c @@ -71,7 +71,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -110,12 +110,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -400,7 +400,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF4, .end = IRQ_PF4, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c index 739773cb7fc..a1cb8e7c101 100644 --- a/arch/blackfin/mach-bf533/boards/ezkit.c +++ b/arch/blackfin/mach-bf533/boards/ezkit.c @@ -222,7 +222,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -261,12 +261,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -422,8 +422,8 @@ static struct platform_device bfin_device_gpiokeys = { #include <linux/i2c-gpio.h> static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 1, - .scl_pin = 0, + .sda_pin = GPIO_PF1, + .scl_pin = GPIO_PF0, .sda_is_open_drain = 0, .scl_is_open_drain = 0, .udelay = 40, diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index b8474cac6b0..5ba4b02a12e 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c @@ -232,7 +232,7 @@ static struct resource isp1362_hcd_resources[] = { },{ .start = IRQ_PF11, .end = IRQ_PF11, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c index 29c219eff2f..b3b1cdea270 100644 --- a/arch/blackfin/mach-bf533/boards/stamp.c +++ b/arch/blackfin/mach-bf533/boards/stamp.c @@ -185,7 +185,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -252,13 +252,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, + .platform_data = "ad1836", /* only includes chip name for the moment */ .controller_data = &ad1836_spi_chip_info, + .mode = SPI_MODE_3, }, #endif @@ -495,8 +497,8 @@ static struct platform_device bfin_device_gpiokeys = { #include <linux/i2c-gpio.h> static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 2, - .scl_pin = 3, + .sda_pin = GPIO_PF2, + .scl_pin = GPIO_PF3, .sda_is_open_drain = 0, .scl_is_open_drain = 0, .udelay = 40, @@ -534,6 +536,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { I2C_BOARD_INFO("bfin-adv7393", 0x2B), }, #endif +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("ad5252", 0x2f), + }, +#endif }; static const unsigned int cclk_vlev_datasheet[] = diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 04acf1ed10f..3adb0b44e59 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -681,76 +681,6 @@ #define PF14_P 14 #define PF15_P 15 -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - -/* SPIx_FLG Masks */ -#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig index d81224f9d72..08b2b343cce 100644 --- a/arch/blackfin/mach-bf537/Kconfig +++ b/arch/blackfin/mach-bf537/Kconfig @@ -14,8 +14,8 @@ config IRQ_DMA_ERROR int "IRQ_DMA_ERROR Generic" default 7 config IRQ_ERROR - int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" - default 7 + int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1" + default 11 config IRQ_RTC int "IRQ_RTC" default 8 diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c index d35fc5fe4c2..e2e7be40ef4 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c @@ -73,7 +73,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -112,12 +112,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -229,7 +229,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c index d464ad5b72b..752c833f7ca 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c @@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 812e8f99160..6b03808800a 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c @@ -175,8 +175,8 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -238,13 +238,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 68a27bccc7d..c9e0e85629b 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -35,12 +35,10 @@ #include <asm/reboot.h> #include <asm/portmux.h> #include <asm/dpmc.h> -#ifdef CONFIG_REGULATOR_ADP_SWITCH -#include <linux/regulator/adp_switch.h> -#endif -#ifdef CONFIG_REGULATOR_AD5398 -#include <linux/regulator/ad5398.h> +#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE +#include <linux/regulator/fixed.h> #endif +#include <linux/regulator/machine.h> #include <linux/regulator/consumer.h> #include <linux/regulator/userspace-consumer.h> @@ -264,7 +262,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF3, .end = IRQ_PF3, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -418,7 +416,7 @@ static struct platform_nand_data bfin_plat_nand_data = { static struct resource bfin_plat_nand_resources = { .start = 0x20212000, .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, + .flags = IORESOURCE_MEM, }; static struct platform_device bfin_async_nand_device = { @@ -545,6 +543,14 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = { }; #endif +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \ + || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) +static struct bfin5xx_spi_chip adav801_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) #include <linux/input/ad714x.h> static struct bfin5xx_spi_chip ad7147_spi_chip_info = { @@ -693,6 +699,65 @@ static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { }; #endif +#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE) +static struct bfin5xx_spi_chip ad7314_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE) +static unsigned short ad7816_platform_data[] = { + GPIO_PF4, /* rdwr_pin */ + GPIO_PF5, /* convert_pin */ + GPIO_PF7, /* busy_pin */ + 0, +}; + +static struct bfin5xx_spi_chip ad7816_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE) +static unsigned long adt7310_platform_data[3] = { +/* INT bound temperature alarm event. line 1 */ + IRQ_PG4, IRQF_TRIGGER_LOW, +/* CT bound temperature alarm event irq_flags. line 0 */ + IRQF_TRIGGER_LOW, +}; + +static struct bfin5xx_spi_chip adt7310_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + +#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE) +static unsigned short ad7298_platform_data[] = { + GPIO_PF7, /* busy_pin */ + 0, +}; + +static struct bfin5xx_spi_chip ad7298_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 16, +}; +#endif + +#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) +static unsigned long adt7316_spi_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; + +static struct bfin5xx_spi_chip adt7316_spi_chip_info = { + .enable_dma = 0, + .bits_per_word = 8, +}; +#endif + #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) #define MMC_SPI_CARD_DETECT_INT IRQ_PF5 @@ -824,14 +889,12 @@ static struct bfin5xx_spi_chip lq035q1_spi_chip_info = { static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { .enable_dma = 1, .bits_per_word = 8, - .cs_gpio = GPIO_PF10, }; #endif #if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) static struct bfin5xx_spi_chip adf7021_spi_chip_info = { .bits_per_word = 16, - .cs_gpio = GPIO_PF10, }; #include <linux/spi/adf702x.h> @@ -938,6 +1001,13 @@ static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { }; #endif +#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE) +static struct bfin5xx_spi_chip spi_ad7476_chip_info = { + .enable_dma = 0, /* use dma transfer with this chip*/ + .bits_per_word = 8, +}; +#endif + static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -982,7 +1052,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = 4,/* CONFIG_SND_BLACKFIN_SPI_PFBIT */ + .chip_select = 4, .platform_data = "ad1836", /* only includes chip name for the moment */ .controller_data = &ad1836_spi_chip_info, .mode = SPI_MODE_3, @@ -1000,6 +1070,17 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) + { + .modalias = "adav80x", + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, + .controller_data = &adav801_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + #if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) { .modalias = "ad714x_captouch", @@ -1018,6 +1099,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "ad2s90", .bus_num = 0, .chip_select = 3, /* change it for your board */ + .mode = SPI_MODE_3, .platform_data = NULL, .controller_data = &ad2s90_spi_chip_info, }, @@ -1044,6 +1126,67 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif +#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE) + { + .modalias = "ad7314", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .controller_data = &ad7314_spi_chip_info, + .mode = SPI_MODE_1, + }, +#endif + +#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE) + { + .modalias = "ad7818", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7816_platform_data, + .controller_data = &ad7816_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE) + { + .modalias = "adt7310", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* CT alarm event. Line 0 */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7310_platform_data, + .controller_data = &adt7310_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE) + { + .modalias = "ad7298", + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = ad7298_platform_data, + .controller_data = &ad7298_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + +#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) + { + .modalias = "adt7316", + .max_speed_hz = 1000000, + .irq = IRQ_PG5, /* interrupt line */ + .bus_num = 0, + .chip_select = 4, /* CS, change it for your board */ + .platform_data = adt7316_spi_data, + .controller_data = &adt7316_spi_chip_info, + .mode = SPI_MODE_3, + }, +#endif + #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) { .modalias = "mmc_spi", @@ -1103,7 +1246,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ .irq = IRQ_PF6, .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ .controller_data = &enc28j60_spi_chip_info, .mode = SPI_MODE_0, }, @@ -1125,7 +1268,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .modalias = "adf702x", .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ + .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ .controller_data = &adf7021_spi_chip_info, .platform_data = &adf7021_platform_data, .mode = SPI_MODE_0, @@ -1143,12 +1286,239 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_0, }, #endif +#if defined(CONFIG_AD7476) \ + || defined(CONFIG_AD7476_MODULE) + { + .modalias = "ad7476", /* Name of spi_driver for this device */ + .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Framework bus number */ + .chip_select = 1, /* Framework chip select. */ + .platform_data = NULL, /* No spi_driver specific config */ + .controller_data = &spi_ad7476_chip_info, + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADE7753) \ + || defined(CONFIG_ADE7753_MODULE) + { + .modalias = "ade7753", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7754) \ + || defined(CONFIG_ADE7754_MODULE) + { + .modalias = "ade7754", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7758) \ + || defined(CONFIG_ADE7758_MODULE) + { + .modalias = "ade7758", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7759) \ + || defined(CONFIG_ADE7759_MODULE) + { + .modalias = "ade7759", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADE7854_SPI) \ + || defined(CONFIG_ADE7854_SPI_MODULE) + { + .modalias = "ade7854", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16060) \ + || defined(CONFIG_ADIS16060_MODULE) + { + .modalias = "adis16060_r", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_0, + }, + { + .modalias = "adis16060_w", + .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 2, /* CS for write, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_1, + }, +#endif +#if defined(CONFIG_ADIS16130) \ + || defined(CONFIG_ADIS16130_MODULE) + { + .modalias = "adis16130", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS for read, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16201) \ + || defined(CONFIG_ADIS16201_MODULE) + { + .modalias = "adis16201", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16203) \ + || defined(CONFIG_ADIS16203_MODULE) + { + .modalias = "adis16203", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16204) \ + || defined(CONFIG_ADIS16204_MODULE) + { + .modalias = "adis16204", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16209) \ + || defined(CONFIG_ADIS16209_MODULE) + { + .modalias = "adis16209", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16220) \ + || defined(CONFIG_ADIS16220_MODULE) + { + .modalias = "adis16220", + .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16240) \ + || defined(CONFIG_ADIS16240_MODULE) + { + .modalias = "adis16240", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16260) \ + || defined(CONFIG_ADIS16260_MODULE) + { + .modalias = "adis16260", + .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16261) \ + || defined(CONFIG_ADIS16261_MODULE) + { + .modalias = "adis16261", + .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif +#if defined(CONFIG_ADIS16300) \ + || defined(CONFIG_ADIS16300_MODULE) + { + .modalias = "adis16300", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16350) \ + || defined(CONFIG_ADIS16350_MODULE) + { + .modalias = "adis16364", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 5, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + .irq = IRQ_PF4, + }, +#endif +#if defined(CONFIG_ADIS16400) \ + || defined(CONFIG_ADIS16400_MODULE) + { + .modalias = "adis16400", + .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 1, /* CS, change it for your board */ + .platform_data = NULL, /* No spi_driver specific config */ + .mode = SPI_MODE_3, + }, +#endif }; #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) /* SPI controller data */ static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, + .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -1773,12 +2143,6 @@ static struct regulator_init_data ad5398_regulator_data = { .consumer_supplies = &ad5398_consumer, }; -static struct ad5398_platform_data ad5398_i2c_platform_data = { - .current_bits = 10, - .current_offset = 4, - .regulator_data = &ad5398_regulator_data, -}; - #if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \ defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE) static struct platform_device ad5398_virt_consumer_device = { @@ -1811,7 +2175,34 @@ static struct platform_device ad5398_userspace_consumer_device = { #endif #endif +#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7410_platform_data[2] = { + IRQ_PG4, IRQF_TRIGGER_LOW, +}; +#endif + +#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE) +/* INT bound temperature alarm event. line 1 */ +static unsigned long adt7316_i2c_data[2] = { + IRQF_TRIGGER_LOW, /* interrupt flags */ + GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */ +}; +#endif + static struct i2c_board_info __initdata bfin_i2c_board_info[] = { +#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE) + { + I2C_BOARD_INFO("ad1937", 0x04), + }, +#endif + +#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE) + { + I2C_BOARD_INFO("adav803", 0x10), + }, +#endif + #if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) { I2C_BOARD_INFO("ad7142_captouch", 0x2C), @@ -1843,12 +2234,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { { I2C_BOARD_INFO("ad7414", 0x9), .irq = IRQ_PG5, - /* - * platform_data pointer is borrwoed by the driver to - * store custimer defined IRQ ALART level mode. - * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. - */ - .platform_data = (void *)IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_LOW, }, #endif @@ -1856,12 +2242,56 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { { I2C_BOARD_INFO("ad7417", 0xb), .irq = IRQ_PG5, - /* - * platform_data pointer is borrwoed by the driver to - * store custimer defined IRQ ALART level mode. - * only IRQF_TRIGGER_HIGH and IRQF_TRIGGER_LOW are valid. - */ - .platform_data = (void *)IRQF_TRIGGER_LOW, + .irq_flags = IRQF_TRIGGER_LOW, + .platform_data = (void *)GPIO_PF4, + }, +#endif + +#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE) + { + I2C_BOARD_INFO("ade7854", 0x38), + }, +#endif + +#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE) + { + I2C_BOARD_INFO("adt75", 0x9), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE) + { + I2C_BOARD_INFO("adt7408", 0x18), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE) + { + I2C_BOARD_INFO("adt7410", 0x48), + /* CT critical temperature event. line 0 */ + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + .platform_data = (void *)&adt7410_platform_data, + }, +#endif + +#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE) + { + I2C_BOARD_INFO("ad7291", 0x20), + .irq = IRQ_PG5, + .irq_flags = IRQF_TRIGGER_LOW, + }, +#endif + +#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE) + { + I2C_BOARD_INFO("adt7316", 0x48), + .irq = IRQ_PG6, + .platform_data = (void *)&adt7316_i2c_data, }, #endif @@ -1917,7 +2347,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { #endif #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) { - I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), + I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F), }, #endif #if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) @@ -1954,7 +2384,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { #if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE) { I2C_BOARD_INFO("ad5398", 0xC), - .platform_data = (void *)&ad5398_i2c_platform_data, + .platform_data = (void *)&ad5398_regulator_data, }, #endif #if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE) @@ -1963,6 +2393,16 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { .platform_data = (void *)&adp8860_pdata, }, #endif +#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE) + { + I2C_BOARD_INFO("adau1373", 0x1A), + }, +#endif +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("ad5252", 0x2e), + }, +#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -2147,50 +2587,38 @@ static struct platform_device bfin_ac97 = { }; #endif -#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) -#define REGULATOR_ADP122 "adp122" -#define REGULATOR_ADP150 "adp150" +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) +#define REGULATOR_ADP122 "adp122" +#define REGULATOR_ADP122_UV 2500000 static struct regulator_consumer_supply adp122_consumers = { .supply = REGULATOR_ADP122, }; -static struct regulator_consumer_supply adp150_consumers = { - .supply = REGULATOR_ADP150, -}; - -static struct regulator_init_data adp_switch_regulator_data[] = { - { - .constraints = { - .name = REGULATOR_ADP122, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .min_uA = 0, - .max_uA = 300000, - }, - .num_consumer_supplies = 1, /* only 1 */ - .consumer_supplies = &adp122_consumers, - .driver_data = (void *)GPIO_PF2, /* gpio port only */ - }, - { - .constraints = { - .name = REGULATOR_ADP150, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .min_uA = 0, - .max_uA = 150000, - }, - .num_consumer_supplies = 1, /* only 1 */ - .consumer_supplies = &adp150_consumers, - .driver_data = (void *)GPIO_PF3, /* gpio port only */ +static struct regulator_init_data adp_switch_regulator_data = { + .constraints = { + .name = REGULATOR_ADP122, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .min_uV = REGULATOR_ADP122_UV, + .max_uV = REGULATOR_ADP122_UV, + .min_uA = 0, + .max_uA = 300000, }, + .num_consumer_supplies = 1, /* only 1 */ + .consumer_supplies = &adp122_consumers, }; -static struct adp_switch_platform_data adp_switch_pdata = { - .regulator_num = ARRAY_SIZE(adp_switch_regulator_data), - .regulator_data = adp_switch_regulator_data, +static struct fixed_voltage_config adp_switch_pdata = { + .supply_name = REGULATOR_ADP122, + .microvolts = REGULATOR_ADP122_UV, + .gpio = GPIO_PF2, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &adp_switch_regulator_data, }; static struct platform_device adp_switch_device = { - .name = "adp_switch", + .name = "reg-fixed-voltage", .id = 0, .dev = { .platform_data = &adp_switch_pdata, @@ -2216,27 +2644,26 @@ static struct platform_device adp122_userspace_consumer_device = { .platform_data = &adp122_userspace_comsumer_data, }, }; +#endif +#endif -static struct regulator_bulk_data adp150_bulk_data = { - .supply = REGULATOR_ADP150, -}; +#if defined(CONFIG_IIO_GPIO_TRIGGER) || \ + defined(CONFIG_IIO_GPIO_TRIGGER_MODULE) -static struct regulator_userspace_consumer_data adp150_userspace_comsumer_data = { - .name = REGULATOR_ADP150, - .num_supplies = 1, - .supplies = &adp150_bulk_data, +static struct resource iio_gpio_trigger_resources[] = { + [0] = { + .start = IRQ_PF5, + .end = IRQ_PF5, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, + }, }; -static struct platform_device adp150_userspace_consumer_device = { - .name = "reg-userspace-consumer", - .id = 1, - .dev = { - .platform_data = &adp150_userspace_comsumer_data, - }, +static struct platform_device iio_gpio_trigger = { + .name = "iio_gpio_trigger", + .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources), + .resource = iio_gpio_trigger_resources, }; #endif -#endif - static struct platform_device *stamp_devices[] __initdata = { @@ -2369,14 +2796,18 @@ static struct platform_device *stamp_devices[] __initdata = { #endif #endif -#if defined(CONFIG_REGULATOR_ADP_SWITCH) || defined(CONFIG_REGULATOR_ADP_SWITCH_MODULE) +#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) &adp_switch_device, #if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \ defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE) &adp122_userspace_consumer_device, - &adp150_userspace_consumer_device, #endif #endif + +#if defined(CONFIG_IIO_GPIO_TRIGGER) || \ + defined(CONFIG_IIO_GPIO_TRIGGER_MODULE) + &iio_gpio_trigger, +#endif }; static int __init stamp_init(void) diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 4f0a2e72ce4..a4d62b5fc7b 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c @@ -74,7 +74,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -113,12 +113,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -230,7 +230,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PG15, .end = IRQ_PG15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h index 6f56907a18c..0323e6bacda 100644 --- a/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -1071,50 +1071,6 @@ #define FPE 0x10 /* Force Parity Error On Transmit */ #define FFE 0x20 /* Force Framing Error On Transmit */ -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/ -/* SPI_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPI_FLG Masks */ -#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ -#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ -#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ -#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ -#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ -#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ -#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ -#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ - -/* SPI_STAT Masks */ -#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ -#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ -#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ -#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ -#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ - /* **************** GENERAL PURPOSE TIMER MASKS **********************/ /* TIMER_ENABLE Masks */ #define TIMEN0 0x0001 /* Enable Timer 0 */ diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c index 1a1f65855b0..c6fb0a52f84 100644 --- a/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/arch/blackfin/mach-bf538/boards/ezkit.c @@ -695,7 +695,7 @@ static struct platform_device bf538_spi_master0 = { }; static struct bfin5xx_spi_master bf538_spi_master_info1 = { - .num_chipselect = 8, + .num_chipselect = 2, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; @@ -711,7 +711,7 @@ static struct platform_device bf538_spi_master1 = { }; static struct bfin5xx_spi_master bf538_spi_master_info2 = { - .num_chipselect = 8, + .num_chipselect = 2, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, }; diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h index fe43062b497..7a8ac5f4420 100644 --- a/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -32,6 +32,7 @@ /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ #define SYSCR 0xFFC00104 /* System Configuration registe */ +#define SIC_RVECT 0xFFC00108 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ @@ -1894,78 +1895,6 @@ #define PE14_P 0xE #define PE15_P 0xF - -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ -/* SPIx_CTL Masks */ -#define TIMOD 0x0003 /* Transfer Initiate Mode */ -#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ -#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ -#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ -#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ -#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ -#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ -#define PSSE 0x0010 /* Slave-Select Input Enable */ -#define EMISO 0x0020 /* Enable MISO As Output */ -#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ -#define LSBF 0x0200 /* LSB First */ -#define CPHA 0x0400 /* Clock Phase */ -#define CPOL 0x0800 /* Clock Polarity */ -#define MSTR 0x1000 /* Master/Slave* */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define SPE 0x4000 /* SPI Enable */ - -/* SPIx_FLG Masks */ -#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ - -#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPIx_FLG Bit Positions */ -#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPIx_STAT Masks */ -#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */ - -/* SPIx_FLG Masks */ -#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ -#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ -#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ -#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ -#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ -#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ -#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ - - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* EBIU_AMGCTL Masks */ #define AMCKEN 0x0001 /* Enable CLKOUT */ diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c index 0c38eec9ade..f0c0eef95ba 100644 --- a/arch/blackfin/mach-bf548/boards/cm_bf548.c +++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c @@ -753,6 +753,44 @@ static struct platform_device bf54x_sdh_device = { }; #endif +#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) +unsigned short bfin_can_peripherals[] = { + P_CAN0_RX, P_CAN0_TX, 0 +}; + +static struct resource bfin_can_resources[] = { + { + .start = 0xFFC02A00, + .end = 0xFFC02FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CAN0_RX, + .end = IRQ_CAN0_RX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN0_TX, + .end = IRQ_CAN0_TX, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CAN0_ERROR, + .end = IRQ_CAN0_ERROR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bfin_can_device = { + .name = "bfin_can", + .num_resources = ARRAY_SIZE(bfin_can_resources), + .resource = bfin_can_resources, + .dev = { + .platform_data = &bfin_can_peripherals, /* Passed to driver */ + }, +}; +#endif + #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) static struct mtd_partition para_partitions[] = { { @@ -928,7 +966,7 @@ static struct resource bfin_spi1_resource[] = { /* SPI controller data */ static struct bfin5xx_spi_master bf54x_spi_master_info0 = { - .num_chipselect = 3, + .num_chipselect = 4, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -944,7 +982,7 @@ static struct platform_device bf54x_spi_master0 = { }; static struct bfin5xx_spi_master bf54x_spi_master_info1 = { - .num_chipselect = 3, + .num_chipselect = 4, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; @@ -1152,6 +1190,11 @@ static struct platform_device *cm_bf548_devices[] __initdata = { #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) ¶_flash_device, #endif + +#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) + &bfin_can_device, +#endif + }; static int __init cm_bf548_init(void) diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c index 56682a36e42..216e26999af 100644 --- a/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/arch/blackfin/mach-bf548/boards/ezkit.c @@ -837,8 +837,12 @@ static struct platform_device bfin_atapi_device = { #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) static struct mtd_partition partition_info[] = { { - .name = "linux kernel(nand)", + .name = "bootloader(nand)", .offset = 0, + .size = 0x80000, + }, { + .name = "linux kernel(nand)", + .offset = MTDPART_OFS_APPEND, .size = 4 * 1024 * 1024, }, { @@ -901,7 +905,7 @@ static struct platform_device bf54x_sdh_device = { static struct mtd_partition ezkit_partitions[] = { { .name = "bootloader(nor)", - .size = 0x40000, + .size = 0x80000, .offset = 0, }, { .name = "linux kernel(nor)", @@ -943,7 +947,7 @@ static struct platform_device ezkit_flash_device = { static struct mtd_partition bfin_spi_flash_partitions[] = { { .name = "bootloader(spi)", - .size = 0x00040000, + .size = 0x00080000, .offset = 0, .mask_flags = MTD_CAP_ROM }, { @@ -966,8 +970,8 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -1023,13 +1027,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_3, }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 1, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -1107,7 +1111,7 @@ static struct resource bfin_spi1_resource[] = { /* SPI controller data */ static struct bfin5xx_spi_master bf54x_spi_master_info0 = { - .num_chipselect = 3, + .num_chipselect = 4, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; @@ -1123,7 +1127,7 @@ static struct platform_device bf54x_spi_master0 = { }; static struct bfin5xx_spi_master bf54x_spi_master_info1 = { - .num_chipselect = 3, + .num_chipselect = 4, .enable_dma = 1, /* master has the ability to do dma transfer */ .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; @@ -1206,6 +1210,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { .platform_data = (void *)&adxl34x_info, }, #endif +#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) + { + I2C_BOARD_INFO("ad5252", 0x2f), + }, +#endif }; #endif diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c index 039a6d9d38f..888b9cc0b82 100644 --- a/arch/blackfin/mach-bf548/dma.c +++ b/arch/blackfin/mach-bf548/dma.c @@ -63,6 +63,7 @@ int channel2irq(unsigned int channel) break; case CH_SPORT1_TX: ret_irq = IRQ_SPORT1_TX; + break; case CH_SPI0: ret_irq = IRQ_SPI0; break; diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 0c16067df4f..deaf5d6542d 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -40,6 +40,8 @@ /* SIC Registers */ +#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 7866197f548..78f91103f17 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -35,6 +35,7 @@ /* SIC Registers */ +#define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ @@ -2061,56 +2062,6 @@ #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ -/* Bit masks for SPIx_BAUD */ - -#define SPI_BAUD 0xffff /* Baud Rate */ - -/* Bit masks for SPIx_CTL */ - -#define SPE 0x4000 /* SPI Enable */ -#define WOM 0x2000 /* Write Open Drain Master */ -#define MSTR 0x1000 /* Master Mode */ -#define CPOL 0x800 /* Clock Polarity */ -#define CPHA 0x400 /* Clock Phase */ -#define LSBF 0x200 /* LSB First */ -#define SIZE 0x100 /* Size of Words */ -#define EMISO 0x20 /* Enable MISO Output */ -#define PSSE 0x10 /* Slave-Select Enable */ -#define GM 0x8 /* Get More Data */ -#define SZ 0x4 /* Send Zero */ -#define TIMOD 0x3 /* Transfer Initiation Mode */ - -/* Bit masks for SPIx_FLG */ - -#define FLS1 0x2 /* Slave Select Enable 1 */ -#define FLS2 0x4 /* Slave Select Enable 2 */ -#define FLS3 0x8 /* Slave Select Enable 3 */ -#define FLG1 0x200 /* Slave Select Value 1 */ -#define FLG2 0x400 /* Slave Select Value 2 */ -#define FLG3 0x800 /* Slave Select Value 3 */ - -/* Bit masks for SPIx_STAT */ - -#define TXCOL 0x40 /* Transmit Collision Error */ -#define RXS 0x20 /* RDBR Data Buffer Status */ -#define RBSY 0x10 /* Receive Error */ -#define TXS 0x8 /* TDBR Data Buffer Status */ -#define TXE 0x4 /* Transmission Error */ -#define MODF 0x2 /* Mode Fault Error */ -#define SPIF 0x1 /* SPI Finished */ - -/* Bit masks for SPIx_TDBR */ - -#define TDBR 0xffff /* Transmit Data Buffer */ - -/* Bit masks for SPIx_RDBR */ - -#define RDBR 0xffff /* Receive Data Buffer */ - -/* Bit masks for SPIx_SHADOW */ - -#define SHADOW 0xffff /* RDBR Shadow */ - /* ************************************************ */ /* The TWI bit masks fields are from the ADSP-BF538 */ /* and they have not been verified as the final */ diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c index 35b6d124c1e..0b1c20f14fe 100644 --- a/arch/blackfin/mach-bf561/boards/acvilon.c +++ b/arch/blackfin/mach-bf561/boards/acvilon.c @@ -302,7 +302,7 @@ static struct platform_nand_data bfin_plat_nand_data = { static struct resource bfin_plat_nand_resources = { .start = 0x24000000, .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, + .flags = IORESOURCE_MEM, }; static struct platform_device bfin_async_nand_device = { diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index e127aedc1d7..087b6b05cc7 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c @@ -72,7 +72,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -111,12 +111,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, .controller_data = &ad1836_spi_chip_info, }, #endif @@ -278,7 +278,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF47, .end = IRQ_PF47, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c index 9b93e2f9579..ab7a487975f 100644 --- a/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/arch/blackfin/mach-bf561/boards/ezkit.c @@ -14,6 +14,7 @@ #include <linux/spi/spi.h> #include <linux/irq.h> #include <linux/interrupt.h> +#include <linux/delay.h> #include <asm/dma.h> #include <asm/bfin5xx_spi.h> #include <asm/portmux.h> @@ -74,7 +75,7 @@ static struct resource isp1362_hcd_resources[] = { }, { .start = IRQ_PF8, .end = IRQ_PF8, - .flags = IORESOURCE_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, }; @@ -274,8 +275,8 @@ static struct platform_device ezkit_flash_device = { }; #endif -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, @@ -328,14 +329,16 @@ static struct platform_device bfin_spi0_device = { #endif static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_SND_BLACKFIN_AD183X) \ - || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE) +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ + || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) { - .modalias = "ad1836", + .modalias = "ad183x", .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ .bus_num = 0, - .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, + .chip_select = 4, + .platform_data = "ad1836", /* only includes chip name for the moment */ .controller_data = &ad1836_spi_chip_info, + .mode = SPI_MODE_3, }, #endif #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) @@ -377,8 +380,8 @@ static struct platform_device bfin_device_gpiokeys = { #include <linux/i2c-gpio.h> static struct i2c_gpio_platform_data i2c_gpio_data = { - .sda_pin = 1, - .scl_pin = 0, + .sda_pin = GPIO_PF1, + .scl_pin = GPIO_PF0, .sda_is_open_drain = 0, .scl_is_open_drain = 0, .udelay = 40, @@ -420,6 +423,30 @@ static struct platform_device bfin_dpmc = { }, }; +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) +static struct platform_device bfin_i2s = { + .name = "bfin-i2s", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) +static struct platform_device bfin_tdm = { + .name = "bfin-tdm", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) +static struct platform_device bfin_ac97 = { + .name = "bfin-ac97", + .id = CONFIG_SND_BF5XX_SPORT_NUM, + /* TODO: add platform data here */ +}; +#endif + static struct platform_device *ezkit_devices[] __initdata = { &bfin_dpmc, @@ -467,6 +494,18 @@ static struct platform_device *ezkit_devices[] __initdata = { #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) &ezkit_flash_device, #endif + +#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) + &bfin_i2s, +#endif + +#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) + &bfin_tdm, +#endif + +#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) + &bfin_ac97, +#endif }; static int __init ezkit_init(void) @@ -484,6 +523,17 @@ static int __init ezkit_init(void) SSYNC(); #endif +#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) + bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15)); + bfin_write_FIO0_FLAG_S(1 << 15); + SSYNC(); + /* + * This initialization lasts for approximately 4500 MCLKs. + * MCLK = 12.288MHz + */ + udelay(400); +#endif + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); return 0; } diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index c6a4c8f2d37..78ecb50bafc 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -18,9 +18,9 @@ #include <linux/miscdevice.h> #include <linux/module.h> -#define CMD_COREB_START 2 -#define CMD_COREB_STOP 3 -#define CMD_COREB_RESET 4 +#define CMD_COREB_START _IO('b', 0) +#define CMD_COREB_STOP _IO('b', 1) +#define CMD_COREB_RESET _IO('b', 2) static long coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) @@ -29,10 +29,10 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) switch (cmd) { case CMD_COREB_START: - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020); + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); break; case CMD_COREB_STOP: - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020); + bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); break; case CMD_COREB_RESET: @@ -74,3 +74,4 @@ module_exit(bf561_coreb_exit); MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); MODULE_DESCRIPTION("BF561 Core B Support"); +MODULE_LICENSE("GPL"); diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 67d6bdcd3fa..6c7dc58c018 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -24,29 +24,16 @@ #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) -#define SIC_IWR0 SICA_IWR0 -#define SIC_IWR1 SICA_IWR1 -#define SIC_IAR0 SICA_IAR0 -#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 -#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 -#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0 -#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1 - -#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0 -#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1 -#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0 -#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1 -#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0 -#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1 - -#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) -#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) -#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) -#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) -#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) -#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) -#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) -#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) +/* Weird muxer funcs which pick SIC regs from IMASK base */ +#define __SIC_MUX(base, x) ((base) + ((x) << 2)) +#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x)) +#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val) +#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x)) +#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val) +#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x)) +#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val) +#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x)) +#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val) #define BFIN_UART_NR_PORTS 1 diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h index cc0416a5fa0..2bab9915249 100644 --- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h @@ -30,49 +30,41 @@ #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) #define bfin_read_CHIPID() bfin_read32(CHIPID) -/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define bfin_read_SWRST() bfin_read_SICA_SWRST() -#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val) -#define bfin_read_SYSCR() bfin_read_SICA_SYSCR() -#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val) - /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST,val) -#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) -#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR,val) -#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) -#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT,val) -#define bfin_read_SICA_IMASK() bfin_read32(SICA_IMASK) -#define bfin_write_SICA_IMASK(val) bfin_write32(SICA_IMASK,val) -#define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) -#define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0,val) -#define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) -#define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1,val) -#define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) -#define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0,val) -#define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) -#define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1,val) -#define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) -#define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2,val) -#define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) -#define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3,val) -#define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) -#define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4,val) -#define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) -#define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5,val) -#define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) -#define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6,val) -#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) -#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7,val) -#define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) -#define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0,val) -#define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) -#define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1,val) -#define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) -#define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0,val) -#define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) -#define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1,val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST,val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val) /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 2674f009757..79e048d452e 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -28,32 +28,29 @@ #define CHIPID 0xFFC00014 /* Chip ID Register */ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ -#define SWRST SICA_SWRST -#define SYSCR SICA_SYSCR #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) #define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ -#define SICA_SWRST 0xFFC00100 /* Software Reset register */ -#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ -#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ -#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ -#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ -#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ -#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ -#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ -#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ -#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ -#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ -#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ -#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ -#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ -#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ -#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ -#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ -#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ +#define SWRST 0xFFC00100 /* Software Reset register */ +#define SYSCR 0xFFC00104 /* System Reset Configuration register */ +#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ +#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ +#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ +#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ +#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ +#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ +#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ +#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ +#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ #define SICB_SWRST 0xFFC01100 /* reserved */ @@ -1271,63 +1268,6 @@ #define PF14_P 14 #define PF15_P 15 -/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ - -/* SPI_CTL Masks */ -#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ -#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ -#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ -#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ -#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ -#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ -#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ -#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ -#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ -#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ -#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ -#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ - -/* SPI_FLG Masks */ -#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_FLG Bit Positions */ -#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ -#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ -#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ -#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ -#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ -#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ -#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ -#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ - -/* SPI_STAT Masks */ -#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ -#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */ -#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ -#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ -#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ -#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ -#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ - /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ /* AMGCTL Masks */ diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c index b4424172ad9..7ee9262fe13 100644 --- a/arch/blackfin/mach-bf561/ints-priority.c +++ b/arch/blackfin/mach-bf561/ints-priority.c @@ -13,7 +13,7 @@ void __init program_IAR(void) { /* Program the IAR0 Register with the configured priority */ - bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | + bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) | ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) | ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) | ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) | @@ -22,7 +22,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) | ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS)); - bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | + bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) | ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) | ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) | ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) | @@ -31,7 +31,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) | ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS)); - bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | + bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) | ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) | ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) | ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) | @@ -40,7 +40,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) | ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS)); - bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | + bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) | ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) | ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) | ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) | @@ -49,7 +49,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) | ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS)); - bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | + bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) | ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) | ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) | ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) | @@ -58,7 +58,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) | ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS)); - bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | + bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) | ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) | ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) | ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) | @@ -67,7 +67,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) | ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS)); - bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | + bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) | ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) | ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) | ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) | @@ -76,7 +76,7 @@ void __init program_IAR(void) ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) | ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS)); - bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | + bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) | ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) | ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) | ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) | diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 3b9a4bf7dac..f540ed1257d 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -52,19 +52,19 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ void __cpuinit platform_secondary_init(unsigned int cpu) { /* Clone setup for peripheral interrupt sources from CoreA. */ - bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); - bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); + bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0()); + bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1()); SSYNC(); /* Clone setup for IARs from CoreA. */ - bfin_write_SICB_IAR0(bfin_read_SICA_IAR0()); - bfin_write_SICB_IAR1(bfin_read_SICA_IAR1()); - bfin_write_SICB_IAR2(bfin_read_SICA_IAR2()); - bfin_write_SICB_IAR3(bfin_read_SICA_IAR3()); - bfin_write_SICB_IAR4(bfin_read_SICA_IAR4()); - bfin_write_SICB_IAR5(bfin_read_SICA_IAR5()); - bfin_write_SICB_IAR6(bfin_read_SICA_IAR6()); - bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); + bfin_write_SICB_IAR0(bfin_read_SIC_IAR0()); + bfin_write_SICB_IAR1(bfin_read_SIC_IAR1()); + bfin_write_SICB_IAR2(bfin_read_SIC_IAR2()); + bfin_write_SICB_IAR3(bfin_read_SIC_IAR3()); + bfin_write_SICB_IAR4(bfin_read_SIC_IAR4()); + bfin_write_SICB_IAR5(bfin_read_SIC_IAR5()); + bfin_write_SICB_IAR6(bfin_read_SIC_IAR6()); + bfin_write_SICB_IAR7(bfin_read_SIC_IAR7()); bfin_write_SICB_IWR0(IWR_DISABLE_ALL); bfin_write_SICB_IWR1(IWR_DISABLE_ALL); SSYNC(); @@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle spin_lock(&boot_lock); - if ((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0) { + if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT); + bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 5969d86836a..9cfdd49a312 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S @@ -292,13 +292,7 @@ ENTRY(_do_hibernate) #ifdef SIC_IMASK PM_SYS_PUSH(SIC_IMASK) #endif -#ifdef SICA_IMASK0 - PM_SYS_PUSH(SICA_IMASK0) -#endif -#ifdef SICA_IMASK1 - PM_SYS_PUSH(SICA_IMASK1) -#endif -#ifdef SIC_IAR2 +#ifdef SIC_IAR0 PM_SYS_PUSH(SIC_IAR0) PM_SYS_PUSH(SIC_IAR1) PM_SYS_PUSH(SIC_IAR2) @@ -321,17 +315,6 @@ ENTRY(_do_hibernate) PM_SYS_PUSH(SIC_IAR11) #endif -#ifdef SICA_IAR0 - PM_SYS_PUSH(SICA_IAR0) - PM_SYS_PUSH(SICA_IAR1) - PM_SYS_PUSH(SICA_IAR2) - PM_SYS_PUSH(SICA_IAR3) - PM_SYS_PUSH(SICA_IAR4) - PM_SYS_PUSH(SICA_IAR5) - PM_SYS_PUSH(SICA_IAR6) - PM_SYS_PUSH(SICA_IAR7) -#endif - #ifdef SIC_IWR PM_SYS_PUSH(SIC_IWR) #endif @@ -344,12 +327,6 @@ ENTRY(_do_hibernate) #ifdef SIC_IWR2 PM_SYS_PUSH(SIC_IWR2) #endif -#ifdef SICA_IWR0 - PM_SYS_PUSH(SICA_IWR0) -#endif -#ifdef SICA_IWR1 - PM_SYS_PUSH(SICA_IWR1) -#endif #ifdef PINT0_ASSIGN PM_SYS_PUSH(PINT0_MASK_SET) @@ -750,12 +727,6 @@ ENTRY(_do_hibernate) PM_SYS_POP(PINT0_MASK_SET) #endif -#ifdef SICA_IWR1 - PM_SYS_POP(SICA_IWR1) -#endif -#ifdef SICA_IWR0 - PM_SYS_POP(SICA_IWR0) -#endif #ifdef SIC_IWR2 PM_SYS_POP(SIC_IWR2) #endif @@ -769,17 +740,6 @@ ENTRY(_do_hibernate) PM_SYS_POP(SIC_IWR) #endif -#ifdef SICA_IAR0 - PM_SYS_POP(SICA_IAR7) - PM_SYS_POP(SICA_IAR6) - PM_SYS_POP(SICA_IAR5) - PM_SYS_POP(SICA_IAR4) - PM_SYS_POP(SICA_IAR3) - PM_SYS_POP(SICA_IAR2) - PM_SYS_POP(SICA_IAR1) - PM_SYS_POP(SICA_IAR0) -#endif - #ifdef SIC_IAR8 PM_SYS_POP(SIC_IAR11) PM_SYS_POP(SIC_IAR10) @@ -797,17 +757,11 @@ ENTRY(_do_hibernate) #ifdef SIC_IAR3 PM_SYS_POP(SIC_IAR3) #endif -#ifdef SIC_IAR2 +#ifdef SIC_IAR0 PM_SYS_POP(SIC_IAR2) PM_SYS_POP(SIC_IAR1) PM_SYS_POP(SIC_IAR0) #endif -#ifdef SICA_IMASK1 - PM_SYS_POP(SICA_IMASK1) -#endif -#ifdef SICA_IMASK0 - PM_SYS_POP(SICA_IMASK0) -#endif #ifdef SIC_IMASK PM_SYS_POP(SIC_IMASK) #endif diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index af1bffa21dc..2ca915ee181 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S @@ -889,6 +889,66 @@ ENTRY(_ret_from_exception) rts; ENDPROC(_ret_from_exception) +#if defined(CONFIG_PREEMPT) + +ENTRY(_up_to_irq14) +#if ANOMALY_05000281 || ANOMALY_05000461 + r0.l = lo(SAFE_USER_INSTRUCTION); + r0.h = hi(SAFE_USER_INSTRUCTION); + reti = r0; +#endif + +#ifdef CONFIG_DEBUG_HWERR + /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */ + r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); +#else + /* Only enable irq14 interrupt, until we transition to _evt_evt14 */ + r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); +#endif + sti r0; + + p0.l = lo(EVT14); + p0.h = hi(EVT14); + p1.l = _evt_up_evt14; + p1.h = _evt_up_evt14; + [p0] = p1; + csync; + + raise 14; +1: + jump 1b; +ENDPROC(_up_to_irq14) + +ENTRY(_evt_up_evt14) +#ifdef CONFIG_DEBUG_HWERR + r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU); + sti r0; +#else + cli r0; +#endif +#ifdef CONFIG_TRACE_IRQFLAGS + [--sp] = rets; + sp += -12; + call _trace_hardirqs_off; + sp += 12; + rets = [sp++]; +#endif + [--sp] = RETI; + SP += 4; + + /* restore normal evt14 */ + p0.l = lo(EVT14); + p0.h = hi(EVT14); + p1.l = _evt_evt14; + p1.h = _evt_evt14; + [p0] = p1; + csync; + + rts; +ENDPROC(_evt_up_evt14) + +#endif + #ifdef CONFIG_IPIPE _resume_kernel_from_int: @@ -902,8 +962,54 @@ _resume_kernel_from_int: ( r7:4, p5:3 ) = [sp++]; rets = [sp++]; rts +#elif defined(CONFIG_PREEMPT) + +_resume_kernel_from_int: + /* check preempt_count */ + r7 = sp; + r4.l = lo(ALIGN_PAGE_MASK); + r4.h = hi(ALIGN_PAGE_MASK); + r7 = r7 & r4; + p5 = r7; + r7 = [p5 + TI_PREEMPT]; + cc = r7 == 0x0; + if !cc jump .Lreturn_to_kernel; +.Lneed_schedule: + r7 = [p5 + TI_FLAGS]; + r4.l = lo(_TIF_WORK_MASK); + r4.h = hi(_TIF_WORK_MASK); + r7 = r7 & r4; + cc = BITTST(r7, TIF_NEED_RESCHED); + if !cc jump .Lreturn_to_kernel; + /* + * let schedule done at level 15, otherwise sheduled process will run + * at high level and block low level interrupt + */ + r6 = reti; /* save reti */ + r5.l = .Lkernel_schedule; + r5.h = .Lkernel_schedule; + reti = r5; + rti; +.Lkernel_schedule: + [--sp] = rets; + sp += -12; + pseudo_long_call _preempt_schedule_irq, p4; + sp += 12; + rets = [sp++]; + + [--sp] = rets; + sp += -12; + /* up to irq14 so that reti after restore_all can return to irq15(kernel) */ + pseudo_long_call _up_to_irq14, p4; + sp += 12; + rets = [sp++]; + + reti = r6; /* restore reti so that origin process can return to interrupted point */ + + jump .Lneed_schedule; #else -#define _resume_kernel_from_int 2f + +#define _resume_kernel_from_int .Lreturn_to_kernel #endif ENTRY(_return_from_int) @@ -913,7 +1019,7 @@ ENTRY(_return_from_int) p2.h = hi(ILAT); r0 = [p2]; cc = bittst (r0, EVT_IVG15_P); - if cc jump 2f; + if cc jump .Lreturn_to_kernel; /* if not return to user mode, get out */ p2.l = lo(IPEND); @@ -945,7 +1051,7 @@ ENTRY(_return_from_int) STI r0; raise 15; /* raise evt15 to do signal or reschedule */ rti; -2: +.Lreturn_to_kernel: rts; ENDPROC(_return_from_int) @@ -1631,6 +1737,7 @@ ENTRY(_sys_call_table) .long _sys_fanotify_init .long _sys_fanotify_mark .long _sys_prlimit64 + .long _sys_cacheflush .rept NR_syscalls-(.-_sys_call_table)/4 .long _sys_ni_syscall diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index cee62cf4acd..2df37db3b49 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S @@ -116,7 +116,24 @@ __common_int_entry: cc = r0 == 0; if cc jump .Lcommon_restore_context; #else /* CONFIG_IPIPE */ + +#ifdef CONFIG_PREEMPT + r7 = sp; + r4.l = lo(ALIGN_PAGE_MASK); + r4.h = hi(ALIGN_PAGE_MASK); + r7 = r7 & r4; + p5 = r7; + r7 = [p5 + TI_PREEMPT]; /* get preempt count */ + r7 += 1; /* increment it */ + [p5 + TI_PREEMPT] = r7; +#endif pseudo_long_call _do_irq, p2; + +#ifdef CONFIG_PREEMPT + r7 += -1; + [p5 + TI_PREEMPT] = r7; /* restore preempt count */ +#endif + SP += 12; #endif /* CONFIG_IPIPE */ pseudo_long_call _return_from_int, p2; diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index eaece5f84e4..da7e3c63746 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -511,7 +511,7 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq, int i, irq = 0; u32 status = bfin_read_EMAC_SYSTAT(); - for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) + for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) if (status & (1L << i)) { irq = IRQ_MAC_PHYINT + i; break; @@ -529,8 +529,9 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq, } else printk(KERN_ERR "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" - " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", - __func__, __FILE__, __LINE__); + " INTERRUPT ASSERTED BUT NO SOURCE FOUND" + "(EMAC_SYSTAT=0x%X)\n", + __func__, __FILE__, __LINE__, status); } #endif @@ -1298,7 +1299,7 @@ void do_irq(int vec, struct pt_regs *fp) } else { struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; -#if defined(SIC_ISR0) || defined(SICA_ISR0) +#if defined(SIC_ISR0) unsigned long sic_status[3]; if (smp_processor_id()) { @@ -1378,7 +1379,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) if (likely(vec == EVT_IVTMR_P)) irq = IRQ_CORETMR; else { -#if defined(SIC_ISR0) || defined(SICA_ISR0) +#if defined(SIC_ISR0) unsigned long sic_status[3]; sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index bb4e8fff4b5..f8435cd36c7 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c @@ -158,5 +158,8 @@ void __init_refok free_initmem(void) free_init_pages("unused kernel memory", (unsigned long)(&__init_begin), (unsigned long)(&__init_end)); + + if (memory_start == (unsigned long)(&__init_end)) + memory_start = (unsigned long)(&__init_begin); #endif } diff --git a/arch/cris/include/asm/ioctls.h b/arch/cris/include/asm/ioctls.h index c9129ed3744..488fbb3f5e8 100644 --- a/arch/cris/include/asm/ioctls.h +++ b/arch/cris/include/asm/ioctls.h @@ -1,93 +1,11 @@ #ifndef __ARCH_CRIS_IOCTLS_H__ #define __ARCH_CRIS_IOCTLS_H__ -/* verbatim copy of asm-i386/ioctls.h */ - -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x5460 - #define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ #define TIOCSERWRRS485 0x5462 /* write rs-485 */ #define TIOCSRS485 0x5463 /* enable rs-485 */ -#define TIOCGRS485 0x542E /* get rs-485 */ - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif diff --git a/arch/frv/include/asm/ioctls.h b/arch/frv/include/asm/ioctls.h index a993e3759cc..2f9fb436ec3 100644 --- a/arch/frv/include/asm/ioctls.h +++ b/arch/frv/include/asm/ioctls.h @@ -1,88 +1,10 @@ #ifndef __ASM_IOCTLS_H__ #define __ASM_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ #define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* __ASM_IOCTLS_H__ */ diff --git a/arch/h8300/include/asm/ioctls.h b/arch/h8300/include/asm/ioctls.h index b6b249f9f30..30eaed2facd 100644 --- a/arch/h8300/include/asm/ioctls.h +++ b/arch/h8300/include/asm/ioctls.h @@ -1,87 +1,8 @@ #ifndef __ARCH_H8300_IOCTLS_H__ #define __ARCH_H8300_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* __ARCH_H8300_IOCTLS_H__ */ diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c index 1e8d71ad93e..13633da0d3d 100644 --- a/arch/ia64/hp/sim/simserial.c +++ b/arch/ia64/hp/sim/simserial.c @@ -395,7 +395,7 @@ static int rs_ioctl(struct tty_struct *tty, struct file * file, { if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && - (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { + (cmd != TIOCMIWAIT)) { if (tty->flags & (1 << TTY_IO_ERROR)) return -EIO; } @@ -433,16 +433,6 @@ static int rs_ioctl(struct tty_struct *tty, struct file * file, case TIOCMIWAIT: printk(KERN_INFO "rs_ioctl: TIOCMIWAIT: called\n"); return 0; - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ - case TIOCGICOUNT: - printk(KERN_INFO "rs_ioctl: TIOCGICOUNT called\n"); - return 0; - case TIOCSERGWILD: case TIOCSERSWILD: /* "setserial -W" is called in Debian boot */ diff --git a/arch/ia64/include/asm/ioctls.h b/arch/ia64/include/asm/ioctls.h index b79c385114e..f3aab5512e9 100644 --- a/arch/ia64/include/asm/ioctls.h +++ b/arch/ia64/include/asm/ioctls.h @@ -1,93 +1,6 @@ #ifndef _ASM_IA64_IOCTLS_H #define _ASM_IA64_IOCTLS_H -/* - * Based on <asm-i386/ioctls.h> - * - * Modified 1998, 1999, 2002 - * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co - */ - -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x5460 - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* _ASM_IA64_IOCTLS_H */ diff --git a/arch/m32r/include/asm/ioctls.h b/arch/m32r/include/asm/ioctls.h index 66288063a4c..349bf87bfbd 100644 --- a/arch/m32r/include/asm/ioctls.h +++ b/arch/m32r/include/asm/ioctls.h @@ -1,87 +1,6 @@ #ifndef __ARCH_M32R_IOCTLS_H__ #define __ARCH_M32R_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */ -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x5460 - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* __ARCH_M32R_IOCTLS_H__ */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 8030e2481d9..77bb0d6baa6 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -434,7 +434,7 @@ config PROC_HARDWARE config ISA bool - depends on Q40 || AMIGA_PCMCIA || GG2 + depends on Q40 || AMIGA_PCMCIA default y help Find out whether you have ISA slots on your motherboard. ISA is the @@ -445,7 +445,7 @@ config ISA config GENERIC_ISA_DMA bool - depends on Q40 || AMIGA_PCMCIA || GG2 + depends on Q40 || AMIGA_PCMCIA default y config ZONE_DMA diff --git a/arch/m68k/include/asm/amigahw.h b/arch/m68k/include/asm/amigahw.h index 5ca5dd951a4..7a19b5686a4 100644 --- a/arch/m68k/include/asm/amigahw.h +++ b/arch/m68k/include/asm/amigahw.h @@ -102,7 +102,6 @@ struct amiga_hw_present { AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */ AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */ AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */ - AMIGAHW_DECLARE(GG2_ISA); /* GG2 Zorro2ISA Bridge */ AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */ AMIGAHW_DECLARE(ZORRO3); /* Zorro III */ }; diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index eab36dcacf6..03ae3d14cd4 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -1,7 +1,211 @@ -#ifdef __uClinux__ -#include "atomic_no.h" +#ifndef __ARCH_M68K_ATOMIC__ +#define __ARCH_M68K_ATOMIC__ + +#include <linux/types.h> +#include <asm/system.h> + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +/* + * We do not have SMP m68k systems, so we don't have to deal with that. + */ + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) (*(volatile int *)&(v)->counter) +#define atomic_set(v, i) (((v)->counter) = i) + +/* + * The ColdFire parts cannot do some immediate to memory operations, + * so for them we do not specify the "i" asm constraint. + */ +#ifdef CONFIG_COLDFIRE +#define ASM_DI "d" #else -#include "atomic_mm.h" +#define ASM_DI "di" #endif +static inline void atomic_add(int i, atomic_t *v) +{ + __asm__ __volatile__("addl %1,%0" : "+m" (*v) : ASM_DI (i)); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + __asm__ __volatile__("subl %1,%0" : "+m" (*v) : ASM_DI (i)); +} + +static inline void atomic_inc(atomic_t *v) +{ + __asm__ __volatile__("addql #1,%0" : "+m" (*v)); +} + +static inline void atomic_dec(atomic_t *v) +{ + __asm__ __volatile__("subql #1,%0" : "+m" (*v)); +} + +static inline int atomic_dec_and_test(atomic_t *v) +{ + char c; + __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); + return c != 0; +} + +static inline int atomic_inc_and_test(atomic_t *v) +{ + char c; + __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); + return c != 0; +} + +#ifdef CONFIG_RMW_INSNS + +static inline int atomic_add_return(int i, atomic_t *v) +{ + int t, tmp; + + __asm__ __volatile__( + "1: movel %2,%1\n" + " addl %3,%1\n" + " casl %2,%1,%0\n" + " jne 1b" + : "+m" (*v), "=&d" (t), "=&d" (tmp) + : "g" (i), "2" (atomic_read(v))); + return t; +} + +static inline int atomic_sub_return(int i, atomic_t *v) +{ + int t, tmp; + + __asm__ __volatile__( + "1: movel %2,%1\n" + " subl %3,%1\n" + " casl %2,%1,%0\n" + " jne 1b" + : "+m" (*v), "=&d" (t), "=&d" (tmp) + : "g" (i), "2" (atomic_read(v))); + return t; +} + +#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + +#else /* !CONFIG_RMW_INSNS */ + +static inline int atomic_add_return(int i, atomic_t * v) +{ + unsigned long flags; + int t; + + local_irq_save(flags); + t = atomic_read(v); + t += i; + atomic_set(v, t); + local_irq_restore(flags); + + return t; +} + +static inline int atomic_sub_return(int i, atomic_t * v) +{ + unsigned long flags; + int t; + + local_irq_save(flags); + t = atomic_read(v); + t -= i; + atomic_set(v, t); + local_irq_restore(flags); + + return t; +} + +static inline int atomic_cmpxchg(atomic_t *v, int old, int new) +{ + unsigned long flags; + int prev; + + local_irq_save(flags); + prev = atomic_read(v); + if (prev == old) + atomic_set(v, new); + local_irq_restore(flags); + return prev; +} + +static inline int atomic_xchg(atomic_t *v, int new) +{ + unsigned long flags; + int prev; + + local_irq_save(flags); + prev = atomic_read(v); + atomic_set(v, new); + local_irq_restore(flags); + return prev; +} + +#endif /* !CONFIG_RMW_INSNS */ + +#define atomic_dec_return(v) atomic_sub_return(1, (v)) +#define atomic_inc_return(v) atomic_add_return(1, (v)) + +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + char c; + __asm__ __volatile__("subl %2,%1; seq %0" + : "=d" (c), "+m" (*v) + : ASM_DI (i)); + return c != 0; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + char c; + __asm__ __volatile__("addl %2,%1; smi %0" + : "=d" (c), "+m" (*v) + : "id" (i)); + return c != 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) +{ + __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); +} + +static inline void atomic_set_mask(unsigned long mask, unsigned long *v) +{ + __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); +} + +static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) +{ + int c, old; + c = atomic_read(v); + for (;;) { + if (unlikely(c == (u))) + break; + old = atomic_cmpxchg((v), c, c + (a)); + if (likely(old == c)) + break; + c = old; + } + return c != (u); +} + +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +/* Atomic operations are already serializing */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include <asm-generic/atomic-long.h> #include <asm-generic/atomic64.h> +#endif /* __ARCH_M68K_ATOMIC __ */ diff --git a/arch/m68k/include/asm/atomic_mm.h b/arch/m68k/include/asm/atomic_mm.h deleted file mode 100644 index 6a223b3f7e7..00000000000 --- a/arch/m68k/include/asm/atomic_mm.h +++ /dev/null @@ -1,200 +0,0 @@ -#ifndef __ARCH_M68K_ATOMIC__ -#define __ARCH_M68K_ATOMIC__ - -#include <linux/types.h> -#include <asm/system.h> - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -/* - * We do not have SMP m68k systems, so we don't have to deal with that. - */ - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) (*(volatile int *)&(v)->counter) -#define atomic_set(v, i) (((v)->counter) = i) - -static inline void atomic_add(int i, atomic_t *v) -{ - __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i)); -} - -static inline void atomic_sub(int i, atomic_t *v) -{ - __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i)); -} - -static inline void atomic_inc(atomic_t *v) -{ - __asm__ __volatile__("addql #1,%0" : "+m" (*v)); -} - -static inline void atomic_dec(atomic_t *v) -{ - __asm__ __volatile__("subql #1,%0" : "+m" (*v)); -} - -static inline int atomic_dec_and_test(atomic_t *v) -{ - char c; - __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -static inline int atomic_inc_and_test(atomic_t *v) -{ - char c; - __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -#ifdef CONFIG_RMW_INSNS - -static inline int atomic_add_return(int i, atomic_t *v) -{ - int t, tmp; - - __asm__ __volatile__( - "1: movel %2,%1\n" - " addl %3,%1\n" - " casl %2,%1,%0\n" - " jne 1b" - : "+m" (*v), "=&d" (t), "=&d" (tmp) - : "g" (i), "2" (atomic_read(v))); - return t; -} - -static inline int atomic_sub_return(int i, atomic_t *v) -{ - int t, tmp; - - __asm__ __volatile__( - "1: movel %2,%1\n" - " subl %3,%1\n" - " casl %2,%1,%0\n" - " jne 1b" - : "+m" (*v), "=&d" (t), "=&d" (tmp) - : "g" (i), "2" (atomic_read(v))); - return t; -} - -#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -#else /* !CONFIG_RMW_INSNS */ - -static inline int atomic_add_return(int i, atomic_t * v) -{ - unsigned long flags; - int t; - - local_irq_save(flags); - t = atomic_read(v); - t += i; - atomic_set(v, t); - local_irq_restore(flags); - - return t; -} - -static inline int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long flags; - int t; - - local_irq_save(flags); - t = atomic_read(v); - t -= i; - atomic_set(v, t); - local_irq_restore(flags); - - return t; -} - -static inline int atomic_cmpxchg(atomic_t *v, int old, int new) -{ - unsigned long flags; - int prev; - - local_irq_save(flags); - prev = atomic_read(v); - if (prev == old) - atomic_set(v, new); - local_irq_restore(flags); - return prev; -} - -static inline int atomic_xchg(atomic_t *v, int new) -{ - unsigned long flags; - int prev; - - local_irq_save(flags); - prev = atomic_read(v); - atomic_set(v, new); - local_irq_restore(flags); - return prev; -} - -#endif /* !CONFIG_RMW_INSNS */ - -#define atomic_dec_return(v) atomic_sub_return(1, (v)) -#define atomic_inc_return(v) atomic_add_return(1, (v)) - -static inline int atomic_sub_and_test(int i, atomic_t *v) -{ - char c; - __asm__ __volatile__("subl %2,%1; seq %0" - : "=d" (c), "+m" (*v) - : "id" (i)); - return c != 0; -} - -static inline int atomic_add_negative(int i, atomic_t *v) -{ - char c; - __asm__ __volatile__("addl %2,%1; smi %0" - : "=d" (c), "+m" (*v) - : "id" (i)); - return c != 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); -} - -static inline void atomic_set_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); -} - -static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) -{ - int c, old; - c = atomic_read(v); - for (;;) { - if (unlikely(c == (u))) - break; - old = atomic_cmpxchg((v), c, c + (a)); - if (likely(old == c)) - break; - c = old; - } - return c != (u); -} - -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#include <asm-generic/atomic-long.h> -#endif /* __ARCH_M68K_ATOMIC __ */ diff --git a/arch/m68k/include/asm/atomic_no.h b/arch/m68k/include/asm/atomic_no.h deleted file mode 100644 index 289310c63a8..00000000000 --- a/arch/m68k/include/asm/atomic_no.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __ARCH_M68KNOMMU_ATOMIC__ -#define __ARCH_M68KNOMMU_ATOMIC__ - -#include <linux/types.h> -#include <asm/system.h> - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -/* - * We do not have SMP m68k systems, so we don't have to deal with that. - */ - -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) (*(volatile int *)&(v)->counter) -#define atomic_set(v, i) (((v)->counter) = i) - -static __inline__ void atomic_add(int i, atomic_t *v) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i)); -#else - __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i)); -#endif -} - -static __inline__ void atomic_sub(int i, atomic_t *v) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i)); -#else - __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i)); -#endif -} - -static __inline__ int atomic_sub_and_test(int i, atomic_t * v) -{ - char c; -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("subl %2,%1; seq %0" - : "=d" (c), "+m" (*v) - : "d" (i)); -#else - __asm__ __volatile__("subl %2,%1; seq %0" - : "=d" (c), "+m" (*v) - : "di" (i)); -#endif - return c != 0; -} - -static __inline__ void atomic_inc(volatile atomic_t *v) -{ - __asm__ __volatile__("addql #1,%0" : "+m" (*v)); -} - -/* - * atomic_inc_and_test - increment and test - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ - -static __inline__ int atomic_inc_and_test(volatile atomic_t *v) -{ - char c; - __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -static __inline__ void atomic_dec(volatile atomic_t *v) -{ - __asm__ __volatile__("subql #1,%0" : "+m" (*v)); -} - -static __inline__ int atomic_dec_and_test(volatile atomic_t *v) -{ - char c; - __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); -} - -static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); -} - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -static inline int atomic_add_return(int i, atomic_t * v) -{ - unsigned long temp, flags; - - local_irq_save(flags); - temp = *(long *)v; - temp += i; - *(long *)v = temp; - local_irq_restore(flags); - - return temp; -} - -#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) - -static inline int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long temp, flags; - - local_irq_save(flags); - temp = *(long *)v; - temp -= i; - *(long *)v = temp; - local_irq_restore(flags); - - return temp; -} - -#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) -{ - int c, old; - c = atomic_read(v); - for (;;) { - if (unlikely(c == (u))) - break; - old = atomic_cmpxchg((v), c, c + (a)); - if (likely(old == c)) - break; - c = old; - } - return c != (u); -} - -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) - -#include <asm-generic/atomic-long.h> -#endif /* __ARCH_M68KNOMMU_ATOMIC __ */ diff --git a/arch/m68k/include/asm/entry_mm.h b/arch/m68k/include/asm/entry_mm.h index 47412588621..e41fea399bf 100644 --- a/arch/m68k/include/asm/entry_mm.h +++ b/arch/m68k/include/asm/entry_mm.h @@ -3,6 +3,9 @@ #include <asm/setup.h> #include <asm/page.h> +#ifdef __ASSEMBLY__ +#include <asm/thread_info.h> +#endif /* * Stack layout in 'ret_from_exception': diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h index 9e673e3bd43..0fb3468000e 100644 --- a/arch/m68k/include/asm/io_mm.h +++ b/arch/m68k/include/asm/io_mm.h @@ -49,23 +49,6 @@ #define MULTI_ISA 0 #endif /* Q40 */ -/* GG-II Zorro to ISA bridge */ -#ifdef CONFIG_GG2 - -extern unsigned long gg2_isa_base; -#define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4)) -#define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+ ((unsigned long)(ioaddr)*4)) -#define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff)) -#define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff)) - -#ifndef MULTI_ISA -#define MULTI_ISA 0 -#else -#undef MULTI_ISA -#define MULTI_ISA 1 -#endif -#endif /* GG2 */ - #ifdef CONFIG_AMIGA_PCMCIA #include <asm/amigayle.h> @@ -89,8 +72,7 @@ extern unsigned long gg2_isa_base; #endif #define ISA_TYPE_Q40 (1) -#define ISA_TYPE_GG2 (2) -#define ISA_TYPE_AG (3) +#define ISA_TYPE_AG (2) #if defined(CONFIG_Q40) && !defined(MULTI_ISA) #define ISA_TYPE ISA_TYPE_Q40 @@ -100,10 +82,6 @@ extern unsigned long gg2_isa_base; #define ISA_TYPE ISA_TYPE_AG #define ISA_SEX 1 #endif -#if defined(CONFIG_GG2) && !defined(MULTI_ISA) -#define ISA_TYPE ISA_TYPE_GG2 -#define ISA_SEX 0 -#endif #ifdef MULTI_ISA extern int isa_type; @@ -125,9 +103,6 @@ static inline u8 __iomem *isa_itb(unsigned long addr) #ifdef CONFIG_Q40 case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr); #endif -#ifdef CONFIG_GG2 - case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_IO_B(addr); -#endif #ifdef CONFIG_AMIGA_PCMCIA case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr); #endif @@ -141,9 +116,6 @@ static inline u16 __iomem *isa_itw(unsigned long addr) #ifdef CONFIG_Q40 case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr); #endif -#ifdef CONFIG_GG2 - case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_IO_W(addr); -#endif #ifdef CONFIG_AMIGA_PCMCIA case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr); #endif @@ -167,9 +139,6 @@ static inline u8 __iomem *isa_mtb(unsigned long addr) #ifdef CONFIG_Q40 case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr); #endif -#ifdef CONFIG_GG2 - case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_MEM_B(addr); -#endif #ifdef CONFIG_AMIGA_PCMCIA case ISA_TYPE_AG: return (u8 __iomem *)addr; #endif @@ -183,9 +152,6 @@ static inline u16 __iomem *isa_mtw(unsigned long addr) #ifdef CONFIG_Q40 case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr); #endif -#ifdef CONFIG_GG2 - case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_MEM_W(addr); -#endif #ifdef CONFIG_AMIGA_PCMCIA case ISA_TYPE_AG: return (u16 __iomem *)addr; #endif @@ -217,9 +183,6 @@ static inline void isa_delay(void) #ifdef CONFIG_Q40 case ISA_TYPE_Q40: isa_outb(0,0x80); break; #endif -#ifdef CONFIG_GG2 - case ISA_TYPE_GG2: break; -#endif #ifdef CONFIG_AMIGA_PCMCIA case ISA_TYPE_AG: break; #endif @@ -287,9 +250,13 @@ static inline void isa_delay(void) #define outb(val,port) ((void)0) #define outb_p(val,port) ((void)0) #define inw(port) 0xffff +#define inw_p(port) 0xffff #define outw(val,port) ((void)0) +#define outw_p(val,port) ((void)0) #define inl(port) 0xffffffffUL +#define inl_p(port) 0xffffffffUL #define outl(val,port) ((void)0) +#define outl_p(val,port) ((void)0) #define insb(port,buf,nr) ((void)0) #define outsb(port,buf,nr) ((void)0) diff --git a/arch/m68k/include/asm/ioctls.h b/arch/m68k/include/asm/ioctls.h index 91a57d66546..1332bb4ca5b 100644 --- a/arch/m68k/include/asm/ioctls.h +++ b/arch/m68k/include/asm/ioctls.h @@ -1,86 +1,8 @@ #ifndef __ARCH_M68K_IOCTLS_H__ #define __ARCH_M68K_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* __ARCH_M68K_IOCTLS_H__ */ diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h index fc24b6fc550..789f3b2de0e 100644 --- a/arch/m68k/include/asm/machdep.h +++ b/arch/m68k/include/asm/machdep.h @@ -1,5 +1,44 @@ -#ifdef __uClinux__ -#include "machdep_no.h" -#else -#include "machdep_mm.h" -#endif +#ifndef _M68K_MACHDEP_H +#define _M68K_MACHDEP_H + +#include <linux/seq_file.h> +#include <linux/interrupt.h> + +struct pt_regs; +struct mktime; +struct rtc_time; +struct rtc_pll_info; +struct buffer_head; + +extern void (*mach_sched_init) (irq_handler_t handler); +/* machine dependent irq functions */ +extern void (*mach_init_IRQ) (void); +extern void (*mach_get_model) (char *model); +extern void (*mach_get_hardware_list) (struct seq_file *m); +/* machine dependent timer functions */ +extern unsigned long (*mach_gettimeoffset)(void); +extern int (*mach_hwclk)(int, struct rtc_time*); +extern unsigned int (*mach_get_ss)(void); +extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); +extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); +extern int (*mach_set_clock_mmss)(unsigned long); +extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, + int *min, int *sec); +extern void (*mach_reset)( void ); +extern void (*mach_halt)( void ); +extern void (*mach_power_off)( void ); +extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); +extern void (*mach_hd_setup)(char *, int *); +extern long mach_max_dma_address; +extern void (*mach_heartbeat) (int); +extern void (*mach_l2_flush) (int); +extern void (*mach_beep) (unsigned int, unsigned int); + +/* Hardware clock functions */ +extern void hw_timer_init(void); +extern unsigned long hw_timer_offset(void); +extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); + +extern void config_BSP(char *command, int len); + +#endif /* _M68K_MACHDEP_H */ diff --git a/arch/m68k/include/asm/machdep_mm.h b/arch/m68k/include/asm/machdep_mm.h deleted file mode 100644 index 5637dcef314..00000000000 --- a/arch/m68k/include/asm/machdep_mm.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _M68K_MACHDEP_H -#define _M68K_MACHDEP_H - -#include <linux/seq_file.h> -#include <linux/interrupt.h> - -struct pt_regs; -struct mktime; -struct rtc_time; -struct rtc_pll_info; -struct buffer_head; - -extern void (*mach_sched_init) (irq_handler_t handler); -/* machine dependent irq functions */ -extern void (*mach_init_IRQ) (void); -extern void (*mach_get_model) (char *model); -extern void (*mach_get_hardware_list) (struct seq_file *m); -/* machine dependent timer functions */ -extern unsigned long (*mach_gettimeoffset)(void); -extern int (*mach_hwclk)(int, struct rtc_time*); -extern unsigned int (*mach_get_ss)(void); -extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); -extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); -extern int (*mach_set_clock_mmss)(unsigned long); -extern void (*mach_reset)( void ); -extern void (*mach_halt)( void ); -extern void (*mach_power_off)( void ); -extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); -extern void (*mach_hd_setup)(char *, int *); -extern long mach_max_dma_address; -extern void (*mach_heartbeat) (int); -extern void (*mach_l2_flush) (int); -extern void (*mach_beep) (unsigned int, unsigned int); - -#endif /* _M68K_MACHDEP_H */ diff --git a/arch/m68k/include/asm/machdep_no.h b/arch/m68k/include/asm/machdep_no.h deleted file mode 100644 index de9f47a51cc..00000000000 --- a/arch/m68k/include/asm/machdep_no.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _M68KNOMMU_MACHDEP_H -#define _M68KNOMMU_MACHDEP_H - -#include <linux/interrupt.h> - -/* Hardware clock functions */ -extern void hw_timer_init(void); -extern unsigned long hw_timer_offset(void); - -extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); - -/* Machine dependent time handling */ -extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, - int *min, int *sec); -extern int (*mach_set_clock_mmss)(unsigned long); - -/* machine dependent power off functions */ -extern void (*mach_reset)( void ); -extern void (*mach_halt)( void ); -extern void (*mach_power_off)( void ); - -extern void config_BSP(char *command, int len); - -extern void do_IRQ(int irq, struct pt_regs *fp); - -#endif /* _M68KNOMMU_MACHDEP_H */ diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h index f2b4480cc98..dfebb7c1e37 100644 --- a/arch/m68k/include/asm/page.h +++ b/arch/m68k/include/asm/page.h @@ -1,5 +1,49 @@ -#ifdef __uClinux__ -#include "page_no.h" +#ifndef _M68K_PAGE_H +#define _M68K_PAGE_H + +#include <linux/const.h> +#include <asm/setup.h> +#include <asm/page_offset.h> + +/* PAGE_SHIFT determines the page size */ +#ifndef CONFIG_SUN3 +#define PAGE_SHIFT (12) #else +#define PAGE_SHIFT (13) +#endif +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) +#define PAGE_OFFSET (PAGE_OFFSET_RAW) + +#ifndef __ASSEMBLY__ + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pmd[16]; } pmd_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((&x)->pmd[0]) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#endif /* !__ASSEMBLY__ */ + +#ifdef CONFIG_MMU #include "page_mm.h" +#else +#include "page_no.h" #endif + +#include <asm-generic/getorder.h> + +#endif /* _M68K_PAGE_H */ diff --git a/arch/m68k/include/asm/page_mm.h b/arch/m68k/include/asm/page_mm.h index d009f3ea39a..31d5570d656 100644 --- a/arch/m68k/include/asm/page_mm.h +++ b/arch/m68k/include/asm/page_mm.h @@ -1,29 +1,9 @@ -#ifndef _M68K_PAGE_H -#define _M68K_PAGE_H - -#include <linux/const.h> - -/* PAGE_SHIFT determines the page size */ -#ifndef CONFIG_SUN3 -#define PAGE_SHIFT (12) -#else -#define PAGE_SHIFT (13) -#endif -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#include <asm/setup.h> - -#if PAGE_SHIFT < 13 -#define THREAD_SIZE (8192) -#else -#define THREAD_SIZE PAGE_SIZE -#endif +#ifndef _M68K_PAGE_MM_H +#define _M68K_PAGE_MM_H #ifndef __ASSEMBLY__ #include <linux/compiler.h> - #include <asm/module.h> #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) @@ -84,33 +64,6 @@ static inline void clear_page(void *page) flush_dcache_page(page); \ } while (0) -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd[16]; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -#endif /* !__ASSEMBLY__ */ - -#include <asm/page_offset.h> - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - extern unsigned long m68k_memoffset; #ifndef CONFIG_SUN3 @@ -127,7 +80,7 @@ static inline unsigned long ___pa(void *vaddr) : "0" (vaddr), "i" (m68k_fixup_memoffset)); return paddr; } -#define __pa(vaddr) ___pa((void *)(vaddr)) +#define __pa(vaddr) ___pa((void *)(long)(vaddr)) static inline void *__va(unsigned long paddr) { void *vaddr; @@ -223,6 +176,4 @@ static inline __attribute_const__ int __virt_to_node_shift(void) #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -#include <asm-generic/getorder.h> - -#endif /* _M68K_PAGE_H */ +#endif /* _M68K_PAGE_MM_H */ diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h index 8029a33e03c..90595721185 100644 --- a/arch/m68k/include/asm/page_no.h +++ b/arch/m68k/include/asm/page_no.h @@ -1,18 +1,11 @@ -#ifndef _M68KNOMMU_PAGE_H -#define _M68KNOMMU_PAGE_H - -#include <linux/const.h> - -/* PAGE_SHIFT determines the page size */ - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#include <asm/setup.h> +#ifndef _M68K_PAGE_NO_H +#define _M68K_PAGE_NO_H #ifndef __ASSEMBLY__ +extern unsigned long memory_start; +extern unsigned long memory_end; + #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) #define free_user_page(page, addr) free_page(addr) @@ -26,36 +19,6 @@ alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd[16]; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -extern unsigned long memory_start; -extern unsigned long memory_end; - -#endif /* !__ASSEMBLY__ */ - -#include <asm/page_offset.h> - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - #define __pa(vaddr) ((unsigned long)(vaddr)) #define __va(paddr) ((void *)(paddr)) @@ -74,6 +37,4 @@ extern unsigned long memory_end; #endif /* __ASSEMBLY__ */ -#include <asm-generic/getorder.h> - -#endif /* _M68KNOMMU_PAGE_H */ +#endif /* _M68K_PAGE_NO_H */ diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h index 2c356f90f17..2936dda938d 100644 --- a/arch/m68k/include/asm/string.h +++ b/arch/m68k/include/asm/string.h @@ -1,5 +1,133 @@ -#ifdef __uClinux__ -#include "string_no.h" +#ifndef _M68K_STRING_H_ +#define _M68K_STRING_H_ + +#include <linux/types.h> +#include <linux/compiler.h> + +static inline size_t __kernel_strlen(const char *s) +{ + const char *sc; + + for (sc = s; *sc++; ) + ; + return sc - s - 1; +} + +static inline char *__kernel_strcpy(char *dest, const char *src) +{ + char *xdest = dest; + + asm volatile ("\n" + "1: move.b (%1)+,(%0)+\n" + " jne 1b" + : "+a" (dest), "+a" (src) + : : "memory"); + return xdest; +} + +#ifndef __IN_STRING_C + +#define __HAVE_ARCH_STRLEN +#define strlen(s) (__builtin_constant_p(s) ? \ + __builtin_strlen(s) : \ + __kernel_strlen(s)) + +#define __HAVE_ARCH_STRNLEN +static inline size_t strnlen(const char *s, size_t count) +{ + const char *sc = s; + + asm volatile ("\n" + "1: subq.l #1,%1\n" + " jcs 2f\n" + " tst.b (%0)+\n" + " jne 1b\n" + " subq.l #1,%0\n" + "2:" + : "+a" (sc), "+d" (count)); + return sc - s; +} + +#define __HAVE_ARCH_STRCPY +#if __GNUC__ >= 4 +#define strcpy(d, s) (__builtin_constant_p(s) && \ + __builtin_strlen(s) <= 32 ? \ + __builtin_strcpy(d, s) : \ + __kernel_strcpy(d, s)) #else -#include "string_mm.h" +#define strcpy(d, s) __kernel_strcpy(d, s) #endif + +#define __HAVE_ARCH_STRNCPY +static inline char *strncpy(char *dest, const char *src, size_t n) +{ + char *xdest = dest; + + asm volatile ("\n" + " jra 2f\n" + "1: move.b (%1),(%0)+\n" + " jeq 2f\n" + " addq.l #1,%1\n" + "2: subq.l #1,%2\n" + " jcc 1b\n" + : "+a" (dest), "+a" (src), "+d" (n) + : : "memory"); + return xdest; +} + +#define __HAVE_ARCH_STRCAT +#define strcat(d, s) ({ \ + char *__d = (d); \ + strcpy(__d + strlen(__d), (s)); \ +}) + +#define __HAVE_ARCH_STRCHR +static inline char *strchr(const char *s, int c) +{ + char sc, ch = c; + + for (; (sc = *s++) != ch; ) { + if (!sc) + return NULL; + } + return (char *)s - 1; +} + +#ifndef CONFIG_COLDFIRE +#define __HAVE_ARCH_STRCMP +static inline int strcmp(const char *cs, const char *ct) +{ + char res; + + asm ("\n" + "1: move.b (%0)+,%2\n" /* get *cs */ + " cmp.b (%1)+,%2\n" /* compare a byte */ + " jne 2f\n" /* not equal, break out */ + " tst.b %2\n" /* at end of cs? */ + " jne 1b\n" /* no, keep going */ + " jra 3f\n" /* strings are equal */ + "2: sub.b -(%1),%2\n" /* *cs - *ct */ + "3:" + : "+a" (cs), "+a" (ct), "=d" (res)); + return res; +} + +#define __HAVE_ARCH_MEMMOVE +extern void *memmove(void *, const void *, __kernel_size_t); + +#define __HAVE_ARCH_MEMCMP +extern int memcmp(const void *, const void *, __kernel_size_t); +#define memcmp(d, s, n) __builtin_memcmp(d, s, n) +#endif /* CONFIG_COLDFIRE */ + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *, int, __kernel_size_t); +#define memset(d, c, n) __builtin_memset(d, c, n) + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, __kernel_size_t); +#define memcpy(d, s, n) __builtin_memcpy(d, s, n) + +#endif + +#endif /* _M68K_STRING_H_ */ diff --git a/arch/m68k/include/asm/string_mm.h b/arch/m68k/include/asm/string_mm.h deleted file mode 100644 index 2eb7df1e0f5..00000000000 --- a/arch/m68k/include/asm/string_mm.h +++ /dev/null @@ -1,131 +0,0 @@ -#ifndef _M68K_STRING_H_ -#define _M68K_STRING_H_ - -#include <linux/types.h> -#include <linux/compiler.h> - -static inline size_t __kernel_strlen(const char *s) -{ - const char *sc; - - for (sc = s; *sc++; ) - ; - return sc - s - 1; -} - -static inline char *__kernel_strcpy(char *dest, const char *src) -{ - char *xdest = dest; - - asm volatile ("\n" - "1: move.b (%1)+,(%0)+\n" - " jne 1b" - : "+a" (dest), "+a" (src) - : : "memory"); - return xdest; -} - -#ifndef __IN_STRING_C - -#define __HAVE_ARCH_STRLEN -#define strlen(s) (__builtin_constant_p(s) ? \ - __builtin_strlen(s) : \ - __kernel_strlen(s)) - -#define __HAVE_ARCH_STRNLEN -static inline size_t strnlen(const char *s, size_t count) -{ - const char *sc = s; - - asm volatile ("\n" - "1: subq.l #1,%1\n" - " jcs 2f\n" - " tst.b (%0)+\n" - " jne 1b\n" - " subq.l #1,%0\n" - "2:" - : "+a" (sc), "+d" (count)); - return sc - s; -} - -#define __HAVE_ARCH_STRCPY -#if __GNUC__ >= 4 -#define strcpy(d, s) (__builtin_constant_p(s) && \ - __builtin_strlen(s) <= 32 ? \ - __builtin_strcpy(d, s) : \ - __kernel_strcpy(d, s)) -#else -#define strcpy(d, s) __kernel_strcpy(d, s) -#endif - -#define __HAVE_ARCH_STRNCPY -static inline char *strncpy(char *dest, const char *src, size_t n) -{ - char *xdest = dest; - - asm volatile ("\n" - " jra 2f\n" - "1: move.b (%1),(%0)+\n" - " jeq 2f\n" - " addq.l #1,%1\n" - "2: subq.l #1,%2\n" - " jcc 1b\n" - : "+a" (dest), "+a" (src), "+d" (n) - : : "memory"); - return xdest; -} - -#define __HAVE_ARCH_STRCAT -#define strcat(d, s) ({ \ - char *__d = (d); \ - strcpy(__d + strlen(__d), (s)); \ -}) - -#define __HAVE_ARCH_STRCHR -static inline char *strchr(const char *s, int c) -{ - char sc, ch = c; - - for (; (sc = *s++) != ch; ) { - if (!sc) - return NULL; - } - return (char *)s - 1; -} - -#define __HAVE_ARCH_STRCMP -static inline int strcmp(const char *cs, const char *ct) -{ - char res; - - asm ("\n" - "1: move.b (%0)+,%2\n" /* get *cs */ - " cmp.b (%1)+,%2\n" /* compare a byte */ - " jne 2f\n" /* not equal, break out */ - " tst.b %2\n" /* at end of cs? */ - " jne 1b\n" /* no, keep going */ - " jra 3f\n" /* strings are equal */ - "2: sub.b -(%1),%2\n" /* *cs - *ct */ - "3:" - : "+a" (cs), "+a" (ct), "=d" (res)); - return res; -} - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, __kernel_size_t); -#define memset(d, c, n) __builtin_memset(d, c, n) - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, __kernel_size_t); -#define memcpy(d, s, n) __builtin_memcpy(d, s, n) - -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *, const void *, __kernel_size_t); - -#define __HAVE_ARCH_MEMCMP -extern int memcmp(const void *, const void *, __kernel_size_t); -#define memcmp(d, s, n) __builtin_memcmp(d, s, n) - -#endif - -#endif /* _M68K_STRING_H_ */ diff --git a/arch/m68k/include/asm/string_no.h b/arch/m68k/include/asm/string_no.h deleted file mode 100644 index af09e17000f..00000000000 --- a/arch/m68k/include/asm/string_no.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef _M68KNOMMU_STRING_H_ -#define _M68KNOMMU_STRING_H_ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#include <asm/setup.h> -#include <asm/page.h> - -#define __HAVE_ARCH_STRCPY -static inline char * strcpy(char * dest,const char *src) -{ - char *xdest = dest; - - __asm__ __volatile__ - ("1:\tmoveb %1@+,%0@+\n\t" - "jne 1b" - : "=a" (dest), "=a" (src) - : "0" (dest), "1" (src) : "memory"); - return xdest; -} - -#define __HAVE_ARCH_STRNCPY -static inline char * strncpy(char *dest, const char *src, size_t n) -{ - char *xdest = dest; - - if (n == 0) - return xdest; - - __asm__ __volatile__ - ("1:\tmoveb %1@+,%0@+\n\t" - "jeq 2f\n\t" - "subql #1,%2\n\t" - "jne 1b\n\t" - "2:" - : "=a" (dest), "=a" (src), "=d" (n) - : "0" (dest), "1" (src), "2" (n) - : "memory"); - return xdest; -} - - -#ifndef CONFIG_COLDFIRE - -#define __HAVE_ARCH_STRCMP -static inline int strcmp(const char * cs,const char * ct) -{ - char __res; - - __asm__ - ("1:\tmoveb %0@+,%2\n\t" /* get *cs */ - "cmpb %1@+,%2\n\t" /* compare a byte */ - "jne 2f\n\t" /* not equal, break out */ - "tstb %2\n\t" /* at end of cs? */ - "jne 1b\n\t" /* no, keep going */ - "jra 3f\n\t" /* strings are equal */ - "2:\tsubb %1@-,%2\n\t" /* *cs - *ct */ - "3:" - : "=a" (cs), "=a" (ct), "=d" (__res) - : "0" (cs), "1" (ct)); - - return __res; -} - -#define __HAVE_ARCH_STRNCMP -static inline int strncmp(const char * cs,const char * ct,size_t count) -{ - char __res; - - if (!count) - return 0; - __asm__ - ("1:\tmovb %0@+,%3\n\t" /* get *cs */ - "cmpb %1@+,%3\n\t" /* compare a byte */ - "jne 3f\n\t" /* not equal, break out */ - "tstb %3\n\t" /* at end of cs? */ - "jeq 4f\n\t" /* yes, all done */ - "subql #1,%2\n\t" /* no, adjust count */ - "jne 1b\n\t" /* more to do, keep going */ - "2:\tmoveq #0,%3\n\t" /* strings are equal */ - "jra 4f\n\t" - "3:\tsubb %1@-,%3\n\t" /* *cs - *ct */ - "4:" - : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res) - : "0" (cs), "1" (ct), "2" (count)); - return __res; -} - -#endif /* CONFIG_COLDFIRE */ - -#define __HAVE_ARCH_MEMSET -extern void * memset(void * s, int c, size_t count); - -#define __HAVE_ARCH_MEMCPY -extern void * memcpy(void *d, const void *s, size_t count); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ - -#endif /* _M68K_STRING_H_ */ diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h index 12053c44ccc..47b01f4726b 100644 --- a/arch/m68k/include/asm/system_mm.h +++ b/arch/m68k/include/asm/system_mm.h @@ -182,9 +182,7 @@ static inline unsigned long __cmpxchg(volatile void *p, unsigned long old, ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ (unsigned long)(n), sizeof(*(ptr)))) -#ifndef CONFIG_SMP #include <asm-generic/cmpxchg.h> -#endif #endif diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h index 20126c09794..6fe9f93bc3f 100644 --- a/arch/m68k/include/asm/system_no.h +++ b/arch/m68k/include/asm/system_no.h @@ -59,17 +59,10 @@ asmlinkage void resume(void); #define wmb() asm volatile ("" : : :"memory") #define set_mb(var, value) ({ (var) = (value); wmb(); }) -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else #define smp_mb() barrier() #define smp_rmb() barrier() #define smp_wmb() barrier() #define smp_read_barrier_depends() do { } while(0) -#endif #define read_barrier_depends() ((void)0) @@ -152,9 +145,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz (unsigned long)(n), sizeof(*(ptr)))) #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) -#ifndef CONFIG_SMP #include <asm-generic/cmpxchg.h> -#endif #define arch_align_stack(x) (x) diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h index f31a3f42b7b..1da5d53a00e 100644 --- a/arch/m68k/include/asm/thread_info.h +++ b/arch/m68k/include/asm/thread_info.h @@ -1,5 +1,108 @@ -#ifdef __uClinux__ -#include "thread_info_no.h" +#ifndef _ASM_M68K_THREAD_INFO_H +#define _ASM_M68K_THREAD_INFO_H + +#include <asm/types.h> +#include <asm/page.h> + +/* + * On machines with 4k pages we default to an 8k thread size, though we + * allow a 4k with config option. Any other machine page size then + * the thread size must match the page size (which is 8k and larger here). + */ +#if PAGE_SHIFT < 13 +#ifdef CONFIG_4KSTACKS +#define THREAD_SIZE 4096 #else -#include "thread_info_mm.h" +#define THREAD_SIZE 8192 #endif +#else +#define THREAD_SIZE PAGE_SIZE +#endif +#define THREAD_SIZE_ORDER ((THREAD_SIZE / PAGE_SIZE) - 1) + +#ifndef __ASSEMBLY__ + +struct thread_info { + struct task_struct *task; /* main task structure */ + unsigned long flags; + struct exec_domain *exec_domain; /* execution domain */ + int preempt_count; /* 0 => preemptable, <0 => BUG */ + __u32 cpu; /* should always be 0 on m68k */ + unsigned long tp_value; /* thread pointer */ + struct restart_block restart_block; +}; +#endif /* __ASSEMBLY__ */ + +#define PREEMPT_ACTIVE 0x4000000 + +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .preempt_count = INIT_PREEMPT_COUNT, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_stack (init_thread_union.stack) + +#ifdef CONFIG_MMU + +#ifndef __ASSEMBLY__ +#include <asm/current.h> +#endif + +#ifdef ASM_OFFSETS_C +#define task_thread_info(tsk) ((struct thread_info *) NULL) +#else +#include <asm/asm-offsets.h> +#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_TINFO)) +#endif + +#define init_thread_info (init_task.thread.info) +#define task_stack_page(tsk) ((tsk)->stack) +#define current_thread_info() task_thread_info(current) + +#define __HAVE_THREAD_FUNCTIONS + +#define setup_thread_stack(p, org) ({ \ + *(struct task_struct **)(p)->stack = (p); \ + task_thread_info(p)->task = (p); \ +}) + +#define end_of_stack(p) ((unsigned long *)(p)->stack + 1) + +#else /* !CONFIG_MMU */ + +#ifndef __ASSEMBLY__ +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__( + "move.l %%sp, %0 \n\t" + "and.l %1, %0" + : "=&d"(ti) + : "di" (~(THREAD_SIZE-1)) + ); + return ti; +} +#endif + +#define init_thread_info (init_thread_union.thread_info) + +#endif /* CONFIG_MMU */ + +/* entry.S relies on these definitions! + * bits 0-7 are tested at every exception exit + * bits 8-15 are also tested at syscall exit + */ +#define TIF_SIGPENDING 6 /* signal pending */ +#define TIF_NEED_RESCHED 7 /* rescheduling necessary */ +#define TIF_DELAYED_TRACE 14 /* single step a syscall */ +#define TIF_SYSCALL_TRACE 15 /* syscall trace active */ +#define TIF_MEMDIE 16 /* is terminating due to OOM killer */ +#define TIF_FREEZE 17 /* thread is freezing for suspend */ + +#endif /* _ASM_M68K_THREAD_INFO_H */ diff --git a/arch/m68k/include/asm/thread_info_mm.h b/arch/m68k/include/asm/thread_info_mm.h deleted file mode 100644 index 3bf31dc51b1..00000000000 --- a/arch/m68k/include/asm/thread_info_mm.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _ASM_M68K_THREAD_INFO_H -#define _ASM_M68K_THREAD_INFO_H - -#ifndef ASM_OFFSETS_C -#include <asm/asm-offsets.h> -#endif -#include <asm/types.h> -#include <asm/page.h> - -#ifndef __ASSEMBLY__ -#include <asm/current.h> - -struct thread_info { - struct task_struct *task; /* main task structure */ - unsigned long flags; - struct exec_domain *exec_domain; /* execution domain */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - __u32 cpu; /* should always be 0 on m68k */ - unsigned long tp_value; /* thread pointer */ - struct restart_block restart_block; -}; -#endif /* __ASSEMBLY__ */ - -#define PREEMPT_ACTIVE 0x4000000 - -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -/* THREAD_SIZE should be 8k, so handle differently for 4k and 8k machines */ -#define THREAD_SIZE_ORDER (13 - PAGE_SHIFT) - -#define init_thread_info (init_task.thread.info) -#define init_stack (init_thread_union.stack) - -#ifdef ASM_OFFSETS_C -#define task_thread_info(tsk) ((struct thread_info *) NULL) -#else -#define task_thread_info(tsk) ((struct thread_info *)((char *)tsk+TASK_TINFO)) -#endif - -#define task_stack_page(tsk) ((tsk)->stack) -#define current_thread_info() task_thread_info(current) - -#define __HAVE_THREAD_FUNCTIONS - -#define setup_thread_stack(p, org) ({ \ - *(struct task_struct **)(p)->stack = (p); \ - task_thread_info(p)->task = (p); \ -}) - -#define end_of_stack(p) ((unsigned long *)(p)->stack + 1) - -/* entry.S relies on these definitions! - * bits 0-7 are tested at every exception exit - * bits 8-15 are also tested at syscall exit - */ -#define TIF_SIGPENDING 6 /* signal pending */ -#define TIF_NEED_RESCHED 7 /* rescheduling necessary */ -#define TIF_DELAYED_TRACE 14 /* single step a syscall */ -#define TIF_SYSCALL_TRACE 15 /* syscall trace active */ -#define TIF_MEMDIE 16 /* is terminating due to OOM killer */ -#define TIF_FREEZE 17 /* thread is freezing for suspend */ - -#endif /* _ASM_M68K_THREAD_INFO_H */ diff --git a/arch/m68k/include/asm/thread_info_no.h b/arch/m68k/include/asm/thread_info_no.h deleted file mode 100644 index 51f354b672e..00000000000 --- a/arch/m68k/include/asm/thread_info_no.h +++ /dev/null @@ -1,102 +0,0 @@ -/* thread_info.h: m68knommu low-level thread information - * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com) - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#include <asm/page.h> - -#ifdef __KERNEL__ - -/* - * Size of kernel stack for each process. This must be a power of 2... - */ -#ifdef CONFIG_4KSTACKS -#define THREAD_SIZE_ORDER (0) -#else -#define THREAD_SIZE_ORDER (1) -#endif - -/* - * for asm files, THREAD_SIZE is now generated by asm-offsets.c - */ -#define THREAD_SIZE (PAGE_SIZE<<THREAD_SIZE_ORDER) - -#ifndef __ASSEMBLY__ - -/* - * low level task data. - */ -struct thread_info { - struct task_struct *task; /* main task structure */ - struct exec_domain *exec_domain; /* execution domain */ - unsigned long flags; /* low level flags */ - int cpu; /* cpu we're on */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - unsigned long tp_value; /* thread pointer */ - struct restart_block restart_block; -}; - -/* - * macros/functions for gaining access to the thread information structure - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__( - "move.l %%sp, %0 \n\t" - "and.l %1, %0" - : "=&d"(ti) - : "di" (~(THREAD_SIZE-1)) - ); - return ti; -} - -#endif /* __ASSEMBLY__ */ - -#define PREEMPT_ACTIVE 0x4000000 - -/* - * thread information flag bit numbers - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling - TIF_NEED_RESCHED */ -#define TIF_MEMDIE 4 /* is terminating due to OOM killer */ -#define TIF_FREEZE 16 /* is freezing for suspend */ - -/* as above, but as bit values */ -#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) -#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) -#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) -#define _TIF_FREEZE (1<<TIF_FREEZE) - -#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ - -#endif /* __KERNEL__ */ - -#endif /* _ASM_THREAD_INFO_H */ diff --git a/arch/m68k/include/asm/traps.h b/arch/m68k/include/asm/traps.h index 3011ec0f536..0bffb17d5db 100644 --- a/arch/m68k/include/asm/traps.h +++ b/arch/m68k/include/asm/traps.h @@ -1,5 +1,272 @@ -#ifdef __uClinux__ -#include "traps_no.h" -#else -#include "traps_mm.h" +/* + * linux/include/asm/traps.h + * + * Copyright (C) 1993 Hamish Macdonald + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _M68K_TRAPS_H +#define _M68K_TRAPS_H + +#ifndef __ASSEMBLY__ + +#include <linux/linkage.h> +#include <asm/ptrace.h> + +typedef void (*e_vector)(void); +extern e_vector vectors[]; + +asmlinkage void auto_inthandler(void); +asmlinkage void user_inthandler(void); +asmlinkage void bad_inthandler(void); +extern void init_vectors(void); + #endif + +#define VEC_RESETSP (0) +#define VEC_RESETPC (1) +#define VEC_BUSERR (2) +#define VEC_ADDRERR (3) +#define VEC_ILLEGAL (4) +#define VEC_ZERODIV (5) +#define VEC_CHK (6) +#define VEC_TRAP (7) +#define VEC_PRIV (8) +#define VEC_TRACE (9) +#define VEC_LINE10 (10) +#define VEC_LINE11 (11) +#define VEC_RESV12 (12) +#define VEC_COPROC (13) +#define VEC_FORMAT (14) +#define VEC_UNINT (15) +#define VEC_RESV16 (16) +#define VEC_RESV17 (17) +#define VEC_RESV18 (18) +#define VEC_RESV19 (19) +#define VEC_RESV20 (20) +#define VEC_RESV21 (21) +#define VEC_RESV22 (22) +#define VEC_RESV23 (23) +#define VEC_SPUR (24) +#define VEC_INT1 (25) +#define VEC_INT2 (26) +#define VEC_INT3 (27) +#define VEC_INT4 (28) +#define VEC_INT5 (29) +#define VEC_INT6 (30) +#define VEC_INT7 (31) +#define VEC_SYS (32) +#define VEC_TRAP1 (33) +#define VEC_TRAP2 (34) +#define VEC_TRAP3 (35) +#define VEC_TRAP4 (36) +#define VEC_TRAP5 (37) +#define VEC_TRAP6 (38) +#define VEC_TRAP7 (39) +#define VEC_TRAP8 (40) +#define VEC_TRAP9 (41) +#define VEC_TRAP10 (42) +#define VEC_TRAP11 (43) +#define VEC_TRAP12 (44) +#define VEC_TRAP13 (45) +#define VEC_TRAP14 (46) +#define VEC_TRAP15 (47) +#define VEC_FPBRUC (48) +#define VEC_FPIR (49) +#define VEC_FPDIVZ (50) +#define VEC_FPUNDER (51) +#define VEC_FPOE (52) +#define VEC_FPOVER (53) +#define VEC_FPNAN (54) +#define VEC_FPUNSUP (55) +#define VEC_MMUCFG (56) +#define VEC_MMUILL (57) +#define VEC_MMUACC (58) +#define VEC_RESV59 (59) +#define VEC_UNIMPEA (60) +#define VEC_UNIMPII (61) +#define VEC_RESV62 (62) +#define VEC_RESV63 (63) +#define VEC_USER (64) + +#define VECOFF(vec) ((vec)<<2) + +#ifndef __ASSEMBLY__ + +/* Status register bits */ +#define PS_T (0x8000) +#define PS_S (0x2000) +#define PS_M (0x1000) +#define PS_C (0x0001) + +/* bits for 68020/68030 special status word */ + +#define FC (0x8000) +#define FB (0x4000) +#define RC (0x2000) +#define RB (0x1000) +#define DF (0x0100) +#define RM (0x0080) +#define RW (0x0040) +#define SZ (0x0030) +#define DFC (0x0007) + +/* bits for 68030 MMU status register (mmusr,psr) */ + +#define MMU_B (0x8000) /* bus error */ +#define MMU_L (0x4000) /* limit violation */ +#define MMU_S (0x2000) /* supervisor violation */ +#define MMU_WP (0x0800) /* write-protected */ +#define MMU_I (0x0400) /* invalid descriptor */ +#define MMU_M (0x0200) /* ATC entry modified */ +#define MMU_T (0x0040) /* transparent translation */ +#define MMU_NUM (0x0007) /* number of levels traversed */ + + +/* bits for 68040 special status word */ +#define CP_040 (0x8000) +#define CU_040 (0x4000) +#define CT_040 (0x2000) +#define CM_040 (0x1000) +#define MA_040 (0x0800) +#define ATC_040 (0x0400) +#define LK_040 (0x0200) +#define RW_040 (0x0100) +#define SIZ_040 (0x0060) +#define TT_040 (0x0018) +#define TM_040 (0x0007) + +/* bits for 68040 write back status word */ +#define WBV_040 (0x80) +#define WBSIZ_040 (0x60) +#define WBBYT_040 (0x20) +#define WBWRD_040 (0x40) +#define WBLNG_040 (0x00) +#define WBTT_040 (0x18) +#define WBTM_040 (0x07) + +/* bus access size codes */ +#define BA_SIZE_BYTE (0x20) +#define BA_SIZE_WORD (0x40) +#define BA_SIZE_LONG (0x00) +#define BA_SIZE_LINE (0x60) + +/* bus access transfer type codes */ +#define BA_TT_MOVE16 (0x08) + +/* bits for 68040 MMU status register (mmusr) */ +#define MMU_B_040 (0x0800) +#define MMU_G_040 (0x0400) +#define MMU_S_040 (0x0080) +#define MMU_CM_040 (0x0060) +#define MMU_M_040 (0x0010) +#define MMU_WP_040 (0x0004) +#define MMU_T_040 (0x0002) +#define MMU_R_040 (0x0001) + +/* bits in the 68060 fault status long word (FSLW) */ +#define MMU060_MA (0x08000000) /* misaligned */ +#define MMU060_LK (0x02000000) /* locked transfer */ +#define MMU060_RW (0x01800000) /* read/write */ +# define MMU060_RW_W (0x00800000) /* write */ +# define MMU060_RW_R (0x01000000) /* read */ +# define MMU060_RW_RMW (0x01800000) /* read/modify/write */ +# define MMU060_W (0x00800000) /* general write, includes rmw */ +#define MMU060_SIZ (0x00600000) /* transfer size */ +#define MMU060_TT (0x00180000) /* transfer type (TT) bits */ +#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */ +#define MMU060_IO (0x00008000) /* instruction or operand */ +#define MMU060_PBE (0x00004000) /* push buffer bus error */ +#define MMU060_SBE (0x00002000) /* store buffer bus error */ +#define MMU060_PTA (0x00001000) /* pointer A fault */ +#define MMU060_PTB (0x00000800) /* pointer B fault */ +#define MMU060_IL (0x00000400) /* double indirect descr fault */ +#define MMU060_PF (0x00000200) /* page fault (invalid descr) */ +#define MMU060_SP (0x00000100) /* supervisor protection */ +#define MMU060_WP (0x00000080) /* write protection */ +#define MMU060_TWE (0x00000040) /* bus error on table search */ +#define MMU060_RE (0x00000020) /* bus error on read */ +#define MMU060_WE (0x00000010) /* bus error on write */ +#define MMU060_TTR (0x00000008) /* error caused by TTR translation */ +#define MMU060_BPE (0x00000004) /* branch prediction error */ +#define MMU060_SEE (0x00000001) /* software emulated error */ + +/* cases of missing or invalid descriptors */ +#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \ + MMU060_IL | MMU060_PF) +/* bits that indicate real errors */ +#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \ + MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE) + +/* structure for stack frames */ + +struct frame { + struct pt_regs ptregs; + union { + struct { + unsigned long iaddr; /* instruction address */ + } fmt2; + struct { + unsigned long effaddr; /* effective address */ + } fmt3; + struct { + unsigned long effaddr; /* effective address */ + unsigned long pc; /* pc of faulted instr */ + } fmt4; + struct { + unsigned long effaddr; /* effective address */ + unsigned short ssw; /* special status word */ + unsigned short wb3s; /* write back 3 status */ + unsigned short wb2s; /* write back 2 status */ + unsigned short wb1s; /* write back 1 status */ + unsigned long faddr; /* fault address */ + unsigned long wb3a; /* write back 3 address */ + unsigned long wb3d; /* write back 3 data */ + unsigned long wb2a; /* write back 2 address */ + unsigned long wb2d; /* write back 2 data */ + unsigned long wb1a; /* write back 1 address */ + unsigned long wb1dpd0; /* write back 1 data/push data 0*/ + unsigned long pd1; /* push data 1*/ + unsigned long pd2; /* push data 2*/ + unsigned long pd3; /* push data 3*/ + } fmt7; + struct { + unsigned long iaddr; /* instruction address */ + unsigned short int1[4]; /* internal registers */ + } fmt9; + struct { + unsigned short int1; + unsigned short ssw; /* special status word */ + unsigned short isc; /* instruction stage c */ + unsigned short isb; /* instruction stage b */ + unsigned long daddr; /* data cycle fault address */ + unsigned short int2[2]; + unsigned long dobuf; /* data cycle output buffer */ + unsigned short int3[2]; + } fmta; + struct { + unsigned short int1; + unsigned short ssw; /* special status word */ + unsigned short isc; /* instruction stage c */ + unsigned short isb; /* instruction stage b */ + unsigned long daddr; /* data cycle fault address */ + unsigned short int2[2]; + unsigned long dobuf; /* data cycle output buffer */ + unsigned short int3[4]; + unsigned long baddr; /* stage B address */ + unsigned short int4[2]; + unsigned long dibuf; /* data cycle input buffer */ + unsigned short int5[3]; + unsigned ver : 4; /* stack frame version # */ + unsigned int6:12; + unsigned short int7[18]; + } fmtb; + } un; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _M68K_TRAPS_H */ diff --git a/arch/m68k/include/asm/traps_mm.h b/arch/m68k/include/asm/traps_mm.h deleted file mode 100644 index 8caef25624c..00000000000 --- a/arch/m68k/include/asm/traps_mm.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * linux/include/asm/traps.h - * - * Copyright (C) 1993 Hamish Macdonald - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _M68K_TRAPS_H -#define _M68K_TRAPS_H - -#ifndef __ASSEMBLY__ - -#include <linux/linkage.h> -#include <asm/ptrace.h> - -typedef void (*e_vector)(void); - -asmlinkage void auto_inthandler(void); -asmlinkage void user_inthandler(void); -asmlinkage void bad_inthandler(void); - -extern e_vector vectors[]; - -#endif - -#define VEC_RESETSP (0) -#define VEC_RESETPC (1) -#define VEC_BUSERR (2) -#define VEC_ADDRERR (3) -#define VEC_ILLEGAL (4) -#define VEC_ZERODIV (5) -#define VEC_CHK (6) -#define VEC_TRAP (7) -#define VEC_PRIV (8) -#define VEC_TRACE (9) -#define VEC_LINE10 (10) -#define VEC_LINE11 (11) -#define VEC_RESV12 (12) -#define VEC_COPROC (13) -#define VEC_FORMAT (14) -#define VEC_UNINT (15) -#define VEC_RESV16 (16) -#define VEC_RESV17 (17) -#define VEC_RESV18 (18) -#define VEC_RESV19 (19) -#define VEC_RESV20 (20) -#define VEC_RESV21 (21) -#define VEC_RESV22 (22) -#define VEC_RESV23 (23) -#define VEC_SPUR (24) -#define VEC_INT1 (25) -#define VEC_INT2 (26) -#define VEC_INT3 (27) -#define VEC_INT4 (28) -#define VEC_INT5 (29) -#define VEC_INT6 (30) -#define VEC_INT7 (31) -#define VEC_SYS (32) -#define VEC_TRAP1 (33) -#define VEC_TRAP2 (34) -#define VEC_TRAP3 (35) -#define VEC_TRAP4 (36) -#define VEC_TRAP5 (37) -#define VEC_TRAP6 (38) -#define VEC_TRAP7 (39) -#define VEC_TRAP8 (40) -#define VEC_TRAP9 (41) -#define VEC_TRAP10 (42) -#define VEC_TRAP11 (43) -#define VEC_TRAP12 (44) -#define VEC_TRAP13 (45) -#define VEC_TRAP14 (46) -#define VEC_TRAP15 (47) -#define VEC_FPBRUC (48) -#define VEC_FPIR (49) -#define VEC_FPDIVZ (50) -#define VEC_FPUNDER (51) -#define VEC_FPOE (52) -#define VEC_FPOVER (53) -#define VEC_FPNAN (54) -#define VEC_FPUNSUP (55) -#define VEC_MMUCFG (56) -#define VEC_MMUILL (57) -#define VEC_MMUACC (58) -#define VEC_RESV59 (59) -#define VEC_UNIMPEA (60) -#define VEC_UNIMPII (61) -#define VEC_RESV62 (62) -#define VEC_RESV63 (63) -#define VEC_USER (64) - -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x2000) -#define PS_M (0x1000) -#define PS_C (0x0001) - -/* bits for 68020/68030 special status word */ - -#define FC (0x8000) -#define FB (0x4000) -#define RC (0x2000) -#define RB (0x1000) -#define DF (0x0100) -#define RM (0x0080) -#define RW (0x0040) -#define SZ (0x0030) -#define DFC (0x0007) - -/* bits for 68030 MMU status register (mmusr,psr) */ - -#define MMU_B (0x8000) /* bus error */ -#define MMU_L (0x4000) /* limit violation */ -#define MMU_S (0x2000) /* supervisor violation */ -#define MMU_WP (0x0800) /* write-protected */ -#define MMU_I (0x0400) /* invalid descriptor */ -#define MMU_M (0x0200) /* ATC entry modified */ -#define MMU_T (0x0040) /* transparent translation */ -#define MMU_NUM (0x0007) /* number of levels traversed */ - - -/* bits for 68040 special status word */ -#define CP_040 (0x8000) -#define CU_040 (0x4000) -#define CT_040 (0x2000) -#define CM_040 (0x1000) -#define MA_040 (0x0800) -#define ATC_040 (0x0400) -#define LK_040 (0x0200) -#define RW_040 (0x0100) -#define SIZ_040 (0x0060) -#define TT_040 (0x0018) -#define TM_040 (0x0007) - -/* bits for 68040 write back status word */ -#define WBV_040 (0x80) -#define WBSIZ_040 (0x60) -#define WBBYT_040 (0x20) -#define WBWRD_040 (0x40) -#define WBLNG_040 (0x00) -#define WBTT_040 (0x18) -#define WBTM_040 (0x07) - -/* bus access size codes */ -#define BA_SIZE_BYTE (0x20) -#define BA_SIZE_WORD (0x40) -#define BA_SIZE_LONG (0x00) -#define BA_SIZE_LINE (0x60) - -/* bus access transfer type codes */ -#define BA_TT_MOVE16 (0x08) - -/* bits for 68040 MMU status register (mmusr) */ -#define MMU_B_040 (0x0800) -#define MMU_G_040 (0x0400) -#define MMU_S_040 (0x0080) -#define MMU_CM_040 (0x0060) -#define MMU_M_040 (0x0010) -#define MMU_WP_040 (0x0004) -#define MMU_T_040 (0x0002) -#define MMU_R_040 (0x0001) - -/* bits in the 68060 fault status long word (FSLW) */ -#define MMU060_MA (0x08000000) /* misaligned */ -#define MMU060_LK (0x02000000) /* locked transfer */ -#define MMU060_RW (0x01800000) /* read/write */ -# define MMU060_RW_W (0x00800000) /* write */ -# define MMU060_RW_R (0x01000000) /* read */ -# define MMU060_RW_RMW (0x01800000) /* read/modify/write */ -# define MMU060_W (0x00800000) /* general write, includes rmw */ -#define MMU060_SIZ (0x00600000) /* transfer size */ -#define MMU060_TT (0x00180000) /* transfer type (TT) bits */ -#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */ -#define MMU060_IO (0x00008000) /* instruction or operand */ -#define MMU060_PBE (0x00004000) /* push buffer bus error */ -#define MMU060_SBE (0x00002000) /* store buffer bus error */ -#define MMU060_PTA (0x00001000) /* pointer A fault */ -#define MMU060_PTB (0x00000800) /* pointer B fault */ -#define MMU060_IL (0x00000400) /* double indirect descr fault */ -#define MMU060_PF (0x00000200) /* page fault (invalid descr) */ -#define MMU060_SP (0x00000100) /* supervisor protection */ -#define MMU060_WP (0x00000080) /* write protection */ -#define MMU060_TWE (0x00000040) /* bus error on table search */ -#define MMU060_RE (0x00000020) /* bus error on read */ -#define MMU060_WE (0x00000010) /* bus error on write */ -#define MMU060_TTR (0x00000008) /* error caused by TTR translation */ -#define MMU060_BPE (0x00000004) /* branch prediction error */ -#define MMU060_SEE (0x00000001) /* software emulated error */ - -/* cases of missing or invalid descriptors */ -#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \ - MMU060_IL | MMU060_PF) -/* bits that indicate real errors */ -#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \ - MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE) - -/* structure for stack frames */ - -struct frame { - struct pt_regs ptregs; - union { - struct { - unsigned long iaddr; /* instruction address */ - } fmt2; - struct { - unsigned long effaddr; /* effective address */ - } fmt3; - struct { - unsigned long effaddr; /* effective address */ - unsigned long pc; /* pc of faulted instr */ - } fmt4; - struct { - unsigned long effaddr; /* effective address */ - unsigned short ssw; /* special status word */ - unsigned short wb3s; /* write back 3 status */ - unsigned short wb2s; /* write back 2 status */ - unsigned short wb1s; /* write back 1 status */ - unsigned long faddr; /* fault address */ - unsigned long wb3a; /* write back 3 address */ - unsigned long wb3d; /* write back 3 data */ - unsigned long wb2a; /* write back 2 address */ - unsigned long wb2d; /* write back 2 data */ - unsigned long wb1a; /* write back 1 address */ - unsigned long wb1dpd0; /* write back 1 data/push data 0*/ - unsigned long pd1; /* push data 1*/ - unsigned long pd2; /* push data 2*/ - unsigned long pd3; /* push data 3*/ - } fmt7; - struct { - unsigned long iaddr; /* instruction address */ - unsigned short int1[4]; /* internal registers */ - } fmt9; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[2]; - } fmta; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[4]; - unsigned long baddr; /* stage B address */ - unsigned short int4[2]; - unsigned long dibuf; /* data cycle input buffer */ - unsigned short int5[3]; - unsigned ver : 4; /* stack frame version # */ - unsigned int6:12; - unsigned short int7[18]; - } fmtb; - } un; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _M68K_TRAPS_H */ diff --git a/arch/m68k/include/asm/traps_no.h b/arch/m68k/include/asm/traps_no.h deleted file mode 100644 index d0671e5f8e2..00000000000 --- a/arch/m68k/include/asm/traps_no.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * linux/include/asm/traps.h - * - * Copyright (C) 1993 Hamish Macdonald - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _M68KNOMMU_TRAPS_H -#define _M68KNOMMU_TRAPS_H - -#ifndef __ASSEMBLY__ - -typedef void (*e_vector)(void); - -extern e_vector vectors[]; -extern void init_vectors(void); -extern void enable_vector(unsigned int irq); -extern void disable_vector(unsigned int irq); -extern void ack_vector(unsigned int irq); - -#endif - -#define VEC_BUSERR (2) -#define VEC_ADDRERR (3) -#define VEC_ILLEGAL (4) -#define VEC_ZERODIV (5) -#define VEC_CHK (6) -#define VEC_TRAP (7) -#define VEC_PRIV (8) -#define VEC_TRACE (9) -#define VEC_LINE10 (10) -#define VEC_LINE11 (11) -#define VEC_RESV1 (12) -#define VEC_COPROC (13) -#define VEC_FORMAT (14) -#define VEC_UNINT (15) -#define VEC_SPUR (24) -#define VEC_INT1 (25) -#define VEC_INT2 (26) -#define VEC_INT3 (27) -#define VEC_INT4 (28) -#define VEC_INT5 (29) -#define VEC_INT6 (30) -#define VEC_INT7 (31) -#define VEC_SYS (32) -#define VEC_TRAP1 (33) -#define VEC_TRAP2 (34) -#define VEC_TRAP3 (35) -#define VEC_TRAP4 (36) -#define VEC_TRAP5 (37) -#define VEC_TRAP6 (38) -#define VEC_TRAP7 (39) -#define VEC_TRAP8 (40) -#define VEC_TRAP9 (41) -#define VEC_TRAP10 (42) -#define VEC_TRAP11 (43) -#define VEC_TRAP12 (44) -#define VEC_TRAP13 (45) -#define VEC_TRAP14 (46) -#define VEC_TRAP15 (47) -#define VEC_FPBRUC (48) -#define VEC_FPIR (49) -#define VEC_FPDIVZ (50) -#define VEC_FPUNDER (51) -#define VEC_FPOE (52) -#define VEC_FPOVER (53) -#define VEC_FPNAN (54) -#define VEC_FPUNSUP (55) -#define VEC_UNIMPEA (60) -#define VEC_UNIMPII (61) -#define VEC_USER (64) - -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x2000) -#define PS_M (0x1000) -#define PS_C (0x0001) - -/* structure for stack frames */ - -struct frame { - struct pt_regs ptregs; - union { - struct { - unsigned long iaddr; /* instruction address */ - } fmt2; - struct { - unsigned long effaddr; /* effective address */ - } fmt3; - struct { - unsigned long effaddr; /* effective address */ - unsigned long pc; /* pc of faulted instr */ - } fmt4; - struct { - unsigned long effaddr; /* effective address */ - unsigned short ssw; /* special status word */ - unsigned short wb3s; /* write back 3 status */ - unsigned short wb2s; /* write back 2 status */ - unsigned short wb1s; /* write back 1 status */ - unsigned long faddr; /* fault address */ - unsigned long wb3a; /* write back 3 address */ - unsigned long wb3d; /* write back 3 data */ - unsigned long wb2a; /* write back 2 address */ - unsigned long wb2d; /* write back 2 data */ - unsigned long wb1a; /* write back 1 address */ - unsigned long wb1dpd0; /* write back 1 data/push data 0*/ - unsigned long pd1; /* push data 1*/ - unsigned long pd2; /* push data 2*/ - unsigned long pd3; /* push data 3*/ - } fmt7; - struct { - unsigned long iaddr; /* instruction address */ - unsigned short int1[4]; /* internal registers */ - } fmt9; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[2]; - } fmta; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[4]; - unsigned long baddr; /* stage B address */ - unsigned short int4[2]; - unsigned long dibuf; /* data cycle input buffer */ - unsigned short int5[3]; - unsigned ver : 4; /* stack frame version # */ - unsigned int6:12; - unsigned short int7[18]; - } fmtb; - } un; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _M68KNOMMU_TRAPS_H */ diff --git a/arch/m68k/kernel/setup.c b/arch/m68k/kernel/setup.c index 303730afb1c..b3963ab3d14 100644 --- a/arch/m68k/kernel/setup.c +++ b/arch/m68k/kernel/setup.c @@ -359,12 +359,6 @@ void __init setup_arch(char **cmdline_p) isa_type = ISA_TYPE_Q40; isa_sex = 0; } -#ifdef CONFIG_GG2 - if (MACH_IS_AMIGA && AMIGAHW_PRESENT(GG2_ISA)) { - isa_type = ISA_TYPE_GG2; - isa_sex = 0; - } -#endif #ifdef CONFIG_AMIGA_PCMCIA if (MACH_IS_AMIGA && AMIGAHW_PRESENT(PCMCIA)) { isa_type = ISA_TYPE_AG; diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c index 2f431ece7b5..3db2e7f902a 100644 --- a/arch/m68k/kernel/sys_m68k.c +++ b/arch/m68k/kernel/sys_m68k.c @@ -12,7 +12,6 @@ #include <linux/mm.h> #include <linux/fs.h> #include <linux/smp.h> -#include <linux/smp_lock.h> #include <linux/sem.h> #include <linux/msg.h> #include <linux/shm.h> @@ -377,7 +376,6 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) struct vm_area_struct *vma; int ret = -EINVAL; - lock_kernel(); if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL || cache & ~FLUSH_CACHE_BOTH) goto out; @@ -446,7 +444,6 @@ sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len) } } out: - unlock_kernel(); return ret; } diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 4926b3856c1..06438dac08f 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -42,9 +42,7 @@ static inline int set_rtc_mmss(unsigned long nowtime) static irqreturn_t timer_interrupt(int irq, void *dummy) { do_timer(1); -#ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -#endif profile_tick(CPU_PROFILING); #ifdef CONFIG_HEARTBEAT diff --git a/arch/m68k/sun3/sun3ints.c b/arch/m68k/sun3/sun3ints.c index ad90393a336..2d9e21bd313 100644 --- a/arch/m68k/sun3/sun3ints.c +++ b/arch/m68k/sun3/sun3ints.c @@ -67,9 +67,7 @@ static irqreturn_t sun3_int5(int irq, void *dev_id) intersil_clear(); #endif do_timer(1); -#ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -#endif if (!(kstat_cpu(0).irqs[irq] % 20)) sun3_leds(led_pattern[(kstat_cpu(0).irqs[irq] % 160) / 20]); return IRQ_HANDLED; diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index a90acf5b0cd..7089dd9d843 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -50,9 +50,8 @@ irqreturn_t arch_timer_interrupt(int irq, void *dummy) write_sequnlock(&xtime_lock); -#ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); -#endif + return(IRQ_HANDLED); } #endif diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S index dd7d591f70e..cd79d7e92ce 100644 --- a/arch/m68knommu/platform/coldfire/entry.S +++ b/arch/m68knommu/platform/coldfire/entry.S @@ -112,7 +112,7 @@ ret_from_exception: andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ movel %d1,%a0 movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ - andl #_TIF_NEED_RESCHED,%d1 + andl #(1<<TIF_NEED_RESCHED),%d1 jeq Lkernel_return movel %a0@(TI_PREEMPTCOUNT),%d1 @@ -136,7 +136,7 @@ Luser_return: andl #-THREAD_SIZE,%d1 /* at base of kernel stack */ movel %d1,%a0 movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */ - andl #_TIF_WORK_MASK,%d1 + andl #0xefff,%d1 jne Lwork_to_do /* still work to do */ Lreturn: diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 1dc55ee2681..3691630931d 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -24,6 +24,33 @@ #include <prom.h> +static void alchemy_8250_pm(struct uart_port *port, unsigned int state, + unsigned int old_state) +{ + switch (state) { + case 0: + if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { + /* power-on sequence as suggested in the databooks */ + __raw_writel(0, port->membase + UART_MOD_CNTRL); + wmb(); + __raw_writel(1, port->membase + UART_MOD_CNTRL); + wmb(); + } + __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ + wmb(); + serial8250_do_pm(port, state, old_state); + break; + case 3: /* power off */ + serial8250_do_pm(port, state, old_state); + __raw_writel(0, port->membase + UART_MOD_CNTRL); + wmb(); + break; + default: + serial8250_do_pm(port, state, old_state); + break; + } +} + #define PORT(_base, _irq) \ { \ .mapbase = _base, \ @@ -33,6 +60,7 @@ .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ UPF_FIXED_TYPE, \ .type = PORT_16550A, \ + .pm = alchemy_8250_pm, \ } static struct plat_serial8250_port au1x00_uart_data[] = { diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index 5ef06a164a8..e5916a516e5 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -49,11 +49,6 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_uart0_inten; -static unsigned int sleep_uart0_fifoctl; -static unsigned int sleep_uart0_linectl; -static unsigned int sleep_uart0_clkdiv; -static unsigned int sleep_uart0_enable; static unsigned int sleep_usb[2]; static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; @@ -62,22 +57,6 @@ static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { - extern void save_au1xxx_intctl(void); - extern void pm_eth0_shutdown(void); - - /* - * Do the serial ports.....these really should be a pm_* - * registered function by the driver......but of course the - * standard serial driver doesn't understand our Au1xxx - * unique registers. - */ - sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER); - sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR); - sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); - sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); - sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); - au_sync(); - #ifndef CONFIG_SOC_AU1200 /* Shutdown USB host/device. */ sleep_usb[0] = au_readl(USB_HOST_CONFIG); @@ -175,20 +154,6 @@ static void restore_core_regs(void) au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); - - /* - * Enable the UART if it was enabled before sleep. - * I guess I should define module control bits........ - */ - if (sleep_uart0_enable & 0x02) { - au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); - au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); - au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); - au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); - au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); - } } void au_sleep(void) diff --git a/arch/mn10300/include/asm/ioctls.h b/arch/mn10300/include/asm/ioctls.h index cb8cf190223..0212f4b2255 100644 --- a/arch/mn10300/include/asm/ioctls.h +++ b/arch/mn10300/include/asm/ioctls.h @@ -1,88 +1,6 @@ #ifndef _ASM_IOCTLS_H #define _ASM_IOCTLS_H -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T', 0x2A, struct termios2) -#define TCSETS2 _IOW('T', 0x2B, struct termios2) -#define TCSETSW2 _IOW('T', 0x2C, struct termios2) -#define TCSETSF2 _IOW('T', 0x2D, struct termios2) -#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number - * (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ -#define FIOQSIZE 0x5460 - -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif /* _ASM_IOCTLS_H */ diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 6c67d9ebf16..19e5015e039 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -209,169 +209,6 @@ static int __init of_add_fixed_phys(void) arch_initcall(of_add_fixed_phys); #endif /* CONFIG_FIXED_PHY */ -static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type) -{ - if (!phy_type) - return FSL_USB2_PHY_NONE; - if (!strcasecmp(phy_type, "ulpi")) - return FSL_USB2_PHY_ULPI; - if (!strcasecmp(phy_type, "utmi")) - return FSL_USB2_PHY_UTMI; - if (!strcasecmp(phy_type, "utmi_wide")) - return FSL_USB2_PHY_UTMI_WIDE; - if (!strcasecmp(phy_type, "serial")) - return FSL_USB2_PHY_SERIAL; - - return FSL_USB2_PHY_NONE; -} - -static int __init fsl_usb_of_init(void) -{ - struct device_node *np; - unsigned int i = 0; - struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL, - *usb_dev_dr_client = NULL; - int ret; - - for_each_compatible_node(np, NULL, "fsl-usb2-mph") { - struct resource r[2]; - struct fsl_usb2_platform_data usb_data; - const unsigned char *prop = NULL; - - memset(&r, 0, sizeof(r)); - memset(&usb_data, 0, sizeof(usb_data)); - - ret = of_address_to_resource(np, 0, &r[0]); - if (ret) - goto err; - - of_irq_to_resource(np, 0, &r[1]); - - usb_dev_mph = - platform_device_register_simple("fsl-ehci", i, r, 2); - if (IS_ERR(usb_dev_mph)) { - ret = PTR_ERR(usb_dev_mph); - goto err; - } - - usb_dev_mph->dev.coherent_dma_mask = 0xffffffffUL; - usb_dev_mph->dev.dma_mask = &usb_dev_mph->dev.coherent_dma_mask; - - usb_data.operating_mode = FSL_USB2_MPH_HOST; - - prop = of_get_property(np, "port0", NULL); - if (prop) - usb_data.port_enables |= FSL_USB2_PORT0_ENABLED; - - prop = of_get_property(np, "port1", NULL); - if (prop) - usb_data.port_enables |= FSL_USB2_PORT1_ENABLED; - - prop = of_get_property(np, "phy_type", NULL); - usb_data.phy_mode = determine_usb_phy(prop); - - ret = - platform_device_add_data(usb_dev_mph, &usb_data, - sizeof(struct - fsl_usb2_platform_data)); - if (ret) - goto unreg_mph; - i++; - } - - for_each_compatible_node(np, NULL, "fsl-usb2-dr") { - struct resource r[2]; - struct fsl_usb2_platform_data usb_data; - const unsigned char *prop = NULL; - - if (!of_device_is_available(np)) - continue; - - memset(&r, 0, sizeof(r)); - memset(&usb_data, 0, sizeof(usb_data)); - - ret = of_address_to_resource(np, 0, &r[0]); - if (ret) - goto unreg_mph; - - of_irq_to_resource(np, 0, &r[1]); - - prop = of_get_property(np, "dr_mode", NULL); - - if (!prop || !strcmp(prop, "host")) { - usb_data.operating_mode = FSL_USB2_DR_HOST; - usb_dev_dr_host = platform_device_register_simple( - "fsl-ehci", i, r, 2); - if (IS_ERR(usb_dev_dr_host)) { - ret = PTR_ERR(usb_dev_dr_host); - goto err; - } - } else if (prop && !strcmp(prop, "peripheral")) { - usb_data.operating_mode = FSL_USB2_DR_DEVICE; - usb_dev_dr_client = platform_device_register_simple( - "fsl-usb2-udc", i, r, 2); - if (IS_ERR(usb_dev_dr_client)) { - ret = PTR_ERR(usb_dev_dr_client); - goto err; - } - } else if (prop && !strcmp(prop, "otg")) { - usb_data.operating_mode = FSL_USB2_DR_OTG; - usb_dev_dr_host = platform_device_register_simple( - "fsl-ehci", i, r, 2); - if (IS_ERR(usb_dev_dr_host)) { - ret = PTR_ERR(usb_dev_dr_host); - goto err; - } - usb_dev_dr_client = platform_device_register_simple( - "fsl-usb2-udc", i, r, 2); - if (IS_ERR(usb_dev_dr_client)) { - ret = PTR_ERR(usb_dev_dr_client); - goto err; - } - } else { - ret = -EINVAL; - goto err; - } - - prop = of_get_property(np, "phy_type", NULL); - usb_data.phy_mode = determine_usb_phy(prop); - - if (usb_dev_dr_host) { - usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL; - usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host-> - dev.coherent_dma_mask; - if ((ret = platform_device_add_data(usb_dev_dr_host, - &usb_data, sizeof(struct - fsl_usb2_platform_data)))) - goto unreg_dr; - } - if (usb_dev_dr_client) { - usb_dev_dr_client->dev.coherent_dma_mask = 0xffffffffUL; - usb_dev_dr_client->dev.dma_mask = &usb_dev_dr_client-> - dev.coherent_dma_mask; - if ((ret = platform_device_add_data(usb_dev_dr_client, - &usb_data, sizeof(struct - fsl_usb2_platform_data)))) - goto unreg_dr; - } - i++; - } - return 0; - -unreg_dr: - if (usb_dev_dr_host) - platform_device_unregister(usb_dev_dr_host); - if (usb_dev_dr_client) - platform_device_unregister(usb_dev_dr_client); -unreg_mph: - if (usb_dev_mph) - platform_device_unregister(usb_dev_mph); -err: - return ret; -} - -arch_initcall(fsl_usb_of_init); - #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) static __be32 __iomem *rstcr; diff --git a/arch/s390/include/asm/ioctls.h b/arch/s390/include/asm/ioctls.h index 2f3d8736361..960a4c1ebdf 100644 --- a/arch/s390/include/asm/ioctls.h +++ b/arch/s390/include/asm/ioctls.h @@ -1,94 +1,8 @@ -/* - * include/asm-s390/ioctls.h - * - * S390 version - * - * Derived from "include/asm-i386/ioctls.h" - */ - #ifndef __ARCH_S390_IOCTLS_H__ #define __ARCH_S390_IOCTLS_H__ -#include <asm/ioctl.h> - -/* 0x54 is just a magic number to make these relatively unique ('T') */ - -#define TCGETS 0x5401 -#define TCSETS 0x5402 -#define TCSETSW 0x5403 -#define TCSETSF 0x5404 -#define TCGETA 0x5405 -#define TCSETA 0x5406 -#define TCSETAW 0x5407 -#define TCSETAF 0x5408 -#define TCSBRK 0x5409 -#define TCXONC 0x540A -#define TCFLSH 0x540B -#define TIOCEXCL 0x540C -#define TIOCNXCL 0x540D -#define TIOCSCTTY 0x540E -#define TIOCGPGRP 0x540F -#define TIOCSPGRP 0x5410 -#define TIOCOUTQ 0x5411 -#define TIOCSTI 0x5412 -#define TIOCGWINSZ 0x5413 -#define TIOCSWINSZ 0x5414 -#define TIOCMGET 0x5415 -#define TIOCMBIS 0x5416 -#define TIOCMBIC 0x5417 -#define TIOCMSET 0x5418 -#define TIOCGSOFTCAR 0x5419 -#define TIOCSSOFTCAR 0x541A -#define FIONREAD 0x541B -#define TIOCINQ FIONREAD -#define TIOCLINUX 0x541C -#define TIOCCONS 0x541D -#define TIOCGSERIAL 0x541E -#define TIOCSSERIAL 0x541F -#define TIOCPKT 0x5420 -#define FIONBIO 0x5421 -#define TIOCNOTTY 0x5422 -#define TIOCSETD 0x5423 -#define TIOCGETD 0x5424 -#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ -#define TIOCSBRK 0x5427 /* BSD compatibility */ -#define TIOCCBRK 0x5428 /* BSD compatibility */ -#define TIOCGSID 0x5429 /* Return the session ID of FD */ -#define TCGETS2 _IOR('T',0x2A, struct termios2) -#define TCSETS2 _IOW('T',0x2B, struct termios2) -#define TCSETSW2 _IOW('T',0x2C, struct termios2) -#define TCSETSF2 _IOW('T',0x2D, struct termios2) -#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ -#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ -#define TIOCSIG _IOW('T',0x36, int) /* Generate signal on Pty slave */ - -#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ -#define FIOCLEX 0x5451 -#define FIOASYNC 0x5452 -#define TIOCSERCONFIG 0x5453 -#define TIOCSERGWILD 0x5454 -#define TIOCSERSWILD 0x5455 -#define TIOCGLCKTRMIOS 0x5456 -#define TIOCSLCKTRMIOS 0x5457 -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERGETLSR 0x5459 /* Get line status register */ -#define TIOCSERGETMULTI 0x545A /* Get multiport config */ -#define TIOCSERSETMULTI 0x545B /* Set multiport config */ - -#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ -#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ #define FIOQSIZE 0x545E -/* Used for packet mode */ -#define TIOCPKT_DATA 0 -#define TIOCPKT_FLUSHREAD 1 -#define TIOCPKT_FLUSHWRITE 2 -#define TIOCPKT_STOP 4 -#define TIOCPKT_START 8 -#define TIOCPKT_NOSTOP 16 -#define TIOCPKT_DOSTOP 32 -#define TIOCPKT_IOCTL 64 - -#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#include <asm-generic/ioctls.h> #endif diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index cd28f9ad910..f899e01a8ac 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -47,6 +47,20 @@ #ifdef CONFIG_SMP #define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x #define __my_cpu_offset percpu_read(this_cpu_off) + +/* + * Compared to the generic __my_cpu_offset version, the following + * saves one instruction and avoids clobbering a temp register. + */ +#define __this_cpu_ptr(ptr) \ +({ \ + unsigned long tcp_ptr__; \ + __verify_pcpu_ptr(ptr); \ + asm volatile("add " __percpu_arg(1) ", %0" \ + : "=r" (tcp_ptr__) \ + : "m" (this_cpu_off), "0" (ptr)); \ + (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ +}) #else #define __percpu_arg(x) "%P" #x #endif diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h index f686f49e8b7..8abde9ec90b 100644 --- a/arch/x86/include/asm/pgtable_32.h +++ b/arch/x86/include/asm/pgtable_32.h @@ -26,7 +26,7 @@ struct mm_struct; struct vm_area_struct; extern pgd_t swapper_pg_dir[1024]; -extern pgd_t trampoline_pg_dir[1024]; +extern pgd_t initial_page_table[1024]; static inline void pgtable_cache_init(void) { } static inline void check_pgt_cache(void) { } diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 7f3eba08e7d..169be8938b9 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -172,6 +172,4 @@ static inline void flush_tlb_kernel_range(unsigned long start, flush_tlb_all(); } -extern void zap_low_mappings(bool early); - #endif /* _ASM_X86_TLBFLUSH_H */ diff --git a/arch/x86/include/asm/trampoline.h b/arch/x86/include/asm/trampoline.h index 4dde797c057..f4500fb3b48 100644 --- a/arch/x86/include/asm/trampoline.h +++ b/arch/x86/include/asm/trampoline.h @@ -13,16 +13,13 @@ extern unsigned char *trampoline_base; extern unsigned long init_rsp; extern unsigned long initial_code; -extern unsigned long initial_page_table; extern unsigned long initial_gs; #define TRAMPOLINE_SIZE roundup(trampoline_end - trampoline_data, PAGE_SIZE) extern unsigned long setup_trampoline(void); -extern void __init setup_trampoline_page_table(void); extern void __init reserve_trampoline_memory(void); #else -static inline void setup_trampoline_page_table(void) {} static inline void reserve_trampoline_memory(void) {} #endif /* CONFIG_X86_TRAMPOLINE */ diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index e1252074ea4..74a847835ba 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -13,6 +13,11 @@ #include <asm/segment.h> #include <asm/desc.h> +#ifdef CONFIG_X86_32 +#include <asm/pgtable.h> +#include <asm/pgtable_32.h> +#endif + #include "realmode/wakeup.h" #include "sleep.h" @@ -91,7 +96,7 @@ int acpi_save_state_mem(void) #ifndef CONFIG_64BIT header->pmode_entry = (u32)&wakeup_pmode_return; - header->pmode_cr3 = (u32)(swsusp_pg_dir - __PAGE_OFFSET); + header->pmode_cr3 = (u32)__pa(&initial_page_table); saved_magic = 0x12345678; #else /* CONFIG_64BIT */ header->trampoline_segment = setup_trampoline() >> 4; diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c index 9a6ca239217..763310165fa 100644 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -18,6 +18,7 @@ #include <asm/apic.h> #include <asm/io_apic.h> #include <asm/bios_ebda.h> +#include <asm/tlbflush.h> static void __init i386_default_early_setup(void) { diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index fa8c1b8e09f..bcece91dd31 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -183,13 +183,12 @@ default_entry: #ifdef CONFIG_X86_PAE /* - * In PAE mode swapper_pg_dir is statically defined to contain enough - * entries to cover the VMSPLIT option (that is the top 1, 2 or 3 - * entries). The identity mapping is handled by pointing two PGD - * entries to the first kernel PMD. + * In PAE mode initial_page_table is statically defined to contain + * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3 + * entries). The identity mapping is handled by pointing two PGD entries + * to the first kernel PMD. * - * Note the upper half of each PMD or PTE are always zero at - * this stage. + * Note the upper half of each PMD or PTE are always zero at this stage. */ #define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */ @@ -197,7 +196,7 @@ default_entry: xorl %ebx,%ebx /* %ebx is kept at zero */ movl $pa(__brk_base), %edi - movl $pa(swapper_pg_pmd), %edx + movl $pa(initial_pg_pmd), %edx movl $PTE_IDENT_ATTR, %eax 10: leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */ @@ -226,14 +225,14 @@ default_entry: movl %eax, pa(max_pfn_mapped) /* Do early initialization of the fixmap area */ - movl $pa(swapper_pg_fixmap)+PDE_IDENT_ATTR,%eax - movl %eax,pa(swapper_pg_pmd+0x1000*KPMDS-8) + movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax + movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8) #else /* Not PAE */ page_pde_offset = (__PAGE_OFFSET >> 20); movl $pa(__brk_base), %edi - movl $pa(swapper_pg_dir), %edx + movl $pa(initial_page_table), %edx movl $PTE_IDENT_ATTR, %eax 10: leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */ @@ -257,8 +256,8 @@ page_pde_offset = (__PAGE_OFFSET >> 20); movl %eax, pa(max_pfn_mapped) /* Do early initialization of the fixmap area */ - movl $pa(swapper_pg_fixmap)+PDE_IDENT_ATTR,%eax - movl %eax,pa(swapper_pg_dir+0xffc) + movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax + movl %eax,pa(initial_page_table+0xffc) #endif jmp 3f /* @@ -334,7 +333,7 @@ ENTRY(startup_32_smp) /* * Enable paging */ - movl pa(initial_page_table), %eax + movl $pa(initial_page_table), %eax movl %eax,%cr3 /* set the page table pointer.. */ movl %cr0,%eax orl $X86_CR0_PG,%eax @@ -614,8 +613,6 @@ ignore_int: .align 4 ENTRY(initial_code) .long i386_start_kernel -ENTRY(initial_page_table) - .long pa(swapper_pg_dir) /* * BSS section @@ -623,20 +620,18 @@ ENTRY(initial_page_table) __PAGE_ALIGNED_BSS .align PAGE_SIZE_asm #ifdef CONFIG_X86_PAE -swapper_pg_pmd: +initial_pg_pmd: .fill 1024*KPMDS,4,0 #else -ENTRY(swapper_pg_dir) +ENTRY(initial_page_table) .fill 1024,4,0 #endif -swapper_pg_fixmap: +initial_pg_fixmap: .fill 1024,4,0 -#ifdef CONFIG_X86_TRAMPOLINE -ENTRY(trampoline_pg_dir) - .fill 1024,4,0 -#endif ENTRY(empty_zero_page) .fill 4096,1,0 +ENTRY(swapper_pg_dir) + .fill 1024,4,0 /* * This starts the data section. @@ -645,20 +640,20 @@ ENTRY(empty_zero_page) __PAGE_ALIGNED_DATA /* Page-aligned for the benefit of paravirt? */ .align PAGE_SIZE_asm -ENTRY(swapper_pg_dir) - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ +ENTRY(initial_page_table) + .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ # if KPMDS == 3 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR),0 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x1000),0 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x2000),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x2000),0 # elif KPMDS == 2 .long 0,0 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR),0 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR+0x1000),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 # elif KPMDS == 1 .long 0,0 .long 0,0 - .long pa(swapper_pg_pmd+PGD_IDENT_ATTR),0 + .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 # else # error "Kernel PMDs should be 1, 2 or 3" # endif diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 852b81967a3..d81cfebb848 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -477,8 +477,6 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, raw_smp_processor_id()); } - kgdb_correct_hw_break(); - return 0; } @@ -621,7 +619,12 @@ int kgdb_arch_init(void) static void kgdb_hw_overflow_handler(struct perf_event *event, int nmi, struct perf_sample_data *data, struct pt_regs *regs) { - kgdb_ll_trap(DIE_DEBUG, "debug", regs, 0, 0, SIGTRAP); + struct task_struct *tsk = current; + int i; + + for (i = 0; i < 4; i++) + if (breakinfo[i].enabled) + tsk->thread.debugreg6 |= (DR_TRAP0 << i); } void kgdb_arch_late(void) @@ -644,7 +647,7 @@ void kgdb_arch_late(void) if (breakinfo[i].pev) continue; breakinfo[i].pev = register_wide_hw_breakpoint(&attr, NULL); - if (IS_ERR(breakinfo[i].pev)) { + if (IS_ERR((void * __force)breakinfo[i].pev)) { printk(KERN_ERR "kgdb: Could not allocate hw" "breakpoints\nDisabling the kernel debugger\n"); breakinfo[i].pev = NULL; diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 7a4cf14223b..f7f53dcd3e0 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -371,16 +371,10 @@ void machine_real_restart(const unsigned char *code, int length) CMOS_WRITE(0x00, 0x8f); spin_unlock(&rtc_lock); - /* Remap the kernel at virtual address zero, as well as offset zero - from the kernel segment. This assumes the kernel segment starts at - virtual address PAGE_OFFSET. */ - memcpy(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, - sizeof(swapper_pg_dir [0]) * KERNEL_PGD_PTRS); - /* - * Use `swapper_pg_dir' as our page directory. + * Switch back to the initial page table. */ - load_cr3(swapper_pg_dir); + load_cr3(initial_page_table); /* Write 0x1234 to absolute memory location 0x472. The BIOS reads this on booting to tell it to "Bypass memory test (also warm diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 420e6419785..95a32746fbf 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -700,6 +700,17 @@ void __init setup_arch(char **cmdline_p) #ifdef CONFIG_X86_32 memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data)); visws_early_detect(); + + /* + * copy kernel address range established so far and switch + * to the proper swapper page table + */ + clone_pgd_range(swapper_pg_dir + KERNEL_PGD_BOUNDARY, + initial_page_table + KERNEL_PGD_BOUNDARY, + KERNEL_PGD_PTRS); + + load_cr3(swapper_pg_dir); + __flush_tlb_all(); #else printk(KERN_INFO "Command line: %s\n", boot_command_line); #endif @@ -985,7 +996,12 @@ void __init setup_arch(char **cmdline_p) paging_init(); x86_init.paging.pagetable_setup_done(swapper_pg_dir); - setup_trampoline_page_table(); +#ifdef CONFIG_X86_32 + /* sync back kernel address range */ + clone_pgd_range(initial_page_table + KERNEL_PGD_BOUNDARY, + swapper_pg_dir + KERNEL_PGD_BOUNDARY, + KERNEL_PGD_PTRS); +#endif tboot_probe(); diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index dfb50890b5b..6af118511b4 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -299,22 +299,16 @@ notrace static void __cpuinit start_secondary(void *unused) * fragile that we want to limit the things done here to the * most necessary things. */ + cpu_init(); + preempt_disable(); + smp_callin(); #ifdef CONFIG_X86_32 - /* - * Switch away from the trampoline page-table - * - * Do this before cpu_init() because it needs to access per-cpu - * data which may not be mapped in the trampoline page-table. - */ + /* switch away from the initial page table */ load_cr3(swapper_pg_dir); __flush_tlb_all(); #endif - cpu_init(); - preempt_disable(); - smp_callin(); - /* otherwise gcc will move up smp_processor_id before the cpu_init */ barrier(); /* @@ -785,7 +779,6 @@ do_rest: #ifdef CONFIG_X86_32 /* Stack for startup_32 can be just as for start_secondary onwards */ irq_ctx_init(cpu); - initial_page_table = __pa(&trampoline_pg_dir); #else clear_tsk_thread_flag(c_idle.idle, TIF_FORK); initial_gs = per_cpu_offset(cpu); @@ -934,7 +927,6 @@ int __cpuinit native_cpu_up(unsigned int cpu) per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; err = do_boot_cpu(apicid, cpu); - if (err) { pr_debug("do_boot_cpu failed %d\n", err); return -EIO; diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c index 4c3da5674e6..a375616d77f 100644 --- a/arch/x86/kernel/trampoline.c +++ b/arch/x86/kernel/trampoline.c @@ -38,19 +38,3 @@ unsigned long __trampinit setup_trampoline(void) memcpy(trampoline_base, trampoline_data, TRAMPOLINE_SIZE); return virt_to_phys(trampoline_base); } - -void __init setup_trampoline_page_table(void) -{ -#ifdef CONFIG_X86_32 - /* Copy kernel address range */ - clone_pgd_range(trampoline_pg_dir + KERNEL_PGD_BOUNDARY, - swapper_pg_dir + KERNEL_PGD_BOUNDARY, - KERNEL_PGD_PTRS); - - /* Initialize low mappings */ - clone_pgd_range(trampoline_pg_dir, - swapper_pg_dir + KERNEL_PGD_BOUNDARY, - min_t(unsigned long, KERNEL_PGD_PTRS, - KERNEL_PGD_BOUNDARY)); -#endif -} diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index 5d0a6711c28..0e969f9f401 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -528,48 +528,6 @@ static void __init pagetable_init(void) permanent_kmaps_init(pgd_base); } -#ifdef CONFIG_ACPI_SLEEP -/* - * ACPI suspend needs this for resume, because things like the intel-agp - * driver might have split up a kernel 4MB mapping. - */ -char swsusp_pg_dir[PAGE_SIZE] - __attribute__ ((aligned(PAGE_SIZE))); - -static inline void save_pg_dir(void) -{ - copy_page(swsusp_pg_dir, swapper_pg_dir); -} -#else /* !CONFIG_ACPI_SLEEP */ -static inline void save_pg_dir(void) -{ -} -#endif /* !CONFIG_ACPI_SLEEP */ - -void zap_low_mappings(bool early) -{ - int i; - - /* - * Zap initial low-memory mappings. - * - * Note that "pgd_clear()" doesn't do it for - * us, because pgd_clear() is a no-op on i386. - */ - for (i = 0; i < KERNEL_PGD_BOUNDARY; i++) { -#ifdef CONFIG_X86_PAE - set_pgd(swapper_pg_dir+i, __pgd(1 + __pa(empty_zero_page))); -#else - set_pgd(swapper_pg_dir+i, __pgd(0)); -#endif - } - - if (early) - __flush_tlb(); - else - flush_tlb_all(); -} - pteval_t __supported_pte_mask __read_mostly = ~(_PAGE_NX | _PAGE_GLOBAL | _PAGE_IOMAP); EXPORT_SYMBOL_GPL(__supported_pte_mask); @@ -882,9 +840,6 @@ void __init mem_init(void) if (boot_cpu_data.wp_works_ok < 0) test_wp_bit(); - - save_pg_dir(); - zap_low_mappings(true); } #ifdef CONFIG_MEMORY_HOTPLUG |