diff options
Diffstat (limited to 'drivers/video/mcde/mcde_regs.h')
| -rw-r--r-- | drivers/video/mcde/mcde_regs.h | 309 |
1 files changed, 64 insertions, 245 deletions
diff --git a/drivers/video/mcde/mcde_regs.h b/drivers/video/mcde/mcde_regs.h index 7f28c26360b..06e96e45952 100644 --- a/drivers/video/mcde/mcde_regs.h +++ b/drivers/video/mcde/mcde_regs.h @@ -5,14 +5,6 @@ (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) #define MCDE_CR 0x00000000 -#define MCDE_CR_DSICMD2_EN_V1_SHIFT 0 -#define MCDE_CR_DSICMD2_EN_V1_MASK 0x00000001 -#define MCDE_CR_DSICMD2_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSICMD2_EN_V1, __x) -#define MCDE_CR_DSICMD1_EN_V1_SHIFT 1 -#define MCDE_CR_DSICMD1_EN_V1_MASK 0x00000002 -#define MCDE_CR_DSICMD1_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSICMD1_EN_V1, __x) #define MCDE_CR_DSI0_EN_V3_SHIFT 0 #define MCDE_CR_DSI0_EN_V3_MASK 0x00000001 #define MCDE_CR_DSI0_EN_V3(__x) \ @@ -21,42 +13,10 @@ #define MCDE_CR_DSI1_EN_V3_MASK 0x00000002 #define MCDE_CR_DSI1_EN_V3(__x) \ MCDE_VAL2REG(MCDE_CR, DSI1_EN_V3, __x) -#define MCDE_CR_DSICMD0_EN_V1_SHIFT 2 -#define MCDE_CR_DSICMD0_EN_V1_MASK 0x00000004 -#define MCDE_CR_DSICMD0_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSICMD0_EN_V1, __x) -#define MCDE_CR_DSIVID2_EN_V1_SHIFT 3 -#define MCDE_CR_DSIVID2_EN_V1_MASK 0x00000008 -#define MCDE_CR_DSIVID2_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSIVID2_EN_V1, __x) -#define MCDE_CR_DSIVID1_EN_V1_SHIFT 4 -#define MCDE_CR_DSIVID1_EN_V1_MASK 0x00000010 -#define MCDE_CR_DSIVID1_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSIVID1_EN_V1, __x) -#define MCDE_CR_DSIVID0_EN_V1_SHIFT 5 -#define MCDE_CR_DSIVID0_EN_V1_MASK 0x00000020 -#define MCDE_CR_DSIVID0_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DSIVID0_EN_V1, __x) -#define MCDE_CR_DBIC1_EN_V1_SHIFT 6 -#define MCDE_CR_DBIC1_EN_V1_MASK 0x00000040 -#define MCDE_CR_DBIC1_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DBIC1_EN_V1, __x) -#define MCDE_CR_DBIC0_EN_V1_SHIFT 7 -#define MCDE_CR_DBIC0_EN_V1_MASK 0x00000080 -#define MCDE_CR_DBIC0_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DBIC0_EN_V1, __x) #define MCDE_CR_DBI_EN_V3_SHIFT 7 #define MCDE_CR_DBI_EN_V3_MASK 0x00000080 #define MCDE_CR_DBI_EN_V3(__x) \ MCDE_VAL2REG(MCDE_CR, DBI_EN_V3, __x) -#define MCDE_CR_DPIB_EN_V1_SHIFT 8 -#define MCDE_CR_DPIB_EN_V1_MASK 0x00000100 -#define MCDE_CR_DPIB_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DPIB_EN_V1, __x) -#define MCDE_CR_DPIA_EN_V1_SHIFT 9 -#define MCDE_CR_DPIA_EN_V1_MASK 0x00000200 -#define MCDE_CR_DPIA_EN_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, DPIA_EN_V1, __x) #define MCDE_CR_DPI_EN_V3_SHIFT 9 #define MCDE_CR_DPI_EN_V3_MASK 0x00000200 #define MCDE_CR_DPI_EN_V3(__x) \ @@ -65,14 +25,6 @@ #define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000 #define MCDE_CR_IFIFOCTRLEN(__x) \ MCDE_VAL2REG(MCDE_CR, IFIFOCTRLEN, __x) -#define MCDE_CR_F01MUX_V1_SHIFT 16 -#define MCDE_CR_F01MUX_V1_MASK 0x00010000 -#define MCDE_CR_F01MUX_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, F01MUX_V1, __x) -#define MCDE_CR_FABMUX_V1_SHIFT 17 -#define MCDE_CR_FABMUX_V1_MASK 0x00020000 -#define MCDE_CR_FABMUX_V1(__x) \ - MCDE_VAL2REG(MCDE_CR, FABMUX_V1, __x) #define MCDE_CR_AUTOCLKG_EN_SHIFT 30 #define MCDE_CR_AUTOCLKG_EN_MASK 0x40000000 #define MCDE_CR_AUTOCLKG_EN(__x) \ @@ -114,22 +66,6 @@ #define MCDE_CONF0_SYNCMUX7_MASK 0x00000080 #define MCDE_CONF0_SYNCMUX7(__x) \ MCDE_VAL2REG(MCDE_CONF0, SYNCMUX7, __x) -#define MCDE_CONF0_SWAP_A_C0_V1_SHIFT 8 -#define MCDE_CONF0_SWAP_A_C0_V1_MASK 0x00000100 -#define MCDE_CONF0_SWAP_A_C0_V1(__x) \ - MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0_V1, __x) -#define MCDE_CONF0_SWAP_B_C1_V1_SHIFT 9 -#define MCDE_CONF0_SWAP_B_C1_V1_MASK 0x00000200 -#define MCDE_CONF0_SWAP_B_C1_V1(__x) \ - MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1_V1, __x) -#define MCDE_CONF0_FSYNCTRLA_V1_SHIFT 10 -#define MCDE_CONF0_FSYNCTRLA_V1_MASK 0x00000400 -#define MCDE_CONF0_FSYNCTRLA_V1(__x) \ - MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA_V1, __x) -#define MCDE_CONF0_FSYNCTRLB_V1_SHIFT 11 -#define MCDE_CONF0_FSYNCTRLB_V1_MASK 0x00000800 -#define MCDE_CONF0_FSYNCTRLB_V1(__x) \ - MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB_V1, __x) #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL(__x) \ @@ -2703,76 +2639,51 @@ #define MCDE_CHNL3BCKGNDCOL_R_MASK 0x00FF0000 #define MCDE_CHNL3BCKGNDCOL_R(__x) \ MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, R, __x) -#define MCDE_CHNL0PRIO_V1 0x00000614 -#define MCDE_CHNL0PRIO_V1_GROUPOFFSET 0x20 -#define MCDE_CHNL0PRIO_V1_CHNLPRIO_SHIFT 0 -#define MCDE_CHNL0PRIO_V1_CHNLPRIO_MASK 0x0000000F -#define MCDE_CHNL0PRIO_V1_CHNLPRIO(__x) \ - MCDE_VAL2REG(MCDE_CHNL0PRIO_V1, CHNLPRIO, __x) -#define MCDE_CHNL1PRIO_V1 0x00000634 -#define MCDE_CHNL1PRIO_V1_CHNLPRIO_SHIFT 0 -#define MCDE_CHNL1PRIO_V1_CHNLPRIO_MASK 0x0000000F -#define MCDE_CHNL1PRIO_V1_CHNLPRIO(__x) \ - MCDE_VAL2REG(MCDE_CHNL1PRIO_V1, CHNLPRIO, __x) -#define MCDE_CHNL2PRIO_V1 0x00000654 -#define MCDE_CHNL2PRIO_V1_CHNLPRIO_SHIFT 0 -#define MCDE_CHNL2PRIO_V1_CHNLPRIO_MASK 0x0000000F -#define MCDE_CHNL2PRIO_V1_CHNLPRIO(__x) \ - MCDE_VAL2REG(MCDE_CHNL2PRIO_V1, CHNLPRIO, __x) -#define MCDE_CHNL3PRIO_V1 0x00000674 -#define MCDE_CHNL3PRIO_V1_CHNLPRIO_SHIFT 0 -#define MCDE_CHNL3PRIO_V1_CHNLPRIO_MASK 0x0000000F -#define MCDE_CHNL3PRIO_V1_CHNLPRIO(__x) \ - MCDE_VAL2REG(MCDE_CHNL3PRIO_V1, CHNLPRIO, __x) -#define MCDE_CHNL0MUXING_V2 0x00000614 -#define MCDE_CHNL0MUXING_V2_GROUPOFFSET 0x20 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_SHIFT 0 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_MASK 0x00000007 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_A 0 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_B 1 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C0 2 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C1 3 -#define MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, \ - MCDE_CHNL0MUXING_V2_FIFO_ID_##__x) -#define MCDE_CHNL0MUXING_V2_FIFO_ID(__x) \ - MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, __x) -#define MCDE_CHNL1MUXING_V2 0x00000634 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_SHIFT 0 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_MASK 0x00000007 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_A 0 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_B 1 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C0 2 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C1 3 -#define MCDE_CHNL1MUXING_V2_FIFO_ID_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, \ - MCDE_CHNL1MUXING_V2_FIFO_ID_##__x) -#define MCDE_CHNL1MUXING_V2_FIFO_ID(__x) \ - MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, __x) -#define MCDE_CHNL2MUXING_V2 0x00000654 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_SHIFT 0 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_MASK 0x00000007 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_A 0 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_B 1 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C0 2 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C1 3 -#define MCDE_CHNL2MUXING_V2_FIFO_ID_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, \ - MCDE_CHNL2MUXING_V2_FIFO_ID_##__x) -#define MCDE_CHNL2MUXING_V2_FIFO_ID(__x) \ - MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, __x) -#define MCDE_CHNL3MUXING_V2 0x00000674 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_SHIFT 0 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_MASK 0x00000007 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_A 0 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_B 1 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C0 2 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C1 3 -#define MCDE_CHNL3MUXING_V2_FIFO_ID_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, \ - MCDE_CHNL3MUXING_V2_FIFO_ID_##__x) -#define MCDE_CHNL3MUXING_V2_FIFO_ID(__x) \ - MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, __x) +#define MCDE_CHNL0MUXING 0x00000614 +#define MCDE_CHNL0MUXING_GROUPOFFSET 0x20 +#define MCDE_CHNL0MUXING_FIFO_ID_SHIFT 0 +#define MCDE_CHNL0MUXING_FIFO_ID_MASK 0x00000007 +#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_A 0 +#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_B 1 +#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_C0 2 +#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_C1 3 +#define MCDE_CHNL0MUXING_FIFO_ID_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL0MUXING, FIFO_ID, MCDE_CHNL0MUXING_FIFO_ID_##__x) +#define MCDE_CHNL0MUXING_FIFO_ID(__x) \ + MCDE_VAL2REG(MCDE_CHNL0MUXING, FIFO_ID, __x) +#define MCDE_CHNL1MUXING 0x00000634 +#define MCDE_CHNL1MUXING_FIFO_ID_SHIFT 0 +#define MCDE_CHNL1MUXING_FIFO_ID_MASK 0x00000007 +#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_A 0 +#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_B 1 +#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_C0 2 +#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_C1 3 +#define MCDE_CHNL1MUXING_FIFO_ID_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL1MUXING, FIFO_ID, MCDE_CHNL1MUXING_FIFO_ID_##__x) +#define MCDE_CHNL1MUXING_FIFO_ID(__x) \ + MCDE_VAL2REG(MCDE_CHNL1MUXING, FIFO_ID, __x) +#define MCDE_CHNL2MUXING 0x00000654 +#define MCDE_CHNL2MUXING_FIFO_ID_SHIFT 0 +#define MCDE_CHNL2MUXING_FIFO_ID_MASK 0x00000007 +#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_A 0 +#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_B 1 +#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_C0 2 +#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_C1 3 +#define MCDE_CHNL2MUXING_FIFO_ID_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL2MUXING, FIFO_ID, MCDE_CHNL2MUXING_FIFO_ID_##__x) +#define MCDE_CHNL2MUXING_FIFO_ID(__x) \ + MCDE_VAL2REG(MCDE_CHNL2MUXING, FIFO_ID, __x) +#define MCDE_CHNL3MUXING 0x00000674 +#define MCDE_CHNL3MUXING_FIFO_ID_SHIFT 0 +#define MCDE_CHNL3MUXING_FIFO_ID_MASK 0x00000007 +#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_A 0 +#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_B 1 +#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_C0 2 +#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_C1 3 +#define MCDE_CHNL3MUXING_FIFO_ID_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL3MUXING, FIFO_ID, MCDE_CHNL3MUXING_FIFO_ID_##__x) +#define MCDE_CHNL3MUXING_FIFO_ID(__x) \ + MCDE_VAL2REG(MCDE_CHNL3MUXING, FIFO_ID, __x) #define MCDE_CRA0 0x00000800 #define MCDE_CRA0_GROUPOFFSET 0x200 #define MCDE_CRA0_FLOEN_SHIFT 0 @@ -2857,22 +2768,6 @@ #define MCDE_CRA0_ROTEN_MASK 0x01000000 #define MCDE_CRA0_ROTEN(__x) \ MCDE_VAL2REG(MCDE_CRA0, ROTEN, __x) -#define MCDE_CRA0_ROTBURSTSIZE_V1_SHIFT 25 -#define MCDE_CRA0_ROTBURSTSIZE_V1_MASK 0x0E000000 -#define MCDE_CRA0_ROTBURSTSIZE_V1_1W 0 -#define MCDE_CRA0_ROTBURSTSIZE_V1_2W 1 -#define MCDE_CRA0_ROTBURSTSIZE_V1_4W 2 -#define MCDE_CRA0_ROTBURSTSIZE_V1_8W 3 -#define MCDE_CRA0_ROTBURSTSIZE_V1_16W 4 -#define MCDE_CRA0_ROTBURSTSIZE_V1_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, \ - MCDE_CRA0_ROTBURSTSIZE_V1_##__x) -#define MCDE_CRA0_ROTBURSTSIZE_V1(__x) \ - MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, __x) -#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_SHIFT 28 -#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_MASK 0x10000000 -#define MCDE_CRA0_ROTBURSTSIZE_HW_V1(__x) \ - MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW_V1, __x) #define MCDE_CRB0 0x00000A00 #define MCDE_CRB0_FLOEN_SHIFT 0 #define MCDE_CRB0_FLOEN_MASK 0x00000001 @@ -2956,22 +2851,6 @@ #define MCDE_CRB0_ROTEN_MASK 0x01000000 #define MCDE_CRB0_ROTEN(__x) \ MCDE_VAL2REG(MCDE_CRB0, ROTEN, __x) -#define MCDE_CRB0_ROTBURSTSIZE_V1_SHIFT 25 -#define MCDE_CRB0_ROTBURSTSIZE_V1_MASK 0x0E000000 -#define MCDE_CRB0_ROTBURSTSIZE_V1_1W 0 -#define MCDE_CRB0_ROTBURSTSIZE_V1_2W 1 -#define MCDE_CRB0_ROTBURSTSIZE_V1_4W 2 -#define MCDE_CRB0_ROTBURSTSIZE_V1_8W 3 -#define MCDE_CRB0_ROTBURSTSIZE_V1_16W 4 -#define MCDE_CRB0_ROTBURSTSIZE_V1_ENUM(__x) \ - MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, \ - MCDE_CRB0_ROTBURSTSIZE_V1_##__x) -#define MCDE_CRB0_ROTBURSTSIZE_V1(__x) \ - MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, __x) -#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_SHIFT 28 -#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_MASK 0x10000000 -#define MCDE_CRB0_ROTBURSTSIZE_HW_V1(__x) \ - MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW_V1, __x) #define MCDE_CRA1 0x00000804 #define MCDE_CRA1_GROUPOFFSET 0x200 #define MCDE_CRA1_PCD_SHIFT 0 @@ -3033,10 +2912,6 @@ MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x) #define MCDE_CRA1_CLKTYPE(__x) \ MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, __x) -#define MCDE_CRA1_TEFFECTEN_V1_SHIFT 31 -#define MCDE_CRA1_TEFFECTEN_V1_MASK 0x80000000 -#define MCDE_CRA1_TEFFECTEN_V1(__x) \ - MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN_V1, __x) #define MCDE_CRB1 0x00000A04 #define MCDE_CRB1_PCD_SHIFT 0 #define MCDE_CRB1_PCD_MASK 0x000003FF @@ -3097,10 +2972,6 @@ MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x) #define MCDE_CRB1_CLKTYPE(__x) \ MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, __x) -#define MCDE_CRB1_TEFFECTEN_V1_SHIFT 31 -#define MCDE_CRB1_TEFFECTEN_V1_MASK 0x80000000 -#define MCDE_CRB1_TEFFECTEN_V1(__x) \ - MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN_V1, __x) #define MCDE_COLKEYA 0x00000808 #define MCDE_COLKEYA_GROUPOFFSET 0x200 #define MCDE_COLKEYA_KEYB_SHIFT 0 @@ -3336,25 +3207,25 @@ #define MCDE_FFCOEF2_T2_MASK 0x0F000000 #define MCDE_FFCOEF2_T2(__x) \ MCDE_VAL2REG(MCDE_FFCOEF2, T2, __x) -#define MCDE_MCDE_WDATAA_V2 0x00000834 -#define MCDE_MCDE_WDATAA_V2_GROUPOFFSET 0x200 -#define MCDE_MCDE_WDATAA_V2_DC_SHIFT 24 -#define MCDE_MCDE_WDATAA_V2_DC_MASK 0x01000000 -#define MCDE_MCDE_WDATAA_V2_DC(__x) \ - MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DC, __x) -#define MCDE_MCDE_WDATAA_V2_DATAVALUE_SHIFT 0 -#define MCDE_MCDE_WDATAA_V2_DATAVALUE_MASK 0x00FFFFFF -#define MCDE_MCDE_WDATAA_V2_DATAVALUE(__x) \ - MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DATAVALUE, __x) -#define MCDE_MCDE_WDATAB_V2 0x00000A34 -#define MCDE_MCDE_WDATAB_V2_DC_SHIFT 24 -#define MCDE_MCDE_WDATAB_V2_DC_MASK 0x01000000 -#define MCDE_MCDE_WDATAB_V2_DC(__x) \ - MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DC, __x) -#define MCDE_MCDE_WDATAB_V2_DATAVALUE_SHIFT 0 -#define MCDE_MCDE_WDATAB_V2_DATAVALUE_MASK 0x00FFFFFF -#define MCDE_MCDE_WDATAB_V2_DATAVALUE(__x) \ - MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DATAVALUE, __x) +#define MCDE_MCDE_WDATAA 0x00000834 +#define MCDE_MCDE_WDATAA_GROUPOFFSET 0x200 +#define MCDE_MCDE_WDATAA_DC_SHIFT 24 +#define MCDE_MCDE_WDATAA_DC_MASK 0x01000000 +#define MCDE_MCDE_WDATAA_DC(__x) \ + MCDE_VAL2REG(MCDE_MCDE_WDATAA, DC, __x) +#define MCDE_MCDE_WDATAA_DATAVALUE_SHIFT 0 +#define MCDE_MCDE_WDATAA_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_MCDE_WDATAA_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_MCDE_WDATAA, DATAVALUE, __x) +#define MCDE_MCDE_WDATAB 0x00000A34 +#define MCDE_MCDE_WDATAB_DC_SHIFT 24 +#define MCDE_MCDE_WDATAB_DC_MASK 0x01000000 +#define MCDE_MCDE_WDATAB_DC(__x) \ + MCDE_VAL2REG(MCDE_MCDE_WDATAB, DC, __x) +#define MCDE_MCDE_WDATAB_DATAVALUE_SHIFT 0 +#define MCDE_MCDE_WDATAB_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_MCDE_WDATAB_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_MCDE_WDATAB, DATAVALUE, __x) #define MCDE_TVCRA 0x00000838 #define MCDE_TVCRA_GROUPOFFSET 0x200 #define MCDE_TVCRA_SEL_MOD_SHIFT 0 @@ -4651,17 +4522,6 @@ #define MCDE_DOTR1_DODEACT_MASK 0x0000FF00 #define MCDE_DOTR1_DODEACT(__x) \ MCDE_VAL2REG(MCDE_DOTR1, DODEACT, __x) -#define MCDE_WCMDC0_V1 0x00000C8C -#define MCDE_WCMDC0_V1_GROUPOFFSET 0x4 -#define MCDE_WCMDC0_V1_COMMANDVALUE_SHIFT 0 -#define MCDE_WCMDC0_V1_COMMANDVALUE_MASK 0x00FFFFFF -#define MCDE_WCMDC0_V1_COMMANDVALUE(__x) \ - MCDE_VAL2REG(MCDE_WCMDC0_V1, COMMANDVALUE, __x) -#define MCDE_WCMDC1_V1 0x00000C90 -#define MCDE_WCMDC1_V1_COMMANDVALUE_SHIFT 0 -#define MCDE_WCMDC1_V1_COMMANDVALUE_MASK 0x00FFFFFF -#define MCDE_WCMDC1_V1_COMMANDVALUE(__x) \ - MCDE_VAL2REG(MCDE_WCMDC1_V1, COMMANDVALUE, __x) #define MCDE_WDATADC0 0x00000C94 #define MCDE_WDATADC0_GROUPOFFSET 0x4 #define MCDE_WDATADC0_DATAVALUE_SHIFT 0 @@ -4692,47 +4552,6 @@ #define MCDE_RDATADC1_STARTREAD_MASK 0x00010000 #define MCDE_RDATADC1_STARTREAD(__x) \ MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x) -#define MCDE_STATC_V1 0x00000CA4 -#define MCDE_STATC_V1_STATBUSY0_SHIFT 0 -#define MCDE_STATC_V1_STATBUSY0_MASK 0x00000001 -#define MCDE_STATC_V1_STATBUSY0(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY0, __x) -#define MCDE_STATC_V1_FIFOEMPTY0_SHIFT 1 -#define MCDE_STATC_V1_FIFOEMPTY0_MASK 0x00000002 -#define MCDE_STATC_V1_FIFOEMPTY0(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY0, __x) -#define MCDE_STATC_V1_FIFOFULL0_SHIFT 2 -#define MCDE_STATC_V1_FIFOFULL0_MASK 0x00000004 -#define MCDE_STATC_V1_FIFOFULL0(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL0, __x) -#define MCDE_STATC_V1_FIFOCMDEMPTY0_SHIFT 3 -#define MCDE_STATC_V1_FIFOCMDEMPTY0_MASK 0x00000008 -#define MCDE_STATC_V1_FIFOCMDEMPTY0(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY0, __x) -#define MCDE_STATC_V1_FIFOCMDFULL0_SHIFT 4 -#define MCDE_STATC_V1_FIFOCMDFULL0_MASK 0x00000010 -#define MCDE_STATC_V1_FIFOCMDFULL0(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL0, __x) -#define MCDE_STATC_V1_STATBUSY1_SHIFT 5 -#define MCDE_STATC_V1_STATBUSY1_MASK 0x00000020 -#define MCDE_STATC_V1_STATBUSY1(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY1, __x) -#define MCDE_STATC_V1_FIFOEMPTY1_SHIFT 6 -#define MCDE_STATC_V1_FIFOEMPTY1_MASK 0x00000040 -#define MCDE_STATC_V1_FIFOEMPTY1(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY1, __x) -#define MCDE_STATC_V1_FIFOFULL1_SHIFT 7 -#define MCDE_STATC_V1_FIFOFULL1_MASK 0x00000080 -#define MCDE_STATC_V1_FIFOFULL1(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL1, __x) -#define MCDE_STATC_V1_FIFOCMDEMPTY1_SHIFT 8 -#define MCDE_STATC_V1_FIFOCMDEMPTY1_MASK 0x00000100 -#define MCDE_STATC_V1_FIFOCMDEMPTY1(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY1, __x) -#define MCDE_STATC_V1_FIFOCMDFULL1_SHIFT 9 -#define MCDE_STATC_V1_FIFOCMDFULL1_MASK 0x00000200 -#define MCDE_STATC_V1_FIFOCMDFULL1(__x) \ - MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL1, __x) #define MCDE_CTRLC0 0x00000CA8 #define MCDE_CTRLC0_GROUPOFFSET 0x4 #define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0 |