diff options
Diffstat (limited to 'include/video')
-rw-r--r-- | include/video/av8100.h | 549 | ||||
-rw-r--r-- | include/video/b2r2_blt.h | 617 | ||||
-rw-r--r-- | include/video/hdmi.h | 205 | ||||
-rw-r--r-- | include/video/mcde.h | 448 | ||||
-rw-r--r-- | include/video/mcde_display-ab8500.h | 24 | ||||
-rw-r--r-- | include/video/mcde_display-av8100.h | 53 | ||||
-rw-r--r-- | include/video/mcde_display-generic_dsi.h | 35 | ||||
-rw-r--r-- | include/video/mcde_display-sony_acx424akp_dsi.h | 26 | ||||
-rw-r--r-- | include/video/mcde_display-vuib500-dpi.h | 31 | ||||
-rw-r--r-- | include/video/mcde_display.h | 149 | ||||
-rw-r--r-- | include/video/mcde_dss.h | 81 | ||||
-rw-r--r-- | include/video/mcde_fb.h | 65 |
12 files changed, 2283 insertions, 0 deletions
diff --git a/include/video/av8100.h b/include/video/av8100.h new file mode 100644 index 00000000000..23e96a0b871 --- /dev/null +++ b/include/video/av8100.h @@ -0,0 +1,549 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * AV8100 driver + * + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __AV8100__H__ +#define __AV8100__H__ + +#define AV8100_CEC_MESSAGE_SIZE 16 +#define AV8100_HDCP_SEND_KEY_SIZE 16 +#define AV8100_INFOFRAME_SIZE 28 +#define AV8100_FUSE_KEY_SIZE 16 +#define AV8100_CHIPVER_1 1 +#define AV8100_CHIPVER_2 2 + +struct av8100_platform_data { + unsigned gpio_base; + int irq; + int reset; + const char *inputclk_id; + const char *regulator_pwr_id; + bool alt_powerupseq; + unsigned char mclk_freq; +}; + +enum av8100_command_type { + AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1, + AV8100_COMMAND_AUDIO_INPUT_FORMAT, + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, + AV8100_COMMAND_VIDEO_SCALING_FORMAT, + AV8100_COMMAND_COLORSPACECONVERSION, + AV8100_COMMAND_CEC_MESSAGE_WRITE, + AV8100_COMMAND_CEC_MESSAGE_READ_BACK, + AV8100_COMMAND_DENC, + AV8100_COMMAND_HDMI, + AV8100_COMMAND_HDCP_SENDKEY, + AV8100_COMMAND_HDCP_MANAGEMENT, + AV8100_COMMAND_INFOFRAMES, + AV8100_COMMAND_EDID_SECTION_READBACK, + AV8100_COMMAND_PATTERNGENERATOR, + AV8100_COMMAND_FUSE_AES_KEY, +}; + +enum interface_type { + I2C_INTERFACE = 0x0, + DSI_INTERFACE = 0x1, +}; + +enum av8100_dsi_mode { + AV8100_HDMI_DSI_OFF, + AV8100_HDMI_DSI_COMMAND_MODE, + AV8100_HDMI_DSI_VIDEO_MODE +}; + +enum av8100_pixel_format { + AV8100_INPUT_PIX_RGB565, + AV8100_INPUT_PIX_RGB666, + AV8100_INPUT_PIX_RGB666P, + AV8100_INPUT_PIX_RGB888, + AV8100_INPUT_PIX_YCBCR422 +}; + +enum av8100_video_mode { + AV8100_VIDEO_INTERLACE, + AV8100_VIDEO_PROGRESSIVE +}; + +enum av8100_dsi_nb_data_lane { + AV8100_DATA_LANES_USED_0, + AV8100_DATA_LANES_USED_1, + AV8100_DATA_LANES_USED_2, + AV8100_DATA_LANES_USED_3, + AV8100_DATA_LANES_USED_4 +}; + +enum av8100_te_config { + AV8100_TE_OFF, /* NO TE*/ + AV8100_TE_DSI_LANE, /* TE generated on DSI lane */ + AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */ + AV8100_TE_DSI_IT, /* TE generatedon both DSI lane & IT line*/ + AV8100_TE_GPIO_IT /* TE on GPIO I2S DAT3 & or IT line*/ +}; + +enum av8100_audio_if_format { + AV8100_AUDIO_I2S_MODE, + AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/ + AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/ +}; + +enum av8100_sample_freq { + AV8100_AUDIO_FREQ_32KHZ, + AV8100_AUDIO_FREQ_44_1KHZ, + AV8100_AUDIO_FREQ_48KHZ, + AV8100_AUDIO_FREQ_64KHZ, + AV8100_AUDIO_FREQ_88_2KHZ, + AV8100_AUDIO_FREQ_96KHZ, + AV8100_AUDIO_FREQ_128KHZ, + AV8100_AUDIO_FREQ_176_1KHZ, + AV8100_AUDIO_FREQ_192KHZ +}; + +enum av8100_audio_word_length { + AV8100_AUDIO_16BITS, + AV8100_AUDIO_20BITS, + AV8100_AUDIO_24BITS +}; + +enum av8100_audio_format { + AV8100_AUDIO_LPCM_MODE, + AV8100_AUDIO_COMPRESS_MODE +}; + +enum av8100_audio_if_mode { + AV8100_AUDIO_SLAVE, + AV8100_AUDIO_MASTER +}; + +enum av8100_audio_mute { + AV8100_AUDIO_MUTE_DISABLE, + AV8100_AUDIO_MUTE_ENABLE +}; + +enum av8100_output_CEA_VESA { + AV8100_CUSTOM, + AV8100_CEA1_640X480P_59_94HZ, + AV8100_CEA2_3_720X480P_59_94HZ, + AV8100_CEA4_1280X720P_60HZ, + AV8100_CEA5_1920X1080I_60HZ, + AV8100_CEA6_7_NTSC_60HZ, + AV8100_CEA14_15_480p_60HZ, + AV8100_CEA16_1920X1080P_60HZ, + AV8100_CEA17_18_720X576P_50HZ, + AV8100_CEA19_1280X720P_50HZ, + AV8100_CEA20_1920X1080I_50HZ, + AV8100_CEA21_22_576I_PAL_50HZ, + AV8100_CEA29_30_576P_50HZ, + AV8100_CEA31_1920x1080P_50Hz, + AV8100_CEA32_1920X1080P_24HZ, + AV8100_CEA33_1920X1080P_25HZ, + AV8100_CEA34_1920X1080P_30HZ, + AV8100_CEA60_1280X720P_24HZ, + AV8100_CEA61_1280X720P_25HZ, + AV8100_CEA62_1280X720P_30HZ, + AV8100_VESA9_800X600P_60_32HZ, + AV8100_VESA14_848X480P_60HZ, + AV8100_VESA16_1024X768P_60HZ, + AV8100_VESA22_1280X768P_59_99HZ, + AV8100_VESA23_1280X768P_59_87HZ, + AV8100_VESA27_1280X800P_59_91HZ, + AV8100_VESA28_1280X800P_59_81HZ, + AV8100_VESA39_1360X768P_60_02HZ, + AV8100_VESA81_1366X768P_59_79HZ, + AV8100_VIDEO_OUTPUT_CEA_VESA_MAX +}; + +enum av8100_video_sync_pol { + AV8100_SYNC_POSITIVE, + AV8100_SYNC_NEGATIVE +}; + +enum av8100_hdmi_mode { + AV8100_HDMI_OFF, + AV8100_HDMI_ON, + AV8100_HDMI_AVMUTE +}; + +enum av8100_hdmi_format { + AV8100_HDMI, + AV8100_DVI +}; + +enum av8100_DVI_format { + AV8100_DVI_CTRL_CTL0, + AV8100_DVI_CTRL_CTL1, + AV8100_DVI_CTRL_CTL2 +}; + +enum av8100_pattern_type { + AV8100_PATTERN_OFF, + AV8100_PATTERN_GENERATOR, + AV8100_PRODUCTION_TESTING +}; + +enum av8100_pattern_format { + AV8100_NO_PATTERN, + AV8100_PATTERN_VGA, + AV8100_PATTERN_720P, + AV8100_PATTERN_1080P +}; + +enum av8100_pattern_audio { + AV8100_PATTERN_AUDIO_OFF, + AV8100_PATTERN_AUDIO_ON, + AV8100_PATTERN_AUDIO_I2S_MEM +}; + +struct av8100_video_input_format_cmd { + enum av8100_dsi_mode dsi_input_mode; + enum av8100_pixel_format input_pixel_format; + unsigned short total_horizontal_pixel; + unsigned short total_horizontal_active_pixel; + unsigned short total_vertical_lines; + unsigned short total_vertical_active_lines; + enum av8100_video_mode video_mode; + enum av8100_dsi_nb_data_lane nb_data_lane; + unsigned char nb_virtual_ch_command_mode; + unsigned char nb_virtual_ch_video_mode; + unsigned short TE_line_nb; + enum av8100_te_config TE_config; + unsigned long master_clock_freq; + unsigned char ui_x4; +}; + +struct av8100_audio_input_format_cmd { + enum av8100_audio_if_format audio_input_if_format; + unsigned char i2s_input_nb; + enum av8100_sample_freq sample_audio_freq; + enum av8100_audio_word_length audio_word_lg; + enum av8100_audio_format audio_format; + enum av8100_audio_if_mode audio_if_mode; + enum av8100_audio_mute audio_mute; +}; + +struct av8100_video_output_format_cmd { + enum av8100_output_CEA_VESA video_output_cea_vesa; + enum av8100_video_sync_pol vsync_polarity; + enum av8100_video_sync_pol hsync_polarity; + unsigned short total_horizontal_pixel; + unsigned short total_horizontal_active_pixel; + unsigned short total_vertical_in_half_lines; + unsigned short total_vertical_active_in_half_lines; + unsigned short hsync_start_in_pixel; + unsigned short hsync_length_in_pixel; + unsigned short vsync_start_in_half_line; + unsigned short vsync_length_in_half_line; + unsigned short hor_video_start_pixel; + unsigned short vert_video_start_pixel; + enum av8100_video_mode video_type; + unsigned short pixel_repeat; + unsigned long pixel_clock_freq_Hz; +}; + +struct av8100_video_scaling_format_cmd { + unsigned short h_start_in_pixel; + unsigned short h_stop_in_pixel; + unsigned short v_start_in_line; + unsigned short v_stop_in_line; + unsigned short h_start_out_pixel; + unsigned short h_stop_out_pixel; + unsigned short v_start_out_line; + unsigned short v_stop_out_line; +}; + +enum av8100_color_transform { + AV8100_COLOR_TRANSFORM_INDENTITY, + AV8100_COLOR_TRANSFORM_INDENTITY_CLAMP_YUV, + AV8100_COLOR_TRANSFORM_YUV_TO_RGB, + AV8100_COLOR_TRANSFORM_YUV_TO_DENC, + AV8100_COLOR_TRANSFORM_RGB_TO_DENC, +}; + +struct av8100_cec_message_write_format_cmd { + unsigned char buffer_length; + unsigned char buffer[AV8100_CEC_MESSAGE_SIZE]; +}; + +struct av8100_cec_message_read_back_format_cmd { +}; + +enum av8100_cvbs_video_format { + AV8100_CVBS_625, + AV8100_CVBS_525, +}; + +enum av8100_standard_selection { + AV8100_PAL_BDGHI, + AV8100_PAL_N, + AV8100_NTSC_M, + AV8100_PAL_M +}; + +struct av8100_denc_format_cmd { + enum av8100_cvbs_video_format cvbs_video_format; + enum av8100_standard_selection standard_selection; + unsigned char enable; + unsigned char macrovision_enable; + unsigned char internal_generator; +}; + +struct av8100_hdmi_cmd { + enum av8100_hdmi_mode hdmi_mode; + enum av8100_hdmi_format hdmi_format; + enum av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/ +}; + +struct av8100_hdcp_send_key_format_cmd { + unsigned char key_number; + unsigned char data_len; + unsigned char data[AV8100_HDCP_SEND_KEY_SIZE]; +}; + +enum av8100_hdcp_auth_req_type { + AV8100_HDCP_AUTH_REQ_OFF = 0, + AV8100_HDCP_AUTH_REQ_ON = 1, + AV8100_HDCP_REV_LIST_REQ = 2, + AV8100_HDCP_AUTH_CONT = 3, +}; + +enum av8100_hdcp_encr_use { + AV8100_HDCP_ENCR_USE_OESS = 0, + AV8100_HDCP_ENCR_USE_EESS = 1, +}; + +struct av8100_hdcp_management_format_cmd { + unsigned char req_type; + unsigned char encr_use; +}; + +struct av8100_infoframes_format_cmd { + unsigned char type; + unsigned char version; + unsigned char length; + unsigned char crc; + unsigned char data[AV8100_INFOFRAME_SIZE]; +}; + +struct av8100_edid_section_readback_format_cmd { + unsigned char address; + unsigned char block_number; +}; + +struct av8100_pattern_generator_format_cmd { + enum av8100_pattern_type pattern_type; + enum av8100_pattern_format pattern_video_format; + enum av8100_pattern_audio pattern_audio_mode; +}; + +enum av8100_fuse_operation { + AV8100_FUSE_READ = 0, + AV8100_FUSE_WRITE = 1, +}; + +struct av8100_fuse_aes_key_format_cmd { + unsigned char fuse_operation; + unsigned char key[AV8100_FUSE_KEY_SIZE]; +}; + +union av8100_configuration { + struct av8100_video_input_format_cmd video_input_format; + struct av8100_audio_input_format_cmd audio_input_format; + struct av8100_video_output_format_cmd video_output_format; + struct av8100_video_scaling_format_cmd video_scaling_format; + enum av8100_color_transform color_transform; + struct av8100_cec_message_write_format_cmd + cec_message_write_format; + struct av8100_cec_message_read_back_format_cmd + cec_message_read_back_format; + struct av8100_denc_format_cmd denc_format; + struct av8100_hdmi_cmd hdmi_format; + struct av8100_hdcp_send_key_format_cmd hdcp_send_key_format; + struct av8100_hdcp_management_format_cmd hdcp_management_format; + struct av8100_infoframes_format_cmd infoframes_format; + struct av8100_edid_section_readback_format_cmd + edid_section_readback_format; + struct av8100_pattern_generator_format_cmd pattern_generator_format; + struct av8100_fuse_aes_key_format_cmd fuse_aes_key_format; +}; + +enum av8100_operating_mode { + AV8100_OPMODE_UNDEFINED = 0, + AV8100_OPMODE_SHUTDOWN, + AV8100_OPMODE_STANDBY, + AV8100_OPMODE_SCAN, + AV8100_OPMODE_INIT, + AV8100_OPMODE_IDLE, + AV8100_OPMODE_VIDEO, +}; + +enum av8100_plugin_status { + AV8100_PLUGIN_NONE = 0x0, + AV8100_HDMI_PLUGIN = 0x1, + AV8100_CVBS_PLUGIN = 0x2, +}; + +enum av8100_hdmi_event { + AV8100_HDMI_EVENT_NONE = 0x0, + AV8100_HDMI_EVENT_HDMI_PLUGIN = 0x1, + AV8100_HDMI_EVENT_HDMI_PLUGOUT = 0x2, + AV8100_HDMI_EVENT_CEC = 0x4, + AV8100_HDMI_EVENT_HDCP = 0x8, + AV8100_HDMI_EVENT_CECTXERR = 0x10, + AV8100_HDMI_EVENT_CECTX = 0x20, /* Transm no error */ +}; + +struct av8100_status { + enum av8100_operating_mode av8100_state; + enum av8100_plugin_status av8100_plugin_status; + int hdmi_on; +}; + + +int av8100_init(void); +void av8100_exit(void); +int av8100_powerscan(void); +int av8100_powerup(void); +int av8100_powerdown(void); +int av8100_disable_interrupt(void); +int av8100_enable_interrupt(void); +int av8100_download_firmware(enum interface_type if_type); +int av8100_reg_stby_w( + unsigned char cpd, + unsigned char stby, + unsigned char mclkrng); +int av8100_reg_hdmi_5_volt_time_w( + unsigned char denc_off_time, + unsigned char hdmi_off_time, + unsigned char on_time); +int av8100_reg_stby_int_mask_w( + unsigned char hpdm, + unsigned char cpdm, + unsigned char stbygpiocfg, + unsigned char ipol); +int av8100_reg_stby_pend_int_w( + unsigned char hpdi, + unsigned char cpdi, + unsigned char oni, + unsigned char bpdig); +int av8100_reg_gen_int_mask_w( + unsigned char eocm, + unsigned char vsim, + unsigned char vsom, + unsigned char cecm, + unsigned char hdcpm, + unsigned char uovbm, + unsigned char tem); +int av8100_reg_gen_int_w( + unsigned char eoci, + unsigned char vsii, + unsigned char vsoi, + unsigned char ceci, + unsigned char hdcpi, + unsigned char uovbi); +int av8100_reg_gpio_conf_w( + unsigned char dat3dir, + unsigned char dat3val, + unsigned char dat2dir, + unsigned char dat2val, + unsigned char dat1dir, + unsigned char dat1val, + unsigned char ucdbg); +int av8100_reg_gen_ctrl_w( + unsigned char fdl, + unsigned char hld, + unsigned char wa, + unsigned char ra); +int av8100_reg_fw_dl_entry_w( + unsigned char mbyte_code_entry); +int av8100_reg_w( + unsigned char offset, + unsigned char value); +int av8100_reg_stby_r( + unsigned char *cpd, + unsigned char *stby, + unsigned char *hpds, + unsigned char *cpds, + unsigned char *mclkrng); +int av8100_reg_hdmi_5_volt_time_r( + unsigned char *denc_off_time, + unsigned char *hdmi_off_time, + unsigned char *on_time); +int av8100_reg_stby_int_mask_r( + unsigned char *hpdm, + unsigned char *cpdm, + unsigned char *stbygpiocfg, + unsigned char *ipol); +int av8100_reg_stby_pend_int_r( + unsigned char *hpdi, + unsigned char *cpdi, + unsigned char *oni, + unsigned char *sid); +int av8100_reg_gen_int_mask_r( + unsigned char *eocm, + unsigned char *vsim, + unsigned char *vsom, + unsigned char *cecm, + unsigned char *hdcpm, + unsigned char *uovbm, + unsigned char *tem); +int av8100_reg_gen_int_r( + unsigned char *eoci, + unsigned char *vsii, + unsigned char *vsoi, + unsigned char *ceci, + unsigned char *hdcpi, + unsigned char *uovbi, + unsigned char *tei); +int av8100_reg_gen_status_r( + unsigned char *cectxerr, + unsigned char *cecrec, + unsigned char *cectrx, + unsigned char *uc, + unsigned char *onuvb, + unsigned char *hdcps); +int av8100_reg_gpio_conf_r( + unsigned char *dat3dir, + unsigned char *dat3val, + unsigned char *dat2dir, + unsigned char *dat2val, + unsigned char *dat1dir, + unsigned char *dat1val, + unsigned char *ucdbg); +int av8100_reg_gen_ctrl_r( + unsigned char *fdl, + unsigned char *hld, + unsigned char *wa, + unsigned char *ra); +int av8100_reg_fw_dl_entry_r( + unsigned char *mbyte_code_entry); +int av8100_reg_r( + unsigned char offset, + unsigned char *value); +int av8100_conf_get(enum av8100_command_type command_type, + union av8100_configuration *config); +int av8100_conf_prep(enum av8100_command_type command_type, + union av8100_configuration *config); +int av8100_conf_w(enum av8100_command_type command_type, + unsigned char *return_buffer_length, + unsigned char *return_buffer, enum interface_type if_type); +int av8100_conf_w_raw(enum av8100_command_type command_type, + unsigned char buffer_length, + unsigned char *buffer, + unsigned char *return_buffer_length, + unsigned char *return_buffer); +struct av8100_status av8100_status_get(void); +enum av8100_output_CEA_VESA av8100_video_output_format_get(int xres, + int yres, + int htot, + int vtot, + int pixelclk, + bool interlaced); +void av8100_hdmi_event_cb_set(void (*event_callback)(enum av8100_hdmi_event)); +u8 av8100_ver_get(void); + +#endif /* __AV8100__H__ */ diff --git a/include/video/b2r2_blt.h b/include/video/b2r2_blt.h new file mode 100644 index 00000000000..a992155f0da --- /dev/null +++ b/include/video/b2r2_blt.h @@ -0,0 +1,617 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson B2R2 user interface + * + * Author: Robert Fekete <robert.fekete@stericsson.com> + * Author: Paul Wannback + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + + +#ifndef _LINUX_VIDEO_B2R2_BLT_H +#define _LINUX_VIDEO_B2R2_BLT_H + +#include <linux/types.h> + +#if defined(__KERNEL__) || defined(_KERNEL) +#include <linux/mm_types.h> +#include <linux/bitops.h> +#else +#define BIT(nr) (1UL << (nr)) +#endif + +/** + * struct b2r2_blt_rect - Specifies a B2R2 rectangle + * + * @left: X-coordinate of top left corner + * @top: Y-coordinate of top left corner + * @width: Rectangle width. Must be >= 0. + * @height: Rectangle height. Must be >= 0. + */ +struct b2r2_blt_rect { + __s32 x; + __s32 y; + __s32 width; + __s32 height; +}; + +/** + * enum b2r2_blt_fmt - Defines the available B2R2 buffer formats + * + * Inspired by Khronos OpenMAX, please see + * OpenMAX IL specification for detailed descriptions of the formats + * + * @B2R2_BLT_FMT_UNUSED: Placeholder value when format is unknown, + * or specified using a vendor-specific means. + * @B2R2_BLT_FMT_16_BIT_ARGB4444: 16 bits per pixel ARGB format with colors + * stored as Alpha 15:12, Red 11:8, Green 7:4, and Blue 3:0. + * @B2R2_BLT_FMT_16_BIT_ARGB1555: 16 bits per pixel ARGB format with colors + * stored as Alpha 15, Red 14:10, Green 9:5, and Blue 4:0. + * @B2R2_BLT_FMT_16_BIT_RGB565: 16 bits per pixel RGB format with colors + * stored as Red 15:11, Green 10:5, and Blue 4:0. + * @B2R2_BLT_FMT_24_BIT_RGB888: 24 bits per pixel RGB format with colors + * stored as Red 23:16, Green 15:8, and Blue 7:0. + * @B2R2_BLT_FMT_32_BIT_ARGB8888: 32 bits per pixel ARGB format with colors + * stored as Alpha 31:24, Red 23:16, Green 15:8, and Blue 7:0. + * @B2R2_BLT_FMT_YUV420_PACKED_PLANAR: YUV planar format, organized with + * three separate planes for each color component, namely Y, U, and V. + * U and V pixels are sub-sampled by a factor of two both horizontally and + * vertically. The buffer shall contain a plane of Y, U, and V data in this + * order + * @B2R2_BLT_FMT_YUV422_PACKED_PLANAR: YUV planar format, organized with + * three separate planes for each color component, namely Y, U, and V. + * U and V pixels are subsampled by a factor of two horizontally. + * The buffer shall contain a plane of Y, U, and V data in this order. + * @B2R2_BLT_FMT_Y_CB_Y_CR: 16 bits per pixel YUV interleaved format organized + * as YUYV (i.e., YCbYCr). + * (Corresponds to YUV422 interleaved) + * @B2R2_BLT_FMT_CB_Y_CR_Y: 16 bits per pixel YUV interleaved format organized + * as UYVY (i.e., CbYCrY). + * (Corresponds to YUV422R) + * @B2R2_BLT_FMT_YUV420_PACKED_SEMI_PLANAR: YUV planar format, organized with + * a first plane containing Y pixels, and a second plane containing U and V + * pixels interleaved with the first U value first. U and V pixels are + * sub-sampled by a factor of two both horizontally and vertically. The buffer + * shall contain a plane of Y, U and V data. + * (Same as B2R2 420 Raster 2 buffer - 420 R2B) + * @B2R2_BLT_FMT_YUV422_PACKED_SEMI_PLANAR: YUV planar format, organized with + * a first plane containing Y pixels, and a second plane containing U and V + * pixels interleaved with the first U value first. U and V pixels are + * sub-sampled by a factor of two horizontally. The buffer shall contain a + * plane of Y, U and V data. + * (Same as B2R2 422 Raster 2 buffer - 422 R2B) + * @B2R2_BLT_FMT_32_BIT_ABGR8888: 32 bits per pixel ABGR format with colors + * stored as Alpha 31:24,Blue 23:16, Green 15:8, and Red 7:0. + * @B2R2_BLT_FMT_24_BIT_ARGB8565: 24 bits per pixel ARGB format with colors + * stored as Alpha 23:16, Red 15:11, Green 10:5, and Blue 4:0. + * @B2R2_BLT_FMT_24_BIT_YUV888: 24 bits per pixel YUV format with colors + * stored as Y 23:16, U 15:8, and V 7:0. + * @B2R2_BLT_FMT_32_BIT_AYUV8888: 32 bits per pixel AYUV format with colors + * stored as Alpha 31:24, Y 23:16, U 15:8, and V 7:0. + * @B2R2_BLT_FMT_YUV420_PACKED_SEMIPLANAR_MB_STE: Nomadik YUV 420 macro block + * format, see B2R2 spec for details + * @B2R2_BLT_FMT_YUV422_PACKED_SEMIPLANAR_MB_STE: Nomadik YUV 422 macro block + * format, see B2R2 spec for details + * @B2R2_BLT_FMT_1_BIT_A1: 1 bit per pixel A format, 1 bit alpha + * @B2R2_BLT_FMT_8_BIT_A8: 8 bit per pixel A format, 8 bit alpha + * @B2R2_BLT_FMT_YUV444_PACKED_PLANAR: YUV planar format, organized with + * three separate planes, one for each color component, namely Y, U, and V. + * All planes use full resolution, there is no subsampling. + * The buffer shall contain a plane of Y, U, and V data in this order. + * @B2R2_BLT_FMT_YVU420_PACKED_SEMI_PLANAR: YVU planar format, organized with + * a first plane containing Y pixels, and a second plane containing V and U + * pixels interleaved with the first V value first. V and U pixels are + * sub-sampled by a factor of two both horizontally and vertically. The buffer + * shall contain two planes, one plane with Y, and one with V and U data. + * (Same as B2R2 420 Raster 2 buffer - 420 R2B except that chroma order is + * swapped.) + * @B2R2_BLT_FMT_YVU422_PACKED_SEMI_PLANAR: YVU planar format, organized with + * a first plane containing Y pixels, and a second plane containing V and U + * pixels interleaved with the first V value first. V and U pixels are + * sub-sampled by a factor of two horizontally. The buffer shall contain a + * two planes, one with Y, and one with V and U data. + * (Same as B2R2 422 Raster 2 buffer - 422 R2B except that chroma order is + * swapped.) + * @B2R2_BLT_FMT_YVU420_PACKED_PLANAR: YVU planar format, organized with + * three separate planes for each color component, namely Y, V, and U. + * V and U pixels are sub-sampled by a factor of two both horizontally and + * vertically. The buffer shall contain a plane of Y, V, and U data in this + * order. (Same as B2R2_BLT_FMT_YUV420_PACKED_PLANAR except that chroma + * order is swapped.) + * @B2R2_BLT_FMT_YVU422_PACKED_PLANAR: YVU planar format, organized with + * three separate planes for each color component, namely Y, V, and U. + * V and U pixels are subsampled by a factor of two horizontally. + * The buffer shall contain a plane of Y, V, and U data in this order. + * (Same as B2R2_BLT_FMT_YUV422_PACKED_PLANAR except that chroma + * order is swapped.) + * @B2R2_BLT_FMT_24_BIT_VUY888: 24 bits per pixel VUY format with colors + * stored as V 23:16, U 15:8, and Y 7:0. + * @B2R2_BLT_FMT_32_BIT_VUYA8888: 32 bits per pixel VUYA format with colors + * stored as V 31:24, U 23:16, Y 15:8, and Alpha 7:0. + */ +enum b2r2_blt_fmt { + B2R2_BLT_FMT_UNUSED = 0, + B2R2_BLT_FMT_16_BIT_ARGB4444 = 4, + B2R2_BLT_FMT_16_BIT_ARGB1555 = 5, + B2R2_BLT_FMT_16_BIT_RGB565 = 6, + B2R2_BLT_FMT_24_BIT_RGB888 = 11, + B2R2_BLT_FMT_32_BIT_ARGB8888 = 16, + B2R2_BLT_FMT_YUV420_PACKED_PLANAR = 20, + B2R2_BLT_FMT_YUV422_PACKED_PLANAR = 23, + B2R2_BLT_FMT_Y_CB_Y_CR = 25, + B2R2_BLT_FMT_CB_Y_CR_Y = 27, + B2R2_BLT_FMT_YUV420_PACKED_SEMI_PLANAR = 39, + B2R2_BLT_FMT_YUV422_PACKED_SEMI_PLANAR = 40, + /* Extensions, non OpenMAX formats */ + B2R2_BLT_FMT_32_BIT_ABGR8888 = 0x7F000000, /* OpenMax vendor start */ + B2R2_BLT_FMT_24_BIT_ARGB8565 = 0x7F000001, + B2R2_BLT_FMT_24_BIT_YUV888 = 0x7F000002, + B2R2_BLT_FMT_32_BIT_AYUV8888 = 0x7F000003, + B2R2_BLT_FMT_YUV420_PACKED_SEMIPLANAR_MB_STE = 0x7F000004, + B2R2_BLT_FMT_YUV422_PACKED_SEMIPLANAR_MB_STE = 0x7F000005, + B2R2_BLT_FMT_1_BIT_A1 = 0x7F000006, + B2R2_BLT_FMT_8_BIT_A8 = 0x7F000007, + B2R2_BLT_FMT_YUV444_PACKED_PLANAR = 0x7F000008, + B2R2_BLT_FMT_YVU420_PACKED_SEMI_PLANAR = 0x7F000009, + B2R2_BLT_FMT_YVU422_PACKED_SEMI_PLANAR = 0x7F00000A, + B2R2_BLT_FMT_YVU420_PACKED_PLANAR = 0x7F00000B, + B2R2_BLT_FMT_YVU422_PACKED_PLANAR = 0x7F00000C, + B2R2_BLT_FMT_24_BIT_VUY888 = 0x7F00000D, + B2R2_BLT_FMT_32_BIT_VUYA8888 = 0x7F00000E, +}; + +/** + * enum b2r2_blt_ptr_type - Specifies a B2R2 buffer pointer type + * + * @B2R2_BLT_PTR_NONE: + * No pointer (NULL). E.g. src fill. + * @B2R2_BLT_PTR_VIRTUAL: + * Use offset as a userspace virtual address + * @B2R2_BLT_PTR_PHYSICAL: + * Use offset as a physical address + * @B2R2_BLT_PTR_FD_OFFSET: + * Use fd + offset to determine buffer location. + * @B2R2_BLT_PTR_HWMEM_BUF_NAME: + * Use hwmem_buf_name and offset to determine buffer location. + */ +enum b2r2_blt_ptr_type { + B2R2_BLT_PTR_NONE, + B2R2_BLT_PTR_VIRTUAL, + B2R2_BLT_PTR_PHYSICAL, + B2R2_BLT_PTR_FD_OFFSET, + B2R2_BLT_PTR_HWMEM_BUF_NAME_OFFSET, +}; + +/** + * struct b2r2_blt_buf - Specifies a B2R2 buffer pointer + * + * @type: Buffer pointer type + * @hwmem_global_buf_id: Hwmem buffer name + * @fd: File descriptor (e.g. file handle to pmem or fb device) + * @offset: Offset where buffer can be found or address. + * @len: Size of buffer in bytes + * @bits: Pointer to the bitmap data. This field can be used to specify + * an alternative way to access the buffer. Whenever the 'bits' pointer + * is set to non-NULL, the underlying implementation is free to decide + * whether or not to use it in favor of other ways to locate the buffer. + */ +struct b2r2_blt_buf { + enum b2r2_blt_ptr_type type; + __s32 hwmem_buf_name; + __s32 fd; + __u32 offset; + __u32 len; + void *bits; +}; + + +/** + * struct b2r2_blt_img - Specifies a B2R2 image + * + * @fmt: Pixel format of image + * @buf: Pixel buffer + * @width: Width in pixels + * @height: Height in pixels + * @pitch: Pitch in bytes (from start of one line to start of next) + */ +struct b2r2_blt_img { + enum b2r2_blt_fmt fmt; + struct b2r2_blt_buf buf; + __s32 width; + __s32 height; + __u32 pitch; +}; + + +/** + * enum b2r2_blt_transform- Specifies rotation and flipping, mutually exclusive + * @B2R2_BLT_TRANSFORM_NONE: + * No rotation or flip + * @B2R2_BLT_TRANSFORM_FLIP_H + * Flip horizontally + * @B2R2_BLT_TRANSFORM_FLIP_V + * Flip vertically + * @B2R2_BLT_TRANSFORM_CCW_ROT_90 + * Rotate 90 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_CCW_ROT_180 + * Rotate 180 degrees (same as flip horizontally together with + * flip vertically) + * @B2R2_BLT_TRANSFORM_CCW_ROT_270 + * Rotate 270 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_FLIP_H_CCW_ROT_90 + * Flip horizontally and then rotate 90 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_FLIP_V_CCW_ROT_90 + * Flip vertically and then rotate 90 degrees counter clockwise + */ +enum b2r2_blt_transform { + B2R2_BLT_TRANSFORM_NONE = 0, + B2R2_BLT_TRANSFORM_FLIP_H = 1, + B2R2_BLT_TRANSFORM_FLIP_V = 2, + B2R2_BLT_TRANSFORM_CCW_ROT_90 = 4, + B2R2_BLT_TRANSFORM_CCW_ROT_180 = 3, + B2R2_BLT_TRANSFORM_CCW_ROT_270 = 7, + B2R2_BLT_TRANSFORM_FLIP_H_CCW_ROT_90 = 5, + B2R2_BLT_TRANSFORM_FLIP_V_CCW_ROT_90 = 6, +}; + + +/** + * enum b2r2_blt_flag - Flags that controls the B2R2 request + * + * Can be combined. + * + * @B2R2_BLT_FLAG_ASYNCH: + * Asynchronous request. b2r2_blt will returns when the request + * has been queued. + * @B2R2_BLT_FLAG_DRY_RUN: + * Dry run, just to check if request can be performed. + * @B2R2_BLT_FLAG_PER_PIXEL_ALPHA_BLEND: + * Enable per pixel alpha blend + * @B2R2_BLT_FLAG_GLOBAL_ALPHA_BLEND: + * Enable global alpha blend (alpha value in global_alpha) + * @B2R2_BLT_FLAG_SOURCE_COLOR_KEY: + * Enable source color key (color in src_color). Color should be in raw + * format. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY and B2R2_BLT_FLAG_DEST_COLOR_KEY cannot be + * specified at the same time. + * @B2R2_BLT_FLAG_SOURCE_FILL: + * Enable ARGB/AYUV source fill (color in src_color). Which of ARGB and AYUV + * is determined by the destination format. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time + * @B2R2_BLT_FLAG_SOURCE_FILL_RAW: + * Enable raw color source fill (color in src_color) + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time + * @B2R2_BLT_FLAG_DEST_COLOR_KEY: + * Enable dest color key (color in dst_color). Color in raw format. + * @B2R2_BLT_FLAG_SRC_IS_NOT_PREMULT: + * Source color not premultiplied (Valid for alpha formats only). + * @B2R2_BLT_FLAG_DITHER: + * Enable dithering + * @B2R2_BLT_FLAG_BLUR: + * Enable blur + * @B2R2_BLT_FLAG_SOURCE_MASK: + * Enable source mask + * @B2R2_BLT_FLAG_DESTINATION_CLIP: + * Enable destination clip rectangle + * @B2R2_BLT_FLAG_INHERIT_PRIO + * Inherit process priority + * @B2R2_BLT_FLAG_REPORT_WHEN_DONE + * Report through b2r2_blt file when done. A b2r2_blt_report structure is + * read. Use poll() or select() if anything to read. (i.e. to help user space + * to implement callback functionality) + * @B2R2_BLT_FLAG_REPORT_PERFORMANCE + * Include performance data in the report structure + * @B2R2_BLT_FLAG_CLUT_COLOR_CORRECTION + * Use color look-up table for color correction. + * Pointer to the table must be specified in *clut field of + * the b2r2_blt_req structure. + * The table must map all input color values + * for each channel to the desired output values. + * It is an array with the following format: + * R0 G0 B0 A0 R1 G1 B1 A1...R255 G255 B255 A255 + * where R0 is the 8 bit output value for red channel whenever its input + * equals 0. + * Similarly, R1 through R255 are the red channel outputs whenever + * the channel's inputs equal 1 through 255 respectively. + * Gn, Bn, An denote green, blue and alpha channel. + * Whenever the input bitmap format lacks the alpha channel, + * all alpha values in the color correction table should be set to 255. + * Size of the array that specifies the color correction table + * must be 1024 bytes. + * A table that does not change anything has the form: + * 0 0 0 0 1 1 1 1 2 2 2 2 ... 254 254 254 254 255 255 255 255. + * CLUT color correction can be applied to YUV raster buffers as well, + * in which case the RGB color channels are mapped onto YUV-space + * as follows: + * R = red chrominance + * G = luminance + * B = blue chrominance + * A = alpha + * If any of the planar or semi-planar formats is used, luminance cannot + * be changed by the color correction table. + */ +enum b2r2_blt_flag { + B2R2_BLT_FLAG_ASYNCH = BIT(0),/*0x1*/ + B2R2_BLT_FLAG_DRY_RUN = BIT(1),/*0x2*/ + B2R2_BLT_FLAG_PER_PIXEL_ALPHA_BLEND = BIT(2),/*0x4*/ + B2R2_BLT_FLAG_GLOBAL_ALPHA_BLEND = BIT(3),/*0x8*/ + B2R2_BLT_FLAG_SOURCE_COLOR_KEY = BIT(4),/*0x10*/ + B2R2_BLT_FLAG_SOURCE_FILL = BIT(5),/*0x20*/ + B2R2_BLT_FLAG_SOURCE_FILL_RAW = BIT(6),/*0x40*/ + B2R2_BLT_FLAG_DEST_COLOR_KEY = BIT(7),/*0x80*/ + B2R2_BLT_FLAG_SRC_IS_NOT_PREMULT = BIT(8),/*0x100*/ + B2R2_BLT_FLAG_DITHER = BIT(9),/*0x200*/ + B2R2_BLT_FLAG_BLUR = BIT(10),/*0x400*/ + B2R2_BLT_FLAG_SOURCE_MASK = BIT(11),/*0x800*/ + B2R2_BLT_FLAG_DESTINATION_CLIP = BIT(12),/*0x1000*/ + B2R2_BLT_FLAG_INHERIT_PRIO = BIT(13),/*0x2000*/ + B2R2_BLT_FLAG_SRC_NO_CACHE_FLUSH = BIT(14),/*0x4000*/ + B2R2_BLT_FLAG_SRC_MASK_NO_CACHE_FLUSH = BIT(15),/*0x8000*/ + B2R2_BLT_FLAG_DST_NO_CACHE_FLUSH = BIT(16),/*0x10000*/ + B2R2_BLT_FLAG_REPORT_WHEN_DONE = BIT(29),/*0x20000000*/ + B2R2_BLT_FLAG_REPORT_PERFORMANCE = BIT(30),/*0x40000000*/ + B2R2_BLT_FLAG_CLUT_COLOR_CORRECTION = BIT(31),/*0x80000000*/ +}; + + +/** + * struct b2r2_blt_req - Specifies a request to B2R2 + * + * @size: Size of this structure. Used for versioning. MUST be specified. + * @flags: Flags that control the B2R2 request ORed together + * @tfm: How source should be flipped and rotated when blitting + * @prio: Priority (-20 to 19). Inherits process prio + * if B2R2_BLT_FLAG_INHERIT_PRIO. Given priority is mapped onto B2R2. + * TBD: How? + * @clut: Pointer to the look-up table for color correction. + * @src_img: Source image. Not used if source fill. + * @src_mask: Source mask. Not used if source fill. + * @src_rect: Source area to be blitted. + * @src_color: Source fill color or color key + * @dst_img: Destination image. + * @dst_rect: Destination area to be blitted to. + * @dst_color: Destination color key + * @dst_clip_rect: Destination clip rectangle. + * @global_alpha: Global alpha value (0 - 255) + * @report1: Data 1 to report back when request is done. + * See struct b2r2_blt_report. + * @report2: Data 2 to report back when request is done. + * See struct b2r2_blt_report. + * + */ +struct b2r2_blt_req { + __u32 size; + enum b2r2_blt_flag flags; + enum b2r2_blt_transform transform; + __s32 prio; + void *clut; + struct b2r2_blt_img src_img; + struct b2r2_blt_img src_mask; + struct b2r2_blt_rect src_rect; + __u32 src_color; + struct b2r2_blt_img dst_img; + struct b2r2_blt_rect dst_rect; + struct b2r2_blt_rect dst_clip_rect; + __u32 dst_color; + __u8 global_alpha; + __u32 report1; + __u32 report2; +}; + +/** + * enum b2r2_blt_cap - Capabilities that can be queried for. + * + * Capabilities can be queried for a specific format or for formats in + * general. To query for capabilities in general, specify BLT_FMT_UNUSED + * as format. + * + * B2R2_BLT_CAP_UNUSED: Unused/unspecified capability + * B2R2_BLT_CAP_FMT_SOURCE: Is format supported as source? + * B2R2_BLT_CAP_FMT_SOURCE_MASK: Is format supported as source mask? + * B2R2_BLT_CAP_FMT_DEST: Is format supported as dest? + * B2R2_BLT_CAP_PER_PIXEL_ALPHA_BLEND: Is per pixel alpha blending supported + * with format as source + * B2R2_BLT_CAP_GLOBAL_ALPHA_BLEND: Is per global alpha blending supported + * with format as source + * B2R2_BLT_CAP_SOURCE_COLOR_KEY: Is source color key supported with format as + * source + * B2R2_BLT_CAP_SOURCE_FILL: Is source fill supported with format as source + * B2R2_BLT_CAP_SOURCE_FILL_RAW: Is source fill raw supported with format as + * dest + * B2R2_BLT_CAP_DEST_COLOR_KEY: Is dest color key supported with format as dest + * B2R2_BLT_CAP_DITHER: Is dithering supported with format as source + * B2R2_BLT_CAP_BLUR: Is blur supported with format as source + * B2R2_BLT_CAP_MINIFICATION_LIMIT: Minification limit (copybit support) + * B2R2_BLT_CAP_MAGNIFICATION_LIMIT: Magnification limit (copybit support) + * B2R2_BLT_CAP_SCALING_FRAC_BITS: Number of scaling fractional bits (copybit + * support) + * B2R2_BLT_CAP_ROTATION_STEP_DEG: Supported rotation step in degrees (copybit + * support) + */ + +enum b2r2_blt_cap { + B2R2_BLT_CAP_UNUSED = 0, + /** + * @brief Is format supported as source. + */ + B2R2_BLT_CAP_FMT_SOURCE, + /** + * @brief Is format supported as source mask + */ + B2R2_BLT_CAP_FMT_SOURCE_MASK, + /** + * @brief Is format supported as destination + */ + B2R2_BLT_CAP_FMT_DEST, + /** + * @brief Is per pixel alpha blending supported with format as source + */ + B2R2_BLT_CAP_PER_PIXEL_ALPHA_BLEND, + /** + * @brief Is global alpha blending supported with format as source + */ + B2R2_BLT_CAP_GLOBAL_ALPHA_BLEND, + /** + * @brief Is source color key supported with format as source + */ + B2R2_BLT_CAP_SOURCE_COLOR_KEY, + /** + * @brief Is source fill supported with format as source + */ + B2R2_BLT_CAP_SOURCE_FILL, + /** + * @brief Is source fill raw supported with format as dest + */ + B2R2_BLT_CAP_SOURCE_FILL_RAW, + /** + * @brief Is dest color key supported with format as dest + */ + B2R2_BLT_CAP_DEST_COLOR_KEY, + /** + * @brief Is dithering supported with format as source + */ + B2R2_BLT_CAP_DITHER, + /** + * @brief Is blur supported with format as source + */ + B2R2_BLT_CAP_BLUR, + /** + * @brief Minification limit (copybit support) + */ + B2R2_BLT_CAP_MINIFICATION_LIMIT, + /** + * @brief Magnification limit (copybit support) + */ + B2R2_BLT_CAP_MAGNIFICATION_LIMIT, + /** + * @brief Number of scaling fractional bits (copybit support) + */ + B2R2_BLT_CAP_SCALING_FRAC_BITS, + /** + * @brief Supported rotation step in degrees (copybit support) + */ + B2R2_BLT_CAP_ROTATION_STEP_DEG, +}; + +/** + * struct b2r2_blt_query_cap - Query B2R2 capabilities + * + * fmt: Format to query capabilities for or BLT_FMT_UNUSED for all + * cap: Capability to query for + * result: Returned capability. Interpretaion of this variable varies + * with the capability queried + */ +struct b2r2_blt_query_cap { + enum b2r2_blt_fmt fmt; + enum b2r2_blt_cap cap; + __u32 result; +}; + +/** + * struct b2r2_blt_report - Report from B2R2 driver back to user space + * + * This structure can be read from B2R2 driver if B2R2_BLT_FLAG_REPORT_WHEN_DONE + * flag was specified when the request was issued. + * + * @request_id: The id for the request, same as reported from blt_request + * @report1: Client data specified in struct blt_request + * @report2: Client data specified in struct blt_request + * @usec_elapsed: Number of microseconds needed to perform this blit + * if B2R2_BLT_FLAG_REPORT_PERFORMANCE was specified when the + * request was issued. + * + */ +struct b2r2_blt_report { + __u32 request_id; + __u32 report1; + __u32 report2; + __u32 usec_elapsed; +}; + +/** + * B2R2 BLT driver is used in the following way: + * + * Obtain a file descriptor to the driver: + * fd = open("/dev/b2r2_blt", O_RDWR); + * + * Issue requests: + * struct b2r2_blt_request blt_request; + * blt_request.size = sizeof(blt_request); + * ... Fill request with data... + * + * request_id = ioctl(fd, B2R2_BLT_IOC, (__u32) &blt_request); + * + * Wait for a request to finish + * ret = ioctl(fd, B2R2_BLT_SYNCH_IOC, (__u32) request_id); + * + * Wait for all requests from this context to finish + * ret = ioctl(fd, B2R2_BLT_SYNCH_IOC, (__u32) 0); + * + * Wait indefinitely for report data from driver: + * pollfd.fd = fd + * pollfd.events = 0xFFFFFFFF; + * pollfd.revents = 0; + * ret = poll(&pollfd, 1, -1); + * + * Read report data from driver + * struct b2r2_blt_report blt_report; + * + * nread = read(fd, &blt_report, sizeof(blt_report)); + * + * Close the driver + * close(fd); + */ + +/* B2R2 BLT IOCTLS */ + +/** + * B2R2_BLT_IOC_MAGIC is ioctl type group for B2R2 driver + */ +#define B2R2_BLT_IOC_MAGIC 0xb2 + +/** + * The B2R2_BLT_IOC ioctl adds a blit request to B2R2. + * + * The ioctl returns when the blit has been performed if not + * asynchronous execution has been specified. If asynchronous, + * control is returned as soon as the request has been queued. + * + * Supplied parameter shall be a pointer to a struct b2r2_blt_req. + * + * Returns an unique request id if >= 0, else a negative error code. + * This request id can be waited for using B2R2_BLT_SYNC_IOC. + * Return values: -ESOMERROR Description of an error + */ +#define B2R2_BLT_IOC _IOW(B2R2_BLT_IOC_MAGIC, 1, struct b2r2_blt_req) + +/** + * The B2R2_BLT_SYNC_IOC waits for all or a specified request to be finished. + * + * Supplied parameter shall be a request id previously returned by + * B2R2_BLT_IOC or 0 for all requests. + * + * Returns 0 if OK, else a negative error code + * Return value: -ESOMERROR Description of an error + */ +#define B2R2_BLT_SYNCH_IOC _IOW(B2R2_BLT_IOC_MAGIC, 2, int) + +/** + * The BLT_QUERY_CAP_IOC returns capability information for all or + * for a certain format + * + * Supplied parameter shall be a pointer to a struct b2r2_blt_query_cap. + * + * @return Returns 0 if OK, else a negative error code + * @retval -ESOMERROR Description of an error + */ +#define B2R2_BLT_QUERY_CAP_IOC _IOWR(B2R2_BLT_IOC_MAGIC, 3, \ + struct b2r2_blt_query_cap) + +#endif /* #ifdef _LINUX_VIDEO_B2R2_BLT_H */ diff --git a/include/video/hdmi.h b/include/video/hdmi.h new file mode 100644 index 00000000000..55dcd003fcd --- /dev/null +++ b/include/video/hdmi.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * HDMI driver + * + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __HDMI__H__ +#define __HDMI__H__ + +#define HDMI_RESULT_OK 0 +#define HDMI_RESULT_NOT_OK 1 +#define HDMI_AES_NOT_FUSED 2 +#define HDMI_RESULT_CRC_MISMATCH 3 + +#define HDMI_CEC_READ_MAXSIZE 16 +#define HDMI_CEC_WRITE_MAXSIZE 15 +#define HDMI_INFOFRAME_MAX_SIZE 27 +#define HDMI_HDCP_FUSEAES_KEYSIZE 16 +#define HDMI_HDCP_AES_BLOCK_START 128 +#define HDMI_HDCP_KSV_BLOCK 40 +#define HDMI_HDCP_AES_NR_OF_BLOCKS 18 +#define HDMI_HDCP_AES_KEYSIZE 16 +#define HDMI_HDCP_AES_KSVSIZE 5 +#define HDMI_HDCP_AES_KSVZEROESSIZE 3 +#define HDMI_EDID_DATA_SIZE 128 +#define HDMI_CEC_SIZE 15 +#define HDMI_INFOFR_SIZE 27 +#define HDMI_FUSE_KEYSIZE 16 +#define HDMI_AES_KSVSIZE 5 +#define HDMI_AES_KEYSIZE 288 +#define HDMI_CRC32_SIZE 4 +#define HDMI_HDCPAUTHRESP_SIZE 126 + +#define HDMI_STOREASTEXT_TEXT_SIZE 2 +#define HDMI_STOREASTEXT_BIN_SIZE 1 +#define HDMI_PLUGDETEN_TEXT_SIZE 6 +#define HDMI_PLUGDETEN_BIN_SIZE 3 +#define HDMI_EDIDREAD_TEXT_SIZE 4 +#define HDMI_EDIDREAD_BIN_SIZE 2 +#define HDMI_CECEVEN_TEXT_SIZE 2 +#define HDMI_CECEVEN_BIN_SIZE 1 +#define HDMI_CECSEND_TEXT_SIZE_MAX 37 +#define HDMI_CECSEND_TEXT_SIZE_MIN 6 +#define HDMI_CECSEND_BIN_SIZE_MAX 18 +#define HDMI_CECSEND_BIN_SIZE_MIN 3 +#define HDMI_INFOFRSEND_TEXT_SIZE_MIN 8 +#define HDMI_INFOFRSEND_TEXT_SIZE_MAX 63 +#define HDMI_INFOFRSEND_BIN_SIZE_MIN 4 +#define HDMI_INFOFRSEND_BIN_SIZE_MAX 31 +#define HDMI_HDCPEVEN_TEXT_SIZE 2 +#define HDMI_HDCPEVEN_BIN_SIZE 1 +#define HDMI_HDCP_FUSEAES_TEXT_SIZE 34 +#define HDMI_HDCP_FUSEAES_BIN_SIZE 17 +#define HDMI_HDCP_LOADAES_TEXT_SIZE 594 +#define HDMI_HDCP_LOADAES_BIN_SIZE 297 +#define HDMI_HDCPAUTHENCR_TEXT_SIZE 4 +#define HDMI_HDCPAUTHENCR_BIN_SIZE 2 +#define HDMI_EVCLR_TEXT_SIZE 2 +#define HDMI_EVCLR_BIN_SIZE 1 +#define HDMI_AUDIOCFG_TEXT_SIZE 14 +#define HDMI_AUDIOCFG_BIN_SIZE 7 +#define HDMI_POWERONOFF_TEXT_SIZE 2 +#define HDMI_POWERONOFF_BIN_SIZE 1 + +#define HDMI_IOC_MAGIC 0xcc + +/** IOCTL Operations */ +#define IOC_PLUG_DETECT_ENABLE _IOWR(HDMI_IOC_MAGIC, 1, int) +#define IOC_EDID_READ _IOWR(HDMI_IOC_MAGIC, 2, int) +#define IOC_CEC_EVENT_ENABLE _IOWR(HDMI_IOC_MAGIC, 3, int) +#define IOC_CEC_READ _IOWR(HDMI_IOC_MAGIC, 4, int) +#define IOC_CEC_SEND _IOWR(HDMI_IOC_MAGIC, 5, int) +#define IOC_INFOFRAME_SEND _IOWR(HDMI_IOC_MAGIC, 6, int) +#define IOC_HDCP_EVENT_ENABLE _IOWR(HDMI_IOC_MAGIC, 7, int) +#define IOC_HDCP_CHKAESOTP _IOWR(HDMI_IOC_MAGIC, 8, int) +#define IOC_HDCP_FUSEAES _IOWR(HDMI_IOC_MAGIC, 9, int) +#define IOC_HDCP_LOADAES _IOWR(HDMI_IOC_MAGIC, 10, int) +#define IOC_HDCP_AUTHENCR_REQ _IOWR(HDMI_IOC_MAGIC, 11, int) +#define IOC_HDCP_STATE_GET _IOWR(HDMI_IOC_MAGIC, 12, int) +#define IOC_EVENTS_READ _IOWR(HDMI_IOC_MAGIC, 13, int) +#define IOC_EVENTS_CLEAR _IOWR(HDMI_IOC_MAGIC, 14, int) +#define IOC_AUDIO_CFG _IOWR(HDMI_IOC_MAGIC, 15, int) +#define IOC_PLUG_STATUS _IOWR(HDMI_IOC_MAGIC, 16, int) +#define IOC_POWERONOFF _IOWR(HDMI_IOC_MAGIC, 17, int) +#define IOC_EVENT_WAKEUP _IOWR(HDMI_IOC_MAGIC, 18, int) +#define IOC_POWERSTATE _IOWR(HDMI_IOC_MAGIC, 19, int) + + +/* HDMI driver */ +void hdmi_event(enum av8100_hdmi_event); +int hdmi_init(void); +void hdmi_exit(void); + +enum hdmi_event { + HDMI_EVENT_NONE = 0x0, + HDMI_EVENT_HDMI_PLUGIN = 0x1, + HDMI_EVENT_HDMI_PLUGOUT = 0x2, + HDMI_EVENT_CEC = 0x4, + HDMI_EVENT_HDCP = 0x8, + HDMI_EVENT_CECTXERR = 0x10, + HDMI_EVENT_WAKEUP = 0x20, + HDMI_EVENT_CECTX = 0x40, +}; + +enum hdmi_hdcp_auth_type { + HDMI_HDCP_AUTH_OFF = 0, + HDMI_HDCP_AUTH_START = 1, + HDMI_HDCP_AUTH_REV_LIST_REQ = 2, + HDMI_HDCP_AUTH_CONT = 3, +}; + +enum hdmi_hdcp_encr_type { + HDMI_HDCP_ENCR_OESS = 0, + HDMI_HDCP_ENCR_EESS = 1, +}; + +struct plug_detect { + __u8 hdmi_detect_enable; + __u8 on_time; + __u8 hdmi_off_time; +}; + +struct edid_read { + __u8 address; + __u8 block_nr; + __u8 data_length; + __u8 data[HDMI_EDID_DATA_SIZE]; +}; + +struct cec_rw { + __u8 src; + __u8 dest; + __u8 length; + __u8 data[HDMI_CEC_SIZE]; +}; + +struct info_fr { + __u8 type; + __u8 ver; + __u8 crc; + __u8 length; + __u8 data[HDMI_INFOFR_SIZE]; +}; + +struct hdcp_fuseaes { + __u8 key[HDMI_FUSE_KEYSIZE]; + __u8 crc; + __u8 result; +}; + +struct hdcp_loadaesall { + __u8 key[HDMI_AES_KEYSIZE]; + __u8 ksv[HDMI_AES_KSVSIZE]; + __u8 crc32[HDMI_CRC32_SIZE]; + __u8 result; +}; + + +/* hdcp_authencr resp coding + * + * When encr_type is 2 (request revoc list), the response is given by + * resp_size is != 0 and resp containing the folllowing: + * + * __u8[5] Bksv from sink (not belonging to revocation list) + * __u8 Device count + * Additional output if Nrofdevices > 0: + * __u8[5 * Nrofdevices] Bksv per connected equipment + * __u8[20] SHA signature + * + * Device count coding: + * 0 = a simple receiver is connected + * 0x80 = a repeater is connected without downstream equipment + * 0x81 = a repeater is connected with one downstream equipment + * up to 0x94 = (0x80 + 0x14) a repeater is connected with downstream + * equipment (thus up to 20 connected equipments) + * 1 = repeater without sink equipment connected + * >1 = number of connected equipment on the repeater + * Nrofdevices = Device count & 0x7F (max 20) + * + * Max resp_size is 5 + 1 + 5 * 20 + 20 = 126 bytes + * + */ +struct hdcp_authencr { + __u8 auth_type; + __u8 encr_type; + __u8 result; + __u8 resp_size; + __u8 resp[HDMI_HDCPAUTHRESP_SIZE]; +}; + +struct audio_cfg { + __u8 if_format; + __u8 i2s_entries; + __u8 freq; + __u8 word_length; + __u8 format; + __u8 if_mode; + __u8 mute; +}; + +#endif /* __HDMI__H__ */ diff --git a/include/video/mcde.h b/include/video/mcde.h new file mode 100644 index 00000000000..b81d88af5fd --- /dev/null +++ b/include/video/mcde.h @@ -0,0 +1,448 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE base driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE__H__ +#define __MCDE__H__ + +/* Physical interface types */ +enum mcde_port_type { + MCDE_PORTTYPE_DSI = 0, + MCDE_PORTTYPE_DPI = 1, +}; + +/* Interface mode */ +enum mcde_port_mode { + MCDE_PORTMODE_CMD = 0, + MCDE_PORTMODE_VID = 1, +}; + +/* MCDE fifos */ +enum mcde_fifo { + MCDE_FIFO_A = 0, + MCDE_FIFO_B = 1, + MCDE_FIFO_C0 = 2, + MCDE_FIFO_C1 = 3, +}; + +/* MCDE channels (pixel pipelines) */ +enum mcde_chnl { + MCDE_CHNL_A = 0, + MCDE_CHNL_B = 1, + MCDE_CHNL_C0 = 2, + MCDE_CHNL_C1 = 3, +}; + +/* Channel path */ +#define MCDE_CHNLPATH(__chnl, __fifo, __type, __ifc, __link) \ + (((__chnl) << 16) | ((__fifo) << 12) | \ + ((__type) << 8) | ((__ifc) << 4) | ((__link) << 0)) +enum mcde_chnl_path { + /* Channel A */ + MCDE_CHNLPATH_CHNLA_FIFOA_DPI_0 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_A, MCDE_PORTTYPE_DPI, 0, 0), + MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0), + MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1), + MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2), + MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0), + MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1), + MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_A, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2), + /* Channel B */ + MCDE_CHNLPATH_CHNLB_FIFOB_DPI_1 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_B, MCDE_PORTTYPE_DPI, 0, 1), + MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0), + MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1), + MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2), + MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0), + MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1), + MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_B, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2), + /* Channel C0 */ + MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0), + MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1), + MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2), + MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0), + MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1), + MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C0, + MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2), + /* Channel C1 */ + MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0), + MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1), + MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2), + MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0), + MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1), + MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C1, + MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2), +}; + +/* Update sync mode */ +enum mcde_sync_src { + MCDE_SYNCSRC_OFF = 0, /* No sync */ + MCDE_SYNCSRC_TE0 = 1, /* MCDE ext TE0 */ + MCDE_SYNCSRC_TE1 = 2, /* MCDE ext TE1 */ + MCDE_SYNCSRC_BTA = 3, /* DSI BTA */ + MCDE_SYNCSRC_TE_POLLING = 4, /* DSI TE_POLLING */ +}; + +/* Interface pixel formats (output) */ +/* +* REVIEW: Define formats +* Add explanatory comments how the formats are ordered in memory +*/ +enum mcde_port_pix_fmt { + /* MIPI standard formats */ + + MCDE_PORTPIXFMT_DPI_16BPP_C1 = 0x21, + MCDE_PORTPIXFMT_DPI_16BPP_C2 = 0x22, + MCDE_PORTPIXFMT_DPI_16BPP_C3 = 0x23, + MCDE_PORTPIXFMT_DPI_18BPP_C1 = 0x24, + MCDE_PORTPIXFMT_DPI_18BPP_C2 = 0x25, + MCDE_PORTPIXFMT_DPI_24BPP = 0x26, + + MCDE_PORTPIXFMT_DSI_16BPP = 0x31, + MCDE_PORTPIXFMT_DSI_18BPP = 0x32, + MCDE_PORTPIXFMT_DSI_18BPP_PACKED = 0x33, + MCDE_PORTPIXFMT_DSI_24BPP = 0x34, + + /* Custom formats */ + MCDE_PORTPIXFMT_DSI_YCBCR422 = 0x40, +}; + +enum mcde_hdmi_sdtv_switch { + HDMI_SWITCH, + SDTV_SWITCH, + DVI_SWITCH +}; + +enum mcde_col_convert { + MCDE_CONVERT_RGB_2_RGB, + MCDE_CONVERT_RGB_2_YCBCR, + MCDE_CONVERT_YCBCR_2_RGB, + MCDE_CONVERT_YCBCR_2_YCBCR, +}; + +struct mcde_col_transform { + u16 matrix[3][3]; + u16 offset[3]; +}; + +#define MCDE_PORT_DPI_NO_CLOCK_DIV 0 + +#define DPI_ACT_HIGH_ALL 0 /* all signals are active high */ +#define DPI_ACT_LOW_HSYNC 1 /* horizontal sync signal is active low */ +#define DPI_ACT_LOW_VSYNC 2 /* vertical sync signal is active low */ +#define DPI_ACT_LOW_DATA_ENABLE 4 /* data enable signal is active low */ +#define DPI_ACT_ON_FALLING_EDGE 8 /* drive data on the falling edge of the + * pixel clock + */ + +struct mcde_port { + enum mcde_port_type type; + enum mcde_port_mode mode; + enum mcde_port_pix_fmt pixel_format; + u8 ifc; + u8 link; + enum mcde_sync_src sync_src; + bool update_auto_trig; + enum mcde_hdmi_sdtv_switch hdmi_sdtv_switch; + union { + struct { + u8 virt_id; + u8 num_data_lanes; + u8 ui; + bool clk_cont; + + /* DSI data lanes are swapped if true */ + bool data_lanes_swap; + } dsi; + struct { + u8 bus_width; + bool tv_mode; + u16 clock_div; /* use 0 or 1 for no clock divider */ + u32 polarity; /* see DPI_ACT_LOW_* definitions */ + } dpi; + } phy; +}; + +/* Overlay pixel formats (input) *//* REVIEW: Define byte order */ +enum mcde_ovly_pix_fmt { + MCDE_OVLYPIXFMT_RGB565 = 1, + MCDE_OVLYPIXFMT_RGBA5551 = 2, + MCDE_OVLYPIXFMT_RGBA4444 = 3, + MCDE_OVLYPIXFMT_RGB888 = 4, + MCDE_OVLYPIXFMT_RGBX8888 = 5, + MCDE_OVLYPIXFMT_RGBA8888 = 6, + MCDE_OVLYPIXFMT_YCbCr422 = 7, +}; + +/* Display power modes */ +enum mcde_display_power_mode { + MCDE_DISPLAY_PM_OFF = 0, /* Power off */ + MCDE_DISPLAY_PM_STANDBY = 1, /* DCS sleep mode */ + MCDE_DISPLAY_PM_ON = 2, /* DCS normal mode, display on */ +}; + +/* Display rotation */ +enum mcde_display_rotation { + MCDE_DISPLAY_ROT_0 = 0, + MCDE_DISPLAY_ROT_90_CCW = 90, + MCDE_DISPLAY_ROT_180_CCW = 180, + MCDE_DISPLAY_ROT_270_CCW = 270, + MCDE_DISPLAY_ROT_90_CW = MCDE_DISPLAY_ROT_270_CCW, + MCDE_DISPLAY_ROT_180_CW = MCDE_DISPLAY_ROT_180_CCW, + MCDE_DISPLAY_ROT_270_CW = MCDE_DISPLAY_ROT_90_CCW, +}; + +/* REVIEW: Verify */ +#define MCDE_MIN_WIDTH 16 +#define MCDE_MIN_HEIGHT 16 +#define MCDE_MAX_WIDTH 2048 +#define MCDE_MAX_HEIGHT 2048 +#define MCDE_BUF_START_ALIGMENT 8 +#define MCDE_BUF_LINE_ALIGMENT 8 + +#define MCDE_FIFO_AB_SIZE 640 +#define MCDE_FIFO_C0C1_SIZE 160 + +#define MCDE_INPUT_FIFO_SIZE_4_0_4 80 +#define MCDE_INPUT_FIFO_SIZE_3_0_8 128 + +/* Tv-out defines */ +#define MCDE_CONFIG_TVOUT_HBORDER 2 +#define MCDE_CONFIG_TVOUT_VBORDER 2 +#define MCDE_CONFIG_TVOUT_BACKGROUND_LUMINANCE 0x83 +#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CB 0x9C +#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CR 0x2C + +/* In seconds */ +#define MCDE_AUTO_SYNC_WATCHDOG 5 + +/* Hardware versions */ +#define MCDE_CHIP_VERSION_4_0_4 4 /* U5500 V2 */ +#define MCDE_CHIP_VERSION_1_0_4 3 /* U5500 V1 */ +#define MCDE_CHIP_VERSION_3_0_8 2 /* U8500 V2 */ +#define MCDE_CHIP_VERSION_3_0_5 1 /* U8500 V1 */ +#define MCDE_CHIP_VERSION_3 0 + +/* DSI modes */ +#define DSI_VIDEO_MODE 0 +#define DSI_CMD_MODE 1 + +/* Video mode descriptor */ +struct mcde_video_mode { + u32 xres; + u32 yres; + u32 pixclock; /* pixel clock in ps (pico seconds) */ + u32 hbp; /* horizontal back porch: left margin (excl. hsync) */ + u32 hfp; /* horizontal front porch: right margin (excl. hsync) */ + u32 hsw; /* horizontal sync width */ + u32 vbp; /* vertical back porch: upper margin (excl. vsync) */ + u32 vfp; /* vertical front porch: lower margin (excl. vsync) */ + u32 vsw; /* vertical sync width*/ + bool interlaced; + bool force_update; /* when switching between hdmi and sdtv */ +}; + +struct mcde_rectangle { + u16 x; + u16 y; + u16 w; + u16 h; +}; + +struct mcde_overlay_info { + u32 paddr; + u32 *vaddr; + u16 stride; /* buffer line len in bytes */ + enum mcde_ovly_pix_fmt fmt; + + u16 src_x; + u16 src_y; + u16 dst_x; + u16 dst_y; + u16 dst_z; + u16 w; + u16 h; + struct mcde_rectangle dirty; +}; + +struct mcde_overlay { + struct kobject kobj; + struct list_head list; /* mcde_display_device.ovlys */ + + struct mcde_display_device *ddev; + struct mcde_overlay_info info; + struct mcde_ovly_state *state; +}; + +/* + * Three functions for mapping 8 bits colour channels on 12 bits colour + * channels. The colour channels (ch0, ch1, ch2) can represent (r, g, b) or + * (Y, Cb, Cr) respectively. + */ +struct mcde_palette_table { + u16 (*map_col_ch0)(u8); + u16 (*map_col_ch1)(u8); + u16 (*map_col_ch2)(u8); +}; + +struct mcde_chnl_state; + +struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id, + enum mcde_fifo fifo, const struct mcde_port *port); +int mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl, + enum mcde_port_pix_fmt pix_fmt); +int mcde_chnl_set_palette(struct mcde_chnl_state *chnl, + struct mcde_palette_table *palette); +void mcde_chnl_set_col_convert(struct mcde_chnl_state *chnl, + struct mcde_col_transform *transform, + enum mcde_col_convert convert); +int mcde_chnl_set_video_mode(struct mcde_chnl_state *chnl, + struct mcde_video_mode *vmode); +/* TODO: Remove rotbuf* parameters when ESRAM allocator is implemented*/ +int mcde_chnl_set_rotation(struct mcde_chnl_state *chnl, + enum mcde_display_rotation rotation, u32 rotbuf1, u32 rotbuf2); +int mcde_chnl_enable_synchronized_update(struct mcde_chnl_state *chnl, + bool enable); +int mcde_chnl_set_power_mode(struct mcde_chnl_state *chnl, + enum mcde_display_power_mode power_mode); + +int mcde_chnl_apply(struct mcde_chnl_state *chnl); +int mcde_chnl_update(struct mcde_chnl_state *chnl, + struct mcde_rectangle *update_area, + bool tripple_buffer); +void mcde_chnl_put(struct mcde_chnl_state *chnl); + +void mcde_chnl_stop_flow(struct mcde_chnl_state *chnl); + +void mcde_chnl_enable(struct mcde_chnl_state *chnl); +void mcde_chnl_disable(struct mcde_chnl_state *chnl); + +/* MCDE overlay */ +struct mcde_ovly_state; + +struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl); +void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly, + u32 paddr); +void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly, + u32 stride, enum mcde_ovly_pix_fmt pix_fmt); +void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly, + u16 x, u16 y, u16 w, u16 h); +void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly, + u16 x, u16 y, u8 z); +void mcde_ovly_apply(struct mcde_ovly_state *ovly); +void mcde_ovly_put(struct mcde_ovly_state *ovly); + +/* MCDE dsi */ + +#define DCS_CMD_ENTER_IDLE_MODE 0x39 +#define DCS_CMD_ENTER_INVERT_MODE 0x21 +#define DCS_CMD_ENTER_NORMAL_MODE 0x13 +#define DCS_CMD_ENTER_PARTIAL_MODE 0x12 +#define DCS_CMD_ENTER_SLEEP_MODE 0x10 +#define DCS_CMD_EXIT_IDLE_MODE 0x38 +#define DCS_CMD_EXIT_INVERT_MODE 0x20 +#define DCS_CMD_EXIT_SLEEP_MODE 0x11 +#define DCS_CMD_GET_ADDRESS_MODE 0x0B +#define DCS_CMD_GET_BLUE_CHANNEL 0x08 +#define DCS_CMD_GET_DIAGNOSTIC_RESULT 0x0F +#define DCS_CMD_GET_DISPLAY_MODE 0x0D +#define DCS_CMD_GET_GREEN_CHANNEL 0x07 +#define DCS_CMD_GET_PIXEL_FORMAT 0x0C +#define DCS_CMD_GET_POWER_MODE 0x0A +#define DCS_CMD_GET_RED_CHANNEL 0x06 +#define DCS_CMD_GET_SCANLINE 0x45 +#define DCS_CMD_GET_SIGNAL_MODE 0x0E +#define DCS_CMD_NOP 0x00 +#define DCS_CMD_READ_DDB_CONTINUE 0xA8 +#define DCS_CMD_READ_DDB_START 0xA1 +#define DCS_CMD_READ_MEMORY_CONTINE 0x3E +#define DCS_CMD_READ_MEMORY_START 0x2E +#define DCS_CMD_SET_ADDRESS_MODE 0x36 +#define DCS_CMD_SET_COLUMN_ADDRESS 0x2A +#define DCS_CMD_SET_DISPLAY_OFF 0x28 +#define DCS_CMD_SET_DISPLAY_ON 0x29 +#define DCS_CMD_SET_GAMMA_CURVE 0x26 +#define DCS_CMD_SET_PAGE_ADDRESS 0x2B +#define DCS_CMD_SET_PARTIAL_AREA 0x30 +#define DCS_CMD_SET_PIXEL_FORMAT 0x3A +#define DCS_CMD_SET_SCROLL_AREA 0x33 +#define DCS_CMD_SET_SCROLL_START 0x37 +#define DCS_CMD_SET_TEAR_OFF 0x34 +#define DCS_CMD_SET_TEAR_ON 0x35 +#define DCS_CMD_SET_TEAR_SCANLINE 0x44 +#define DCS_CMD_SOFT_RESET 0x01 +#define DCS_CMD_WRITE_LUT 0x2D +#define DCS_CMD_WRITE_CONTINUE 0x3C +#define DCS_CMD_WRITE_START 0x2C + +#define MCDE_MAX_DCS_READ 4 +#define MCDE_MAX_DSI_DIRECT_CMD_WRITE 15 + +int mcde_dsi_generic_write(struct mcde_chnl_state *chnl, u8* para, int len); +int mcde_dsi_dcs_write(struct mcde_chnl_state *chnl, + u8 cmd, u8 *data, int len); +int mcde_dsi_dcs_read(struct mcde_chnl_state *chnl, + u8 cmd, u32 *data, int *len); +int mcde_dsi_set_max_pkt_size(struct mcde_chnl_state *chnl); + +/* MCDE */ + +/* Driver data */ +#define MCDE_IRQ "MCDE IRQ" +#define MCDE_IO_AREA "MCDE I/O Area" + +struct mcde_platform_data { + /* DSI */ + int num_dsilinks; + + /* DPI */ + u8 outmux[5]; /* MCDE_CONF0.OUTMUXx */ + u8 syncmux; /* MCDE_CONF0.SYNCMUXx */ + + const char *regulator_vana_id; + const char *regulator_mcde_epod_id; + const char *regulator_esram_epod_id; + int num_channels; + int num_overlays; + const char *clock_dsi_id; + const char *clock_dsi_lp_id; + const char *clock_dpi_id; + const char *clock_mcde_id; + + int (*platform_set_clocks)(void); + int (*platform_enable_dsipll)(void); + int (*platform_disable_dsipll)(void); +}; + +int mcde_init(void); +void mcde_exit(void); + +#endif /* __MCDE__H__ */ diff --git a/include/video/mcde_display-ab8500.h b/include/video/mcde_display-ab8500.h new file mode 100644 index 00000000000..ffebe62af92 --- /dev/null +++ b/include/video/mcde_display-ab8500.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * AB8500 tvout driver interface + * + * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __DISPLAY_AB8500__H__ +#define __DISPLAY_AB8500__H__ + +#include <video/mcde.h> + +struct ab8500_display_platform_data { + /* Platform info */ + struct mcde_col_transform *rgb_2_yCbCr_transform; + int nr_regulators; + const char *regulator_id[]; +}; + +#endif /* __DISPLAY_AB8500__H__*/ + diff --git a/include/video/mcde_display-av8100.h b/include/video/mcde_display-av8100.h new file mode 100644 index 00000000000..52578a675f1 --- /dev/null +++ b/include/video/mcde_display-av8100.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE HDMI display driver + * + * Author: Per Persson <per-xb-persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __DISPLAY_AV8100__H__ +#define __DISPLAY_AV8100__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +#define GPIO_AV8100_RSTN 196 +#define NATIVE_XRES_HDMI 1280 +#define NATIVE_YRES_HDMI 720 +#define NATIVE_XRES_SDTV 720 +#define NATIVE_YRES_SDTV 576 +#define DISPONOFF_SIZE 6 +#define TIMING_SIZE 2 +#define STAYALIVE_SIZE 1 + +struct mcde_display_hdmi_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + const char *cvbs_regulator_id; + int reset_delay; /* ms */ + u32 ddb_id; + struct mcde_col_transform *rgb_2_yCbCr_transform; + + /* Driver data */ /* TODO: move to driver data instead */ + bool hdmi_platform_enable; + struct regulator *regulator; +}; + +struct display_driver_data { + struct regulator *cvbs_regulator; + bool cvbs_regulator_enabled; + bool update_port_pixel_format; + char *fbdevname; + struct mcde_video_mode *video_mode; +}; + +void hdmi_fb_onoff(struct mcde_display_device *ddev, bool enable, + u8 cea, u8 vesa_cea_nr); + +#endif /* __DISPLAY_AV8100__H__ */ diff --git a/include/video/mcde_display-generic_dsi.h b/include/video/mcde_display-generic_dsi.h new file mode 100644 index 00000000000..87ef6baf67a --- /dev/null +++ b/include/video/mcde_display-generic_dsi.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE generic DCS display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY_GENERIC__H__ +#define __MCDE_DISPLAY_GENERIC__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +struct mcde_display_generic_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + int reset_delay; /* ms */ + int sleep_out_delay; /* ms */ + u32 ddb_id; + + /* Driver data */ + bool generic_platform_enable; + struct regulator *regulator; + int max_supply_voltage; + int min_supply_voltage; +}; + +#endif /* __MCDE_DISPLAY_GENERIC__H__ */ + diff --git a/include/video/mcde_display-sony_acx424akp_dsi.h b/include/video/mcde_display-sony_acx424akp_dsi.h new file mode 100644 index 00000000000..9f656fdcc3b --- /dev/null +++ b/include/video/mcde_display-sony_acx424akp_dsi.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE Sony acx424akp DCS display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY_SONY_ACX424AKP__H__ +#define __MCDE_DISPLAY_SONY_ACX424AKP__H__ + +enum display_panel_type { + DISPLAY_NONE = 0, + DISPLAY_SONY_ACX424AKP = 0x1b81, +}; + +struct mcde_display_sony_acx424akp_platform_data { + /* Platform info */ + int reset_gpio; + enum display_panel_type disp_panel; /* display panel types */ +}; + +#endif /* __MCDE_DISPLAY_SONY_ACX424AKP__H__ */ + diff --git a/include/video/mcde_display-vuib500-dpi.h b/include/video/mcde_display-vuib500-dpi.h new file mode 100644 index 00000000000..94bad83bf97 --- /dev/null +++ b/include/video/mcde_display-vuib500-dpi.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE DPI display driver + * + * Author: Torbjorn Svensson <torbjorn.x.svensson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __MCDE_DISPLAY_DPI__H__ +#define __MCDE_DISPLAY_DPI__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +struct mcde_display_dpi_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + int reset_delay; + + /* Driver data */ + struct regulator *regulator; + int max_supply_voltage; + int min_supply_voltage; +}; +#endif /* __MCDE_DISPLAY_DPI__H__ */ diff --git a/include/video/mcde_display.h b/include/video/mcde_display.h new file mode 100644 index 00000000000..97326cbc28c --- /dev/null +++ b/include/video/mcde_display.h @@ -0,0 +1,149 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY__H__ +#define __MCDE_DISPLAY__H__ + +#include <linux/device.h> +#include <linux/pm.h> + +#include <video/mcde.h> + +#define UPDATE_FLAG_PIXEL_FORMAT 0x1 +#define UPDATE_FLAG_VIDEO_MODE 0x2 +#define UPDATE_FLAG_ROTATION 0x4 + +struct mcde_display_dsi_platform_data { + int reset_gpio; + int link; +}; + +#define to_mcde_display_device(__dev) \ + container_of((__dev), struct mcde_display_device, dev) + +struct mcde_display_device { + /* MCDE driver static */ + struct device dev; + const char *name; + int id; + struct mcde_port *port; + struct fb_info *fbi; + bool fictive; + + /* MCDE dss driver internal */ + bool initialized; + enum mcde_chnl chnl_id; + enum mcde_fifo fifo; + bool first_update; + struct mutex display_lock; + + bool enabled; + struct mcde_chnl_state *chnl_state; + struct list_head ovlys; + struct mcde_rectangle update_area; + /* TODO: Remove once ESRAM allocator is done */ + u32 rotbuf1; + u32 rotbuf2; + + /* Display driver internal */ + u16 native_x_res; + u16 native_y_res; + u16 physical_width; + u16 physical_height; + enum mcde_display_power_mode power_mode; + enum mcde_ovly_pix_fmt default_pixel_format; + enum mcde_ovly_pix_fmt pixel_format; + enum mcde_display_rotation rotation; + bool synchronized_update; + struct mcde_video_mode video_mode; + int update_flags; + bool stay_alive; + int check_transparency; + + /* Driver API */ + void (*get_native_resolution)(struct mcde_display_device *dev, + u16 *x_res, u16 *y_res); + enum mcde_ovly_pix_fmt (*get_default_pixel_format)( + struct mcde_display_device *dev); + void (*get_physical_size)(struct mcde_display_device *dev, + u16 *x_size, u16 *y_size); + + int (*set_power_mode)(struct mcde_display_device *dev, + enum mcde_display_power_mode power_mode); + enum mcde_display_power_mode (*get_power_mode)( + struct mcde_display_device *dev); + + int (*try_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + int (*set_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + void (*get_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + int (*set_pixel_format)(struct mcde_display_device *dev, + enum mcde_ovly_pix_fmt pix_fmt); + enum mcde_ovly_pix_fmt (*get_pixel_format)( + struct mcde_display_device *dev); + enum mcde_port_pix_fmt (*get_port_pixel_format)( + struct mcde_display_device *dev); + + int (*set_rotation)(struct mcde_display_device *dev, + enum mcde_display_rotation rotation); + enum mcde_display_rotation (*get_rotation)( + struct mcde_display_device *dev); + + int (*set_synchronized_update)(struct mcde_display_device *dev, + bool enable); + bool (*get_synchronized_update)(struct mcde_display_device *dev); + + int (*apply_config)(struct mcde_display_device *dev); + int (*invalidate_area)(struct mcde_display_device *dev, + struct mcde_rectangle *area); + int (*update)(struct mcde_display_device *dev, bool tripple_buffer); + int (*on_first_update)(struct mcde_display_device *dev); + int (*platform_enable)(struct mcde_display_device *dev); + int (*platform_disable)(struct mcde_display_device *dev); + int (*ceanr_convert)(struct mcde_display_device *ddev, + u8 cea, u8 vesa_cea_nr, int buffering, + u16 *w, u16 *h, u16 *vw, u16 *vh); +}; + +struct mcde_display_driver { + int (*probe)(struct mcde_display_device *dev); + int (*remove)(struct mcde_display_device *dev); + void (*shutdown)(struct mcde_display_device *dev); + int (*suspend)(struct mcde_display_device *dev, + pm_message_t state); + int (*resume)(struct mcde_display_device *dev); + + struct device_driver driver; +}; + +/* MCDE dsi (Used by MCDE display drivers) */ + +int mcde_display_dsi_dcs_write(struct mcde_display_device *dev, + u8 cmd, u8 *data, int len); +int mcde_display_dsi_dcs_read(struct mcde_display_device *dev, + u8 cmd, u8 *data, int *len); +int mcde_display_dsi_bta_sync(struct mcde_display_device *dev); + +/* MCDE display bus */ + +int mcde_display_driver_register(struct mcde_display_driver *drv); +void mcde_display_driver_unregister(struct mcde_display_driver *drv); +int mcde_display_device_register(struct mcde_display_device *dev); +void mcde_display_device_unregister(struct mcde_display_device *dev); + +void mcde_display_init_device(struct mcde_display_device *dev); + +int mcde_display_init(void); +void mcde_display_exit(void); + +#endif /* __MCDE_DISPLAY__H__ */ + diff --git a/include/video/mcde_dss.h b/include/video/mcde_dss.h new file mode 100644 index 00000000000..efed79ad023 --- /dev/null +++ b/include/video/mcde_dss.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display sub system driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DSS__H__ +#define __MCDE_DSS__H__ + +#include <linux/kobject.h> +#include <linux/notifier.h> + +#include "mcde.h" +#include "mcde_display.h" + +/* Public MCDE dss (Used by MCDE fb ioctl & MCDE display sysfs) */ +int mcde_dss_open_channel(struct mcde_display_device *ddev); +void mcde_dss_close_channel(struct mcde_display_device *ddev); +int mcde_dss_enable_display(struct mcde_display_device *ddev); +void mcde_dss_disable_display(struct mcde_display_device *ddev); +int mcde_dss_apply_channel(struct mcde_display_device *ddev); +struct mcde_overlay *mcde_dss_create_overlay(struct mcde_display_device *ddev, + struct mcde_overlay_info *info); +void mcde_dss_destroy_overlay(struct mcde_overlay *ovl); +int mcde_dss_enable_overlay(struct mcde_overlay *ovl); +void mcde_dss_disable_overlay(struct mcde_overlay *ovl); +int mcde_dss_apply_overlay(struct mcde_overlay *ovl, + struct mcde_overlay_info *info); +void mcde_dss_get_overlay_info(struct mcde_overlay *ovly, + struct mcde_overlay_info *info); +int mcde_dss_update_overlay(struct mcde_overlay *ovl, bool tripple_buffer); + +void mcde_dss_get_native_resolution(struct mcde_display_device *ddev, + u16 *x_res, u16 *y_res); +enum mcde_ovl_pix_fmt mcde_dss_get_default_color_format( + struct mcde_display_device *ddev); +void mcde_dss_get_physical_size(struct mcde_display_device *ddev, + u16 *x_size, u16 *y_size); /* mm */ + +int mcde_dss_try_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +int mcde_dss_set_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +void mcde_dss_get_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); + +int mcde_dss_set_pixel_format(struct mcde_display_device *ddev, + enum mcde_ovly_pix_fmt pix_fmt); +int mcde_dss_get_pixel_format(struct mcde_display_device *ddev); + +int mcde_dss_set_rotation(struct mcde_display_device *ddev, + enum mcde_display_rotation rotation); +enum mcde_display_rotation mcde_dss_get_rotation( + struct mcde_display_device *ddev); + +int mcde_dss_set_synchronized_update(struct mcde_display_device *ddev, + bool enable); +bool mcde_dss_get_synchronized_update(struct mcde_display_device *ddev); + +/* MCDE dss events */ + +/* A display device and driver has been loaded, probed and bound */ +#define MCDE_DSS_EVENT_DISPLAY_REGISTERED 1 +/* A display device has been removed */ +#define MCDE_DSS_EVENT_DISPLAY_UNREGISTERED 2 + +/* Note! Notifier callback will be called holding the dev sem */ +int mcde_dss_register_notifier(struct notifier_block *nb); +int mcde_dss_unregister_notifier(struct notifier_block *nb); + +/* MCDE dss driver */ + +int mcde_dss_init(void); +void mcde_dss_exit(void); + +#endif /* __MCDE_DSS__H__ */ + diff --git a/include/video/mcde_fb.h b/include/video/mcde_fb.h new file mode 100644 index 00000000000..17556414aa0 --- /dev/null +++ b/include/video/mcde_fb.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display sub system frame buffer driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_FB__H__ +#define __MCDE_FB__H__ + +#include <linux/fb.h> +#include <linux/ioctl.h> +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#else +#include <linux/types.h> +#include <linux/hwmem.h> +#endif + +#ifdef __KERNEL__ +#include "mcde_dss.h" +#ifdef CONFIG_HAS_EARLYSUSPEND +#include <linux/earlysuspend.h> +#endif +#endif + +#define MCDE_GET_BUFFER_NAME_IOC _IO('M', 1) + +#ifdef __KERNEL__ +#define to_mcde_fb(x) ((struct mcde_fb *)(x)->par) + +#define MCDE_FB_MAX_NUM_OVERLAYS 3 + +struct mcde_fb { + int num_ovlys; + struct mcde_overlay *ovlys[MCDE_FB_MAX_NUM_OVERLAYS]; + u32 pseudo_palette[17]; + enum mcde_ovly_pix_fmt pix_fmt; + int id; + struct hwmem_alloc *alloc; + int alloc_name; +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; + +/* MCDE fbdev API */ +struct fb_info *mcde_fb_create(struct mcde_display_device *ddev, + uint16_t w, uint16_t h, uint16_t vw, uint16_t vh, + enum mcde_ovly_pix_fmt pix_fmt, uint32_t rotate); + +int mcde_fb_attach_overlay(struct fb_info *fb_info, + struct mcde_overlay *ovl); +void mcde_fb_destroy(struct mcde_display_device *ddev); + +/* MCDE fb driver */ +int mcde_fb_init(void); +void mcde_fb_exit(void); +#endif + +#endif /* __MCDE_FB__H__ */ + |