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-rw-r--r--include/acpi/processor.h1
-rw-r--r--include/asm-blackfin/bfin-global.h5
-rw-r--r--include/asm-blackfin/cplbinit.h33
-rw-r--r--include/asm-blackfin/delay.h66
-rw-r--r--include/asm-blackfin/io.h1
-rw-r--r--include/asm-blackfin/mach-bf527/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h4
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h34
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h2
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h18
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h19
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h15
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h7
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h8
-rw-r--r--include/asm-blackfin/page_offset.h2
-rw-r--r--include/asm-blackfin/string.h2
-rw-r--r--include/asm-blackfin/traps.h96
-rw-r--r--include/asm-generic/resource.h2
-rw-r--r--include/asm-ia64/acpi.h1
-rw-r--r--include/asm-mips/8253pit.h10
-rw-r--r--include/asm-mips/dma.h1
-rw-r--r--include/asm-mips/futex.h6
-rw-r--r--include/asm-mips/i8253.h2
-rw-r--r--include/asm-mips/ip32/ip32_ints.h2
-rw-r--r--include/asm-mips/system.h8
-rw-r--r--include/asm-mips/time.h16
-rw-r--r--include/asm-powerpc/page_32.h4
-rw-r--r--include/asm-powerpc/pci-bridge.h5
-rw-r--r--include/asm-powerpc/rtas.h3
-rw-r--r--include/asm-powerpc/vdso_datapage.h8
-rw-r--r--include/asm-s390/system.h5
-rw-r--r--include/asm-sh/cacheflush.h2
-rw-r--r--include/asm-x86/acpi.h27
-rw-r--r--include/asm-x86/apic_32.h1
-rw-r--r--include/linux/acpi.h5
-rw-r--r--include/linux/cpuidle.h1
-rw-r--r--include/linux/libata.h5
-rw-r--r--include/linux/nfs_fs.h1
-rw-r--r--include/linux/sunrpc/debug.h5
-rw-r--r--include/linux/sysctl.h6
-rw-r--r--include/linux/timex.h1
-rw-r--r--include/sound/version.h2
49 files changed, 279 insertions, 191 deletions
diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 26d79f6db8a..76411b1fc4f 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -78,7 +78,6 @@ struct acpi_processor_cx {
struct acpi_processor_power {
struct cpuidle_device dev;
struct acpi_processor_cx *state;
- struct acpi_processor_cx *bm_state;
unsigned long bm_check_timestamp;
u32 default_state;
u32 bm_activity;
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 0212e180b90..39bdd86871c 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -50,8 +50,8 @@ extern unsigned long get_sclk(void);
extern unsigned long sclk_to_usecs(unsigned long sclk);
extern unsigned long usecs_to_sclk(unsigned long usecs);
-extern void dump_thread(struct pt_regs *regs, struct user *dump);
-extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr);
+extern void dump_bfin_process(struct pt_regs *regs);
+extern void dump_bfin_mem(void *retaddr);
extern void dump_bfin_trace_buffer(void);
extern int init_arch_irq(void);
@@ -63,6 +63,7 @@ extern void bfin_dcache_init(void);
extern int read_iloc(void);
extern int bfin_console_init(void);
extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
extern void init_exception_vectors(void);
extern void init_dma(void);
extern void program_IAR(void);
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bd..c4d0596e8e9 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,6 +27,9 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef __ASM_CPLBINIT_H__
+#define __ASM_CPLBINIT_H__
+
#include <asm/blackfin.h>
#include <asm/cplb.h>
@@ -57,8 +60,8 @@ struct cplb_tab {
u16 size;
};
-extern u_long icplb_table[MAX_CPLBS+1];
-extern u_long dcplb_table[MAX_CPLBS+1];
+extern u_long icplb_table[];
+extern u_long dcplb_table[];
/* Till here we are discussing about the static memory management model.
* However, the operating envoronments commonly define more CPLB
@@ -69,28 +72,16 @@ extern u_long dcplb_table[MAX_CPLBS+1];
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
*/
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
-
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
-#endif /* CONFIG_CPLB_INFO */
-
-#else
-
-extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
-extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
-
+extern u_long ipdt_table[];
+extern u_long dpdt_table[];
#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
-extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
-#endif /* CONFIG_CPLB_INFO */
-
-#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
+extern u_long ipdt_swapcount_table[];
+extern u_long dpdt_swapcount_table[];
+#endif
extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;
extern void generate_cpl_tables(void);
+
+#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 52e7a10d7ff..473a8113277 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,29 +1,47 @@
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-static inline void __delay(unsigned long loops)
-{
-
-/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
- uncomment this as soon those are implemented */
/*
- __asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t"
- "1:\t NOP;\n\t"
- : :"a" (loops)
- : "LT0","LB0","LC0");
+ * delay.h - delay functions
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_DELAY_H__
+#define __ASM_DELAY_H__
-*/
+#include <asm/mach/anomaly.h>
- __asm__ __volatile__("[--SP] = LC0;\n\t"
- "[--SP] = LT0;\n\t"
- "[--SP] = LB0;\n\t"
- "LSETUP (1f,1f) LC0 = %0;\n\t"
- "1:\t NOP;\n\t"
- "LB0 = [SP++];\n\t"
- "LT0 = [SP++];\n\t"
- "LC0 = [SP++];\n"
- :
- :"a" (loops));
+static inline void __delay(unsigned long loops)
+{
+ if (ANOMALY_05000312) {
+ /* Interrupted loads to loop registers -> bad */
+ unsigned long tmp;
+ __asm__ __volatile__(
+ "[--SP] = LC0;"
+ "[--SP] = LT0;"
+ "[--SP] = LB0;"
+ "LSETUP (1f,1f) LC0 = %1;"
+ "1: NOP;"
+ /* We take advantage of the fact that LC0 is 0 at
+ * the end of the loop. Otherwise we'd need some
+ * NOPs after the CLI here.
+ */
+ "CLI %0;"
+ "LB0 = [SP++];"
+ "LT0 = [SP++];"
+ "LC0 = [SP++];"
+ "STI %0;"
+ : "=d" (tmp)
+ : "a" (loops)
+ );
+ } else
+ __asm__ __volatile__ (
+ "LSETUP(1f, 1f) LC0 = %0;"
+ "1: NOP;"
+ :
+ : "a" (loops)
+ : "LT0", "LB0", "LC0"
+ );
}
#include <linux/param.h> /* needed for HZ */
@@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs)
__delay(usecs * loops_per_jiffy / (1000000 / HZ));
}
-#endif /* defined(_BLACKFIN_DELAY_H) */
+#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index d1d2e6be3b5..1601d62f39a 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count);
extern void insb(unsigned long port, void *addr, unsigned long count);
extern void insw(unsigned long port, void *addr, unsigned long count);
extern void insl(unsigned long port, void *addr, unsigned long count);
+extern void insl_16(unsigned long port, void *addr, unsigned long count);
extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
index 304f5bcfebe..4e2b3f2020e 100644
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -176,11 +176,7 @@
#define GPIO_IRQ_BASE IRQ_PF0
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PH15+1)
-#else
-#define NR_IRQS (SYS_IRQS+1)
-#endif
#define IVG7 7
#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index c5aa20102b2..193082deaa4 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x8000
/* Level 1 Memory */
@@ -90,9 +91,7 @@
/* Scratch Pad Memory */
-#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
-#endif
#endif /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 452fb825d89..832e6f6122d 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -130,11 +130,7 @@ Core Emulation **
#define GPIO_IRQ_BASE IRQ_PF0
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PF15+1)
-#else
-#define NR_IRQS SYS_IRQS
-#endif
#define IVG7 7
#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 94d8c4062eb..bd30b6f3be0 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
-
/*
* File: include/asm-blackfin/mach-bf533/mem_map.h
* Based on:
@@ -48,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x400
/* Level 1 Memory */
@@ -160,9 +160,7 @@
/* Scratch Pad Memory */
-#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
-#endif
#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 36c44bc1a91..be6f2ff77f3 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -162,11 +162,7 @@ Core Emulation **
#define GPIO_IRQ_BASE IRQ_PF0
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PH15+1)
-#else
-#define NR_IRQS (IRQ_UART1_ERROR+1)
-#endif
#define IVG7 7
#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 18759e38eaa..5c6726d6f3b 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x800
/* Level 1 Memory */
@@ -167,9 +168,7 @@
/* Scratch Pad Memory */
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
-#endif
#endif /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 7e6d349beb0..e748588e893 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,24 +106,22 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-#ifdef CONFIG_BF542
-#define CPU "BF542"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF544
-#define CPU "BF544"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF548
-#define CPU "BF548"
-#define CPUID 0x027c6000
-#endif
-#ifdef CONFIG_BF549
-#define CPU "BF549"
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
+#if defined(CONFIG_BF542)
+# define CPU "BF542"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF544)
+# define CPU "BF544"
+# define CPUID 0x027c8000
+#elif defined(CONFIG_BF547)
+# define CPU "BF547"
+#elif defined(CONFIG_BF548)
+# define CPU "BF548"
+# define CPUID 0x027c6000
+#elif defined(CONFIG_BF549)
+# define CPU "BF549"
+#else
+# define CPU "UNKNOWN"
+# define CPUID 0x0
#endif
#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 760307e34b9..b8b9870e269 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -645,7 +645,7 @@
/* Bit masks for HOST_STATUS */
-#define READY 0x1 /* DMA Ready */
+#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define COMPLETE 0x8 /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 70af33c963b..ecbca952985 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1007,7 +1007,7 @@
/* Bit masks for HOST_STATUS */
-#define READY 0x1 /* DMA Ready */
+#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define COMPLETE 0x8 /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 3b08cf9bd6f..9fb7bc5399a 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -338,11 +338,7 @@ Events (highest priority) EMU 0
#define GPIO_IRQ_BASE IRQ_PA0
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PJ15+1)
-#else
-#define NR_IRQS (SYS_IRQS+1)
-#endif
/* For compatibility reasons with existing code */
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index ec1597e3183..f99f47bc3a0 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,12 @@
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x1000
+
+/* L1 Instruction ROM */
+
+#define L1_ROM_START 0xFFA14000
+#define L1_ROM_LENGTH 0x10000
/* Level 1 Memory */
@@ -87,11 +93,19 @@
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
+/* Level 2 Memory */
+#if !defined(CONFIG_BF542)
+# define L2_START 0xFEB00000
+# if defined(CONFIG_BF544)
+# define L2_LENGTH 0x10000
+# else
+# define L2_LENGTH 0x20000
+# endif
+#endif
+
/* Scratch Pad Memory */
-#if defined(CONFIG_BF54x)
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
-#endif
#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef0..3ef9e5f3613 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
#define SUPPORTED_REVID 0x3
#define OFFSET_(x) ((x) & 0x0000FFFF)
-#define L1_ISRAM 0xFFA00000
-#define L1_ISRAM_END 0xFFA04000
-#define DATA_BANKA_SRAM 0xFF800000
-#define DATA_BANKA_SRAM_END 0xFF804000
-#define DATA_BANKB_SRAM 0xFF900000
-#define DATA_BANKB_SRAM_END 0xFF904000
-#define L1_DSRAMA 0xFF800000
-#define L1_DSRAMA_END 0xFF804000
-#define L1_DSRAMB 0xFF900000
-#define L1_DSRAMB_END 0xFF904000
-#define L2_SRAM 0xFEB00000
-#define L2_SRAM_END 0xFEB20000
-#define AMB_FLASH 0x20000000
-#define AMB_FLASH_END 0x21000000
-#define AMB_FLASH_LENGTH 0x01000000
-#define L1_ISRAM_LENGTH 0x4000
-#define L1_DSRAMA_LENGTH 0x4000
-#define L1_DSRAMB_LENGTH 0x4000
-#define L2_SRAM_LENGTH 0x20000
/*some misc defines*/
#define IMASK_IVG15 0x8000
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 7945e8a3a84..c3c0eb13c81 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,7 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
+#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
#define RESET_SOFTWARE (SWRST_OCCURRED)
@@ -877,12 +878,14 @@
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* SWRST Mask */
-#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */
-#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x00008000 /* SWRST Status */
+#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
+#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
+#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
+#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
+#define SWRST_OCCURRED 0x8000 /* SWRST Status */
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 12789927db3..83f0383957d 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -291,11 +291,7 @@
#define GPIO_IRQ_BASE IRQ_PF0
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
#define NR_IRQS (IRQ_PF47 + 1)
-#else
-#define NR_IRQS SYS_IRQS
-#endif
#define IVG7 7
#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index f7ac09cf2c3..c26d8486cc4 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START 0xEF000000
+#define BOOT_ROM_LENGTH 0x800
+
/* Level 1 Memory */
#ifdef CONFIG_BFIN_ICACHE
@@ -67,9 +72,7 @@
/* Scratch Pad Memory */
-#if defined(CONFIG_BF561)
#define L1_SCRATCH_START 0xFFB00000
#define L1_SCRATCH_LENGTH 0x1000
-#endif
#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index c1d8c4a78fc..e8967f6124f 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -46,7 +46,7 @@
#endif
#define bfin_read8(addr) ({ \
- uint8_t __v; \
+ uint32_t __v; \
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
"%0 = b[%1] (z);" \
@@ -56,7 +56,7 @@
__v; })
#define bfin_read16(addr) ({ \
- uint16_t __v; \
+ uint32_t __v; \
__asm__ __volatile__( \
NOP_PAD_ANOMALY_05000198 \
"%0 = w[%1] (z);" \
@@ -80,7 +80,7 @@
NOP_PAD_ANOMALY_05000198 \
"b[%0] = %1;" \
: \
- : "a" (addr), "d" (val) \
+ : "a" (addr), "d" ((uint8_t)(val)) \
: "memory" \
)
@@ -89,7 +89,7 @@
NOP_PAD_ANOMALY_05000198 \
"w[%0] = %1;" \
: \
- : "a" (addr), "d" (val) \
+ : "a" (addr), "d" ((uint16_t)(val)) \
: "memory" \
)
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 3b671d5fd70..cbaff24b4b2 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,6 +1,6 @@
/* This handles the memory map.. */
-#ifdef CONFIG_BFIN
+#ifdef CONFIG_BLACKFIN
#define PAGE_OFFSET_RAW 0x00000000
#endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index e8ada91ab00..321f4d96e4a 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,6 +1,8 @@
#ifndef _BLACKFIN_STRING_H_
#define _BLACKFIN_STRING_H_
+#include <linux/types.h>
+
#ifdef __KERNEL__ /* only set these up for kernel code */
#define __HAVE_ARCH_STRCPY
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca..ee1cbf73a9a 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -48,28 +48,80 @@
#ifndef __ASSEMBLY__
-#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3 "External Memory Addressing Error\n"
-#define HWC_x12 "Performance Monitor Overflow\n"
-#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default "Reserved\n"
-
-#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
-#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
-#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
-#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
-#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
+#define HWC_x2(level) \
+ "System MMR Error\n" \
+ level " - An error occurred due to an invalid access to an System MMR location\n" \
+ level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
+ level " or a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3(level) \
+ "External Memory Addressing Error\n"
+#define HWC_x12(level) \
+ "Performance Monitor Overflow\n"
+#define HWC_x18(level) \
+ "RAISE 5 instruction\n" \
+ level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
+#define HWC_default(level) \
+ "Reserved\n"
+#define EXC_0x03(level) \
+ "Application stack overflow\n" \
+ level " - Please increase the stack size of the application using elf2flt -s option,\n" \
+ level " and/or reduce the stack use of the application.\n"
+#define EXC_0x10(level) \
+ "Single step\n" \
+ level " - When the processor is in single step mode, every instruction\n" \
+ level " generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11(level) \
+ "Exception caused by a trace buffer full condition\n" \
+ level " - The processor takes this exception when the trace\n" \
+ level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
+#define EXC_0x21(level) \
+ "Undefined instruction\n" \
+ level " - May be used to emulate instructions that are not defined for\n" \
+ level " a particular processor implementation.\n"
+#define EXC_0x22(level) \
+ "Illegal instruction combination\n" \
+ level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
+ level " Processor Instruction Set Reference.\n"
+#define EXC_0x23(level) \
+ "Data access CPLB protection violation\n" \
+ level " - Attempted read or write to Supervisor resource,\n" \
+ level " or illegal data memory access. \n"
+#define EXC_0x24(level) \
+ "Data access misaligned address violation\n" \
+ level " - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25(level) \
+ "Unrecoverable event\n" \
+ level " - For example, an exception generated while processing a previous exception.\n"
+#define EXC_0x26(level) \
+ "Data access CPLB miss\n" \
+ level " - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27(level) \
+ "Data access multiple CPLB hits\n" \
+ level " - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28(level) \
+ "Program Sequencer Exception caused by an emulation watchpoint match\n" \
+ level " - There is a watchpoint match, and one of the EMUSW\n" \
+ level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+#define EXC_0x2A(level) \
+ "Instruction fetch misaligned address violation\n" \
+ level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
+ level " exception, the return address provided in RETX is the destination address which is\n" \
+ level " misaligned, rather than the address of the offending instruction.\n"
+#define EXC_0x2B(level) \
+ "CPLB protection violation\n" \
+ level " - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x2C(level) \
+ "Instruction fetch CPLB miss\n" \
+ level " - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D(level) \
+ "Instruction fetch multiple CPLB hits\n" \
+ level " - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E(level) \
+ "Illegal use of supervisor resource\n" \
+ level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
+ level " Supervisor resources are registers and instructions that are reserved\n" \
+ level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
+ level " only instructions.\n"
#endif /* __ASSEMBLY__ */
#endif /* _BFIN_TRAPS_H */
diff --git a/include/asm-generic/resource.h b/include/asm-generic/resource.h
index cfe3692b23e..a4a22cc3589 100644
--- a/include/asm-generic/resource.h
+++ b/include/asm-generic/resource.h
@@ -12,7 +12,7 @@
* then it defines them prior including asm-generic/resource.h. )
*/
-#define RLIMIT_CPU 0 /* CPU time in ms */
+#define RLIMIT_CPU 0 /* CPU time in sec */
#define RLIMIT_FSIZE 1 /* Maximum filesize */
#define RLIMIT_DATA 2 /* max data size */
#define RLIMIT_STACK 3 /* max stack size */
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index 49730ffbbae..81bcd5e5178 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -94,6 +94,7 @@ ia64_acpi_release_global_lock (unsigned int *lock)
#define acpi_noirq 0 /* ACPI always enabled on IA64 */
#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */
+#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
static inline void disable_acpi(void) { }
const char *acpi_get_sysname (void);
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f78488cc..00000000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE 1193182UL
-
-#endif
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d31ef..d6a6c21f16d 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -92,6 +92,7 @@
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d4f41..17f082cfea8 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
- " j 2b \n" \
+ " j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
@@ -61,7 +61,7 @@
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
- " j 2b \n" \
+ " j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
@@ -200,4 +200,4 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
}
#endif
-#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index 032ca73f181..5dabc870b32 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -12,6 +12,8 @@
#define PIT_CH0 0x40
#define PIT_CH2 0x42
+#define PIT_TICK_RATE 1193182UL
+
extern spinlock_t i8253_lock;
extern void setup_pit_timer(void);
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index ab5612f90f6..85bc5302bce 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,7 +22,7 @@ enum ip32_irq_no {
* CPU interrupts are 0 ... 7
*/
- CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE,
+ CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
/*
* MACE
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b403f53..1030562d6ea 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@ do { \
if (cpu_has_dsp) \
__save_dsp(prev); \
(last) = resume(prev, next, task_thread_info(next)); \
+} while (0)
+
+#define finish_arch_switch(prev) \
+do { \
if (cpu_has_dsp) \
__restore_dsp(current); \
if (cpu_has_userlocal) \
- write_c0_userlocal(task_thread_info(current)->tp_value);\
-} while(0)
+ write_c0_userlocal(current_thread_info()->tp_value); \
+} while (0)
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index ee1663e64da..7717934f94c 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,10 +58,22 @@ extern int (*perf_irq)(void);
* Initialize the calling CPU's compare interrupt as clockevent device
*/
#ifdef CONFIG_CEVT_R4K
-extern void mips_clockevent_init(void);
+extern int mips_clockevent_init(void);
extern unsigned int __weak get_c0_compare_int(void);
#else
-static inline void mips_clockevent_init(void)
+static inline int mips_clockevent_init(void)
+{
+ return -ENXIO;
+}
+#endif
+
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern void init_mips_clocksource(void);
+#else
+static inline void init_mips_clocksource(void)
{
}
#endif
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 374d0db37e1..17110aff26e 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -6,6 +6,10 @@
#define PPC_MEMSTART 0
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+#endif
+
#ifndef __ASSEMBLY__
/*
* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index dc318458b5f..d8bdc79db12 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -246,7 +246,6 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
return PCI_DN(busdn)->phb;
}
-extern void pcibios_free_controller(struct pci_controller *phb);
extern void isa_bridge_find_early(struct pci_controller *hose);
@@ -282,9 +281,11 @@ extern void
pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary);
-/* Allocate a new PCI host bridge structure */
+/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *
pcibios_alloc_controller(struct device_node *dev);
+extern void pcibios_free_controller(struct pci_controller *phb);
+
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
extern int pcibios_vaddr_is_ioport(void __iomem *address);
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index 8eaa7b28d9d..87db8728e82 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -164,7 +164,8 @@ extern int rtas_call(int token, int, int, int *, ...);
extern void rtas_restart(char *cmd);
extern void rtas_power_off(void);
extern void rtas_halt(void);
-extern void rtas_os_term(char *str);
+extern void rtas_panic_msg(char *str);
+extern void rtas_os_term(void);
extern int rtas_get_sensor(int sensor, int index, int *state);
extern int rtas_get_power_level(int powerdomain, int *level);
extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
diff --git a/include/asm-powerpc/vdso_datapage.h b/include/asm-powerpc/vdso_datapage.h
index 8a94f0eba5e..f01393224b5 100644
--- a/include/asm-powerpc/vdso_datapage.h
+++ b/include/asm-powerpc/vdso_datapage.h
@@ -77,6 +77,10 @@ struct vdso_data {
/* those additional ones don't have to be located anywhere
* special as they were not part of the original systemcfg
*/
+ __u32 dcache_block_size; /* L1 d-cache block size */
+ __u32 icache_block_size; /* L1 i-cache block size */
+ __u32 dcache_log_block_size; /* L1 d-cache log block size */
+ __u32 icache_log_block_size; /* L1 i-cache log block size */
__s32 wtom_clock_sec; /* Wall to monotonic clock */
__s32 wtom_clock_nsec;
__u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
@@ -99,6 +103,10 @@ struct vdso_data {
__s32 wtom_clock_sec; /* Wall to monotonic clock */
__s32 wtom_clock_nsec;
__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
+ __u32 dcache_block_size; /* L1 d-cache block size */
+ __u32 icache_block_size; /* L1 i-cache block size */
+ __u32 dcache_log_block_size; /* L1 d-cache log block size */
+ __u32 icache_log_block_size; /* L1 i-cache log block size */
};
#endif /* CONFIG_PPC64 */
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index d866d338555..44bda786eef 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -388,6 +388,11 @@ extern void (*_machine_power_off)(void);
#define arch_align_stack(x) (x)
+#ifdef CONFIG_TRACE_IRQFLAGS
+extern psw_t sysc_restore_trace_psw;
+extern psw_t io_restore_trace_psw;
+#endif
+
#endif /* __KERNEL__ */
#endif
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
index b91246153b7..9d528ada3c1 100644
--- a/include/asm-sh/cacheflush.h
+++ b/include/asm-sh/cacheflush.h
@@ -43,7 +43,7 @@ extern void __flush_purge_region(void *start, int size);
extern void __flush_invalidate_region(void *start, int size);
#endif
-#ifdef CONFIG_CPU_SH4
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
extern void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 0693689d414..f8a89793ac8 100644
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -1,5 +1,32 @@
+#ifndef _ASM_X86_ACPI_H
+#define _ASM_X86_ACPI_H
+
#ifdef CONFIG_X86_32
# include "acpi_32.h"
#else
# include "acpi_64.h"
#endif
+
+#include <asm/processor.h>
+
+/*
+ * Check if the CPU can handle C2 and deeper
+ */
+static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
+{
+ /*
+ * Early models (<=5) of AMD Opterons are not supposed to go into
+ * C2 state.
+ *
+ * Steppings 0x0A and later are good
+ */
+ if (boot_cpu_data.x86 == 0x0F &&
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+ boot_cpu_data.x86_model <= 0x05 &&
+ boot_cpu_data.x86_mask < 0x0A)
+ return 1;
+ else
+ return max_cstate;
+}
+
+#endif
diff --git a/include/asm-x86/apic_32.h b/include/asm-x86/apic_32.h
index 4091b33dcb1..be158b27d54 100644
--- a/include/asm-x86/apic_32.h
+++ b/include/asm-x86/apic_32.h
@@ -120,6 +120,7 @@ extern int local_apic_timer_disabled;
#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
+#define local_apic_timer_c2_ok 1
#endif /* !CONFIG_X86_LOCAL_APIC */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 8ccedf7a0a5..e3c16c981e4 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -132,6 +132,11 @@ extern unsigned long acpi_realmode_flags;
int acpi_register_gsi (u32 gsi, int triggering, int polarity);
int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
+#ifdef CONFIG_X86_IO_APIC
+extern int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity);
+#else
+#define acpi_get_override_irq(bus, trigger, polarity) (-1)
+#endif
/*
* This function undoes the effect of one call to acpi_register_gsi().
* If this matches the last registration, any IRQ resources for gsi
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 16a51546db4..c4e00161a24 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -92,6 +92,7 @@ struct cpuidle_device {
struct kobject kobj;
struct completion kobj_unregister;
void *governor_data;
+ struct cpuidle_state *safe_state;
};
DECLARE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 56a5673aeba..ef52a07c43d 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -340,6 +340,7 @@ enum {
ATA_HORKAGE_HPA_SIZE = (1 << 6), /* native size off by one */
ATA_HORKAGE_IPM = (1 << 7), /* Link PM problems */
ATA_HORKAGE_IVB = (1 << 8), /* cbl det validity bit bugs */
+ ATA_HORKAGE_STUCK_ERR = (1 << 9), /* stuck ERR on next PACKET */
/* DMA mask for user DMA control: User visible values; DO NOT
renumber */
@@ -771,8 +772,6 @@ static inline int ata_port_is_dummy(struct ata_port *ap)
extern void sata_print_link_status(struct ata_link *link);
extern void ata_port_probe(struct ata_port *);
-extern void __sata_phy_reset(struct ata_port *ap);
-extern void sata_phy_reset(struct ata_port *ap);
extern void ata_bus_reset(struct ata_port *ap);
extern int sata_set_spd(struct ata_link *link);
extern int sata_link_debounce(struct ata_link *link,
@@ -994,8 +993,6 @@ extern void sata_pmp_do_eh(struct ata_port *ap,
/*
* EH
*/
-extern void ata_eng_timeout(struct ata_port *ap);
-
extern void ata_port_schedule_eh(struct ata_port *ap);
extern int ata_link_abort(struct ata_link *link);
extern int ata_port_abort(struct ata_port *ap);
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index e82a6ebc725..2d15d4aac09 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -422,7 +422,6 @@ extern long nfs_sync_mapping_wait(struct address_space *, struct writeback_contr
extern int nfs_wb_all(struct inode *inode);
extern int nfs_wb_nocommit(struct inode *inode);
extern int nfs_wb_page(struct inode *inode, struct page* page);
-extern int nfs_wb_page_priority(struct inode *inode, struct page* page, int how);
extern int nfs_wb_page_cancel(struct inode *inode, struct page* page);
#if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4)
extern int nfs_commit_inode(struct inode *, int);
diff --git a/include/linux/sunrpc/debug.h b/include/linux/sunrpc/debug.h
index 3347c72b848..3912cf16361 100644
--- a/include/linux/sunrpc/debug.h
+++ b/include/linux/sunrpc/debug.h
@@ -88,11 +88,6 @@ enum {
CTL_SLOTTABLE_TCP,
CTL_MIN_RESVPORT,
CTL_MAX_RESVPORT,
- CTL_SLOTTABLE_RDMA,
- CTL_RDMA_MAXINLINEREAD,
- CTL_RDMA_MAXINLINEWRITE,
- CTL_RDMA_WRITEPADDING,
- CTL_RDMA_MEMREG,
};
#endif /* _LINUX_SUNRPC_DEBUG_H_ */
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index e99171f01b4..4f5047df8a9 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -70,7 +70,6 @@ enum
CTL_ABI=9, /* Binary emulation */
CTL_CPU=10, /* CPU stuff (speed scaling, etc) */
CTL_ARLAN=254, /* arlan wireless driver */
- CTL_APPLDATA=2120, /* s390 appldata */
CTL_S390DBF=5677, /* s390 debug */
CTL_SUNRPC=7249, /* sunrpc debug */
CTL_PM=9899, /* frv power management */
@@ -207,11 +206,6 @@ enum
VM_PANIC_ON_OOM=33, /* panic at out-of-memory */
VM_VDSO_ENABLED=34, /* map VDSO into new processes? */
VM_MIN_SLAB=35, /* Percent pages ignored by zone reclaim */
-
- /* s390 vm cmm sysctls */
- VM_CMM_PAGES=1111,
- VM_CMM_TIMED_PAGES=1112,
- VM_CMM_TIMEOUT=1113,
};
diff --git a/include/linux/timex.h b/include/linux/timex.h
index 37ac3ff90fa..24c6a2b5951 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -137,6 +137,7 @@ struct timex {
#define ADJ_TIMECONST 0x0020 /* pll time constant */
#define ADJ_TICK 0x4000 /* tick value */
#define ADJ_OFFSET_SINGLESHOT 0x8001 /* old-fashioned adjtime */
+#define ADJ_OFFSET_SS_READ 0xa001 /* read-only adjtime */
/* xntp 3.4 compatibility names */
#define MOD_OFFSET ADJ_OFFSET
diff --git a/include/sound/version.h b/include/sound/version.h
index a2be8ad8894..a9781eb0da0 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
/* include/version.h. Generated by alsa/ksync script. */
#define CONFIG_SND_VERSION "1.0.15"
-#define CONFIG_SND_DATE " (Tue Oct 23 06:09:18 2007 UTC)"
+#define CONFIG_SND_DATE " (Tue Nov 20 19:16:42 2007 UTC)"