diff options
Diffstat (limited to 'include')
67 files changed, 6905 insertions, 226 deletions
diff --git a/include/Kbuild b/include/Kbuild index 8d226bfa269..506f6d7dba7 100644 --- a/include/Kbuild +++ b/include/Kbuild @@ -10,3 +10,4 @@ header-y += video/ header-y += drm/ header-y += xen/ header-y += scsi/ +header-y += trace/ diff --git a/include/linux/Kbuild b/include/linux/Kbuild index c94e71781b7..02324b894e1 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -151,6 +151,7 @@ header-y += hid.h header-y += hiddev.h header-y += hidraw.h header-y += hpet.h +header-y += hwmem.h header-y += hysdn_if.h header-y += i2c-dev.h header-y += i2c.h diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h index 0101e9c17fa..32a89cf5ec4 100644 --- a/include/linux/amba/mmci.h +++ b/include/linux/amba/mmci.h @@ -6,6 +6,19 @@ #include <linux/mmc/host.h> + +/* + * These defines is places here due to access is needed from machine + * configuration files. The ST Micro version does not have ROD and + * reuse the voltage registers for direction settings. + */ +#define MCI_ST_DATA2DIREN (1 << 2) +#define MCI_ST_CMDDIREN (1 << 3) +#define MCI_ST_DATA0DIREN (1 << 4) +#define MCI_ST_DATA31DIREN (1 << 5) +#define MCI_ST_FBCLKEN (1 << 7) +#define MCI_ST_DATA74DIREN (1 << 8) + /* Just some dummy forwarding */ struct dma_chan; @@ -18,7 +31,8 @@ struct dma_chan; * @ocr_mask: available voltages on the 4 pins from the block, this * is ignored if a regulator is used, see the MMC_VDD_* masks in * mmc/host.h - * @vdd_handler: a callback function to translate a MMC_VDD_* + * @ios_handler: a callback function to act on specfic ios changes, + * used for example to control a levelshifter * mask into a value to be binary (or set some other custom bits * in MMCIPWR) or:ed and written into the MMCIPWR register of the * block. May also control external power based on the power_mode. @@ -31,6 +45,8 @@ struct dma_chan; * @capabilities: the capabilities of the block as implemented in * this platform, signify anything MMC_CAP_* from mmc/host.h * @capabilities2: more capabilities, MMC_CAP2_* from mmc/host.h + * @sigdir: a bit field indicating for what bits in the MMC bus the host + * should enable signal direction indication. * @dma_filter: function used to select an appropriate RX and TX * DMA channel to be used for DMA, if and only if you're deploying the * generic DMA engine @@ -46,14 +62,14 @@ struct dma_chan; struct mmci_platform_data { unsigned int f_max; unsigned int ocr_mask; - u32 (*vdd_handler)(struct device *, unsigned int vdd, - unsigned char power_mode); + int (*ios_handler)(struct device *, struct mmc_ios *); unsigned int (*status)(struct device *); int gpio_wp; int gpio_cd; bool cd_invert; unsigned long capabilities; unsigned long capabilities2; + u32 sigdir; bool (*dma_filter)(struct dma_chan *chan, void *filter_param); void *dma_rx_param; void *dma_tx_param; diff --git a/include/linux/boottime.h b/include/linux/boottime.h new file mode 100644 index 00000000000..9836c5b3175 --- /dev/null +++ b/include/linux/boottime.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) ST-Ericsson SA 2009-2010 + * + * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson + * + * License terms: GNU General Public License (GPL) version 2 + * + * boottime is a tool for collecting start-up timing + * information and can together with boot loader support + * display a total system start-up time. + * + */ + +#ifndef LINUX_BOOTTIME_H +#define LINUX_BOOTTIME_H + +#ifdef CONFIG_BOOTTIME +#include <linux/kernel.h> + +/** + * struct boottime_timer - Callbacks for generic timer. + * @init: Function to call at boottime initialization + * @get_time: Returns the number of us since start-up + * Preferable this is based upon a free running timer. + * This is the only required entry. + * @finalize: Called before init is executed and boottime is done. + */ +struct boottime_timer { + int (*init)(void); + unsigned long (*get_time)(void); + void (*finalize)(void); +}; + +/** + * boottime_mark_wtime() + * Add a sample point with a given time. Useful for adding data collected + * by for example a boot loader. + * @name: The name of the sample point + * @time: The time in us when this point was reached + */ +void __init boottime_mark_wtime(char *name, unsigned long time); + +/** + * boottime_mark() + * Add a sample point with the current time. + * @name: The name of this sample point + */ +void __init boottime_mark(char *name); + +/** + * boottime_mark_symbolic() + * Add a sample point where the name is a symbolic function + * and %pF is needed to get the correct function name. + * @name: function name. + */ +void __init boottime_mark_symbolic(void *name); + +/** + * boottime_activate() + * Activates boottime and register callbacks. + * @bt: struct with callbacks. + */ +void __ref boottime_activate(struct boottime_timer *bt); + +/** + * boottime_deactivate() + * This function is called when the kernel boot is done. + * (before "free init memory" is called) + */ +void __init boottime_deactivate(void); + +/** + * boottime_system_up() + * A function is called when the basics of the kernel + * is up and running. + */ +void __init boottime_system_up(void); + +#else + +#define boottime_mark_wtime(name, time) +#define boottime_mark(name) +#define boottime_mark_symbolic(name) +#define boottime_activate(bt) +#define boottime_deactivate() +#define boottime_system_up() +#endif + +#endif /* LINUX_BOOTTIME_H */ diff --git a/include/linux/clksrc-db5500-mtimer.h b/include/linux/clksrc-db5500-mtimer.h new file mode 100644 index 00000000000..3112c7f2709 --- /dev/null +++ b/include/linux/clksrc-db5500-mtimer.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + */ +#ifndef __CLKSRC_DB5500_MTIMER_H +#define __CLKSRC_DB5500_MTIMER_H + +#include <linux/io.h> + +#ifdef CONFIG_CLKSRC_DB5500_MTIMER +void db5500_mtimer_init(void __iomem *base); +#else +static inline void db5500_mtimer_init(void __iomem *base) {} +#endif + +#endif diff --git a/include/linux/compdev.h b/include/linux/compdev.h new file mode 100644 index 00000000000..9e707c7b770 --- /dev/null +++ b/include/linux/compdev.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * ST-Ericsson Display overlay compositer device driver + * + * Author: Anders Bauer <anders.bauer@stericsson.com> + * for ST-Ericsson. + * + * Modified: Per-Daniel Olsson <per-daniel.olsson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef _COMPDEV_H_ +#define _COMPDEV_H_ + +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#else +#include <linux/types.h> +#include <video/mcde.h> +#endif + +#if defined(__KERNEL__) || defined(_KERNEL) +#include <linux/mm_types.h> +#include <linux/bitops.h> +#else +#define BIT(nr) (1UL << (nr)) +#endif + +#define COMPDEV_DEFAULT_DEVICE_PREFIX "comp" +#define NUM_COMPDEV_BUFS 2 + +enum compdev_fmt { + COMPDEV_FMT_RGB565, + COMPDEV_FMT_RGB888, + COMPDEV_FMT_RGBX8888, + COMPDEV_FMT_RGBA8888, + COMPDEV_FMT_YUV422, +}; + +struct compdev_size { + uint16_t width; + uint16_t height; +}; + +/* Display rotation */ +enum compdev_rotation { + COMPDEV_ROT_0 = 0, + COMPDEV_ROT_90_CCW = 90, + COMPDEV_ROT_180_CCW = 180, + COMPDEV_ROT_270_CCW = 270, + COMPDEV_ROT_90_CW = COMPDEV_ROT_270_CCW, + COMPDEV_ROT_180_CW = COMPDEV_ROT_180_CCW, + COMPDEV_ROT_270_CW = COMPDEV_ROT_90_CCW, +}; + +enum compdev_ptr_type { + COMPDEV_PTR_PHYSICAL, + COMPDEV_PTR_HWMEM_BUF_NAME_OFFSET, +}; + +struct compdev_rect { + __s32 x; + __s32 y; + __s32 width; + __s32 height; +}; + +struct compdev_buf { + enum compdev_ptr_type type; + __s32 hwmem_buf_name; + __s32 fd; + __u32 offset; + __u32 len; +}; + +struct compdev_img { + enum compdev_fmt fmt; + struct compdev_buf buf; + __s32 width; + __s32 height; + __u32 pitch; + struct compdev_rect dst_rect; +}; + +struct compdev_post_buffers_req { + enum compdev_rotation rotation; + struct compdev_img img_buffers[NUM_COMPDEV_BUFS]; + __u8 buffer_count; +}; + +#define COMPDEV_GET_SIZE_IOC _IOR('D', 1, struct compdev_size) +#define COMPDEV_POST_BUFFERS_IOC _IOW('D', 2, struct compdev_post_buffers_req) + +#ifdef __KERNEL__ + +int compdev_create(struct mcde_display_device *ddev, + struct mcde_overlay *parent_ovly); +void compdev_destroy(struct mcde_display_device *ddev); + +#endif /* __KERNEL__ */ + +#endif /* _COMPDEV_H_ */ + diff --git a/include/linux/cpufreq-dbx500.h b/include/linux/cpufreq-dbx500.h new file mode 100644 index 00000000000..15c59c3b1c8 --- /dev/null +++ b/include/linux/cpufreq-dbx500.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + */ +#ifndef __CPUFREQ_DBX500_H +#define __CPUFREQ_DBX500_H + +#include <linux/cpufreq.h> + +int dbx500_cpufreq_get_limits(int cpu, int r, + unsigned int *min, unsigned int *max); + +int dbx500_cpufreq_percent2freq(int percent); + +#endif diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 6216115c778..1f8e97c2a08 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -199,6 +199,7 @@ extern int __cpufreq_driver_getavg(struct cpufreq_policy *policy, int cpufreq_register_governor(struct cpufreq_governor *governor); void cpufreq_unregister_governor(struct cpufreq_governor *governor); +int cpufreq_update_freq(int cpu, unsigned int min, unsigned int max); /********************************************************************* * CPUFREQ DRIVER INTERFACE * @@ -336,6 +337,7 @@ static inline unsigned int cpufreq_quick_get_max(unsigned int cpu) } #endif +int cpufreq_update_freq(int cpu, unsigned int min, unsigned int max); /********************************************************************* * CPUFREQ DEFAULT GOVERNOR * diff --git a/include/linux/cyttsp.h b/include/linux/cyttsp.h new file mode 100755 index 00000000000..38ef1236d7a --- /dev/null +++ b/include/linux/cyttsp.h @@ -0,0 +1,114 @@ +/* Header file for: + * Cypress TrueTouch(TM) Standard Product I2C touchscreen driver. + * include/linux/cyttsp.h + * + * Copyright (C) 2009-2011 Cypress Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, and only version 2, as published by the + * Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * Cypress reserves the right to make changes without further notice + * to the materials described herein. Cypress does not assume any + * liability arising out of the application described herein. + * + * Contact Cypress Semiconductor at www.cypress.com + * + */ +#include <linux/input.h> + +#ifndef _CYTTSP_H_ +#define _CYTTSP_H_ + +#include <linux/input.h> + +#define CY_SPI_NAME "cyttsp-spi" +#define CY_I2C_NAME "cyttsp-i2c" +/* Scan Type selection for finger and/or stylus activation */ +#define CY_SCN_TYP_DFLT 0x01 /* finger only mutual scan */ +/* Active Power state scanning/processing refresh interval */ +#define CY_ACT_INTRVL_DFLT 0x00 /* ms */ +/* touch timeout for the Active power */ +#define CY_TCH_TMOUT_DFLT 0x64 /* ms */ +/* Low Power state scanning/processing refresh interval */ +#define CY_LP_INTRVL_DFLT 0x32 /* ms */ +/* + *defines for Gen2 (Txx2xx); Gen3 (Txx3xx) + * use these defines to set cyttsp_platform_data.gen in board config file + */ +enum cyttsp_gen { + CY_GEN2, + CY_GEN3, +}; +/* + * Active distance in pixels for a gesture to be reported + * if set to 0, then all gesture movements are reported + * Valid range is 0 - 15 + */ +#define CY_ACT_DIST_DFLT 8 +#define CY_ACT_DIST CY_ACT_DIST_DFLT +#define CY_ACT_DIST_BITS 0x0F +/* max retries for read/write ops */ +#define CY_NUM_RETRY 6 + +enum cyttsp_gest { + CY_GEST_GRP_NONE = 0, + CY_GEST_GRP1 = 0x10, + CY_GEST_GRP2 = 0x20, + CY_GEST_GRP3 = 0x40, + CY_GEST_GRP4 = 0x80, +}; + +enum cyttsp_powerstate { + CY_IDLE_STATE, /* IC cannot be reached */ + CY_READY_STATE, /* pre-operational; ready to go to ACTIVE */ + CY_ACTIVE_STATE, /* app is running, IC is scanning */ + CY_LOW_PWR_STATE, /* not currently used */ + CY_SLEEP_STATE, /* app is running, IC is idle */ + CY_BL_STATE, /* bootloader is running */ + CY_LDR_STATE, /* loader is running */ + CY_SYSINFO_STATE, /* Switching to SysInfo mode */ + CY_INVALID_STATE /* always last in the list */ +}; + +struct cyttsp_platform_data { + u32 maxx; + u32 maxy; + u32 flags; + enum cyttsp_gen gen; + unsigned use_st:1; + unsigned use_mt:1; + unsigned use_trk_id:1; + unsigned use_hndshk:1; + unsigned use_timer:1; + unsigned use_sleep:1; + unsigned use_gestures:1; + unsigned use_load_file:1; + unsigned use_force_fw_update:1; + unsigned use_virtual_keys:1; + enum cyttsp_powerstate power_state; + u8 gest_set; + u8 scn_typ; /* finger and/or stylus scanning */ + u8 act_intrvl; /* Active refresh interval; ms */ + u8 tch_tmout; /* Active touch timeout; ms */ + u8 lp_intrvl; /* Low power refresh interval; ms */ + int (*wakeup)(void); + int (*init)(int on_off); + void (*mt_sync)(struct input_dev *); + char *name; + s16 irq_gpio; + s16 rst_gpio; + bool invert; +}; + +#endif /* _CYTTSP_H_ */ diff --git a/include/linux/dispdev.h b/include/linux/dispdev.h new file mode 100644 index 00000000000..cbcf6705150 --- /dev/null +++ b/include/linux/dispdev.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * ST-Ericsson Display device driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef _DISPDEV_H_ +#define _DISPDEV_H_ + +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#else +#include <linux/types.h> +#include <video/mcde.h> +#endif + +#define DISPDEV_DEFAULT_DEVICE_PREFIX "disp" + +enum dispdev_fmt { + DISPDEV_FMT_RGB565, + DISPDEV_FMT_RGB888, + DISPDEV_FMT_RGBX8888, + DISPDEV_FMT_RGBA8888, + DISPDEV_FMT_YUV422, +}; + +struct dispdev_config { + uint16_t format; + uint16_t stride; + uint16_t x; + uint16_t y; + uint16_t z; + uint16_t width; + uint16_t height; + + uint32_t user_flags; +}; + +struct dispdev_buffer_info { + uint16_t buf_idx; + uint16_t display_update; + struct dispdev_config buf_cfg; +}; + +#define DISPDEV_SET_CONFIG_IOC _IOW('D', 1, struct dispdev_config) +#define DISPDEV_GET_CONFIG_IOC _IOR('D', 2, struct dispdev_config) +#define DISPDEV_REGISTER_BUFFER_IOC _IO('D', 3) +#define DISPDEV_UNREGISTER_BUFFER_IOC _IO('D', 4) +#define DISPDEV_QUEUE_BUFFER_IOC _IOW('D', 5, struct dispdev_buffer_info) +#define DISPDEV_DEQUEUE_BUFFER_IOC _IO('D', 6) + +#ifdef __KERNEL__ + +int dispdev_create(struct mcde_display_device *ddev, bool overlay, + struct mcde_overlay *parent_ovly); +void dispdev_destroy(struct mcde_display_device *ddev); + +#endif /* __KERNEL__ */ + +#endif /* _DISPDEV_H_ */ + diff --git a/include/linux/gpio/nomadik.h b/include/linux/gpio/nomadik.h new file mode 100644 index 00000000000..3e8b7f16fb7 --- /dev/null +++ b/include/linux/gpio/nomadik.h @@ -0,0 +1,89 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PLAT_NOMADIK_GPIO +#define __PLAT_NOMADIK_GPIO + +/* + * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving + * the "gpio" namespace for generic and cross-machine functions + */ + +/* Register in the logic block */ +#define NMK_GPIO_DAT 0x00 +#define NMK_GPIO_DATS 0x04 +#define NMK_GPIO_DATC 0x08 +#define NMK_GPIO_PDIS 0x0c +#define NMK_GPIO_DIR 0x10 +#define NMK_GPIO_DIRS 0x14 +#define NMK_GPIO_DIRC 0x18 +#define NMK_GPIO_SLPC 0x1c +#define NMK_GPIO_AFSLA 0x20 +#define NMK_GPIO_AFSLB 0x24 +#define NMK_GPIO_LOWEMI 0x28 + +#define NMK_GPIO_RIMSC 0x40 +#define NMK_GPIO_FIMSC 0x44 +#define NMK_GPIO_IS 0x48 +#define NMK_GPIO_IC 0x4c +#define NMK_GPIO_RWIMSC 0x50 +#define NMK_GPIO_FWIMSC 0x54 +#define NMK_GPIO_WKS 0x58 + +/* Alternate functions: function C is set in hw by setting both A and B */ +#define NMK_GPIO_ALT_GPIO 0 +#define NMK_GPIO_ALT_A 1 +#define NMK_GPIO_ALT_B 2 +#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B) + +/* Pull up/down values */ +enum nmk_gpio_pull { + NMK_GPIO_PULL_NONE, + NMK_GPIO_PULL_UP, + NMK_GPIO_PULL_DOWN, +}; + +/* Sleep mode */ +enum nmk_gpio_slpm { + NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_NOCHANGE, + NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, +}; + +extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); +extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull); +extern int nmk_gpio_set_mode(int gpio, int gpio_mode); +extern int nmk_gpio_get_mode(int gpio); + +extern void nmk_gpio_wakeups_suspend(void); +extern void nmk_gpio_wakeups_resume(void); + +extern void nmk_gpio_clocks_enable(void); +extern void nmk_gpio_clocks_disable(void); + +extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up); + +/* + * Platform data to register a block: only the initial gpio/irq number. + */ +struct nmk_gpio_platform_data { + char *name; + int first_gpio; + int first_irq; + int num_gpio; + u32 (*get_secondary_status)(unsigned int bank); + void (*set_ioforce)(bool enable); + bool supports_sleepmode; +}; + +#endif /* __PLAT_NOMADIK_GPIO */ diff --git a/include/linux/hwmem.h b/include/linux/hwmem.h new file mode 100644 index 00000000000..cb9e0dc9aaa --- /dev/null +++ b/include/linux/hwmem.h @@ -0,0 +1,597 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Hardware memory driver, hwmem + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef _HWMEM_H_ +#define _HWMEM_H_ + +#include <linux/types.h> + +#if !defined(__KERNEL__) +#include <sys/types.h> +#else +#include <linux/mm_types.h> +#endif + +#define HWMEM_DEFAULT_DEVICE_NAME "hwmem" + +/** + * @brief Flags defining behavior of allocation + */ +enum hwmem_alloc_flags { + /** + * @brief Buffered + */ + HWMEM_ALLOC_HINT_WRITE_COMBINE = (1 << 0), + /** + * @brief Non-buffered + */ + HWMEM_ALLOC_HINT_NO_WRITE_COMBINE = (1 << 1), + /** + * @brief Cached + */ + HWMEM_ALLOC_HINT_CACHED = (1 << 2), + /** + * @brief Uncached + */ + HWMEM_ALLOC_HINT_UNCACHED = (1 << 3), + /** + * @brief Write back + */ + HWMEM_ALLOC_HINT_CACHE_WB = (1 << 4), + /** + * @brief Write through + */ + HWMEM_ALLOC_HINT_CACHE_WT = (1 << 5), + /** + * @brief No alloc on write + */ + HWMEM_ALLOC_HINT_CACHE_NAOW = (1 << 6), + /** + * @brief Alloc on write + */ + HWMEM_ALLOC_HINT_CACHE_AOW = (1 << 7), + /** + * @brief Inner and outer cache + */ + HWMEM_ALLOC_HINT_INNER_AND_OUTER_CACHE = (1 << 8), + /** + * @brief Inner cache only + */ + HWMEM_ALLOC_HINT_INNER_CACHE_ONLY = (1 << 9), + /** + * @brief Reserved for use by the cache handler integration + */ + HWMEM_ALLOC_RESERVED_CHI = (1 << 31), +}; + +/** + * @brief Flags defining buffer access mode. + */ +enum hwmem_access { + /** + * @brief Buffer will be read from. + */ + HWMEM_ACCESS_READ = (1 << 0), + /** + * @brief Buffer will be written to. + */ + HWMEM_ACCESS_WRITE = (1 << 1), + /** + * @brief Buffer will be imported. + */ + HWMEM_ACCESS_IMPORT = (1 << 2), +}; + +/** + * @brief Values defining memory types. + */ +enum hwmem_mem_type { + /** + * @brief Scattered system memory. + */ + HWMEM_MEM_SCATTERED_SYS, + /** + * @brief Contiguous system memory. + */ + HWMEM_MEM_CONTIGUOUS_SYS, + /** + * @brief Protected system memory. + */ + HWMEM_MEM_PROTECTED_SYS, +}; + +/* User space API */ + +/** + * @see struct hwmem_region. + */ +struct hwmem_region_us { + __u32 offset; + __u32 count; + __u32 start; + __u32 end; + __u32 size; +}; + +/** + * @brief Alloc request data. + */ +struct hwmem_alloc_request { + /** + * @brief [in] Size of requested allocation in bytes. Size will be + * aligned to PAGE_SIZE bytes. + */ + __u32 size; + /** + * @brief [in] Flags describing requested allocation options. + */ + __u32 flags; /* enum hwmem_alloc_flags */ + /** + * @brief [in] Default access rights for buffer. + */ + __u32 default_access; /* enum hwmem_access */ + /** + * @brief [in] Memory type of the buffer. + */ + __u32 mem_type; /* enum hwmem_mem_type */ +}; + +/** + * @brief Set domain request data. + */ +struct hwmem_set_domain_request { + /** + * @brief [in] Identifier of buffer to be prepared. If 0 is specified + * the buffer associated with the current file instance will be used. + */ + __s32 id; + /** + * @brief [in] Flags specifying access mode of the operation. + * + * One of HWMEM_ACCESS_READ and HWMEM_ACCESS_WRITE is required. + * For details, @see enum hwmem_access. + */ + __u32 access; /* enum hwmem_access */ + /** + * @brief [in] The region of bytes to be prepared. + * + * For details, @see struct hwmem_region. + */ + struct hwmem_region_us region; +}; + +/** + * @brief Pin request data. + */ +struct hwmem_pin_request { + /** + * @brief [in] Identifier of buffer to be pinned. If 0 is specified, + * the buffer associated with the current file instance will be used. + */ + __s32 id; + /** + * @brief [out] Physical address of first word in buffer. + */ + __u32 phys_addr; +}; + +/** + * @brief Set access rights request data. + */ +struct hwmem_set_access_request { + /** + * @brief [in] Identifier of buffer to set access rights for. If 0 is + * specified, the buffer associated with the current file instance will + * be used. + */ + __s32 id; + /** + * @param access Access value indicating what is allowed. + */ + __u32 access; /* enum hwmem_access */ + /** + * @param pid Process ID to set rights for. + */ + pid_t pid; +}; + +/** + * @brief Get info request data. + */ +struct hwmem_get_info_request { + /** + * @brief [in] Identifier of buffer to get info about. If 0 is specified, + * the buffer associated with the current file instance will be used. + */ + __s32 id; + /** + * @brief [out] Size in bytes of buffer. + */ + __u32 size; + /** + * @brief [out] Memory type of buffer. + */ + __u32 mem_type; /* enum hwmem_mem_type */ + /** + * @brief [out] Access rights for buffer. + */ + __u32 access; /* enum hwmem_access */ +}; + +/** + * @brief Allocates <size> number of bytes and returns a buffer identifier. + * + * Input is a pointer to a hwmem_alloc_request struct. + * + * @return A buffer identifier on success, or a negative error code. + */ +#define HWMEM_ALLOC_IOC _IOW('W', 1, struct hwmem_alloc_request) + +/** + * @brief Allocates <size> number of bytes and associates the created buffer + * with the current file instance. + * + * If the current file instance is already associated with a buffer the call + * will fail. Buffers referenced through files instances shall not be released + * with HWMEM_RELEASE_IOC, instead the file instance shall be closed. + * + * Input is a pointer to a hwmem_alloc_request struct. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_ALLOC_FD_IOC _IOW('W', 2, struct hwmem_alloc_request) + +/** + * @brief Releases buffer. + * + * Buffers are reference counted and will not be destroyed until the last + * reference is released. Buffers allocated with ALLOC_FD_IOC shall not be + * released with this IOC, @see HWMEM_ALLOC_FD_IOC. + * + * Input is the buffer identifier. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_RELEASE_IOC _IO('W', 3) + +/** + * Memory Mapping + * + * To map a hwmem buffer mmap the hwmem fd and supply the buffer identifier as + * the offset. If the buffer is linked to the fd and thus have no buffer + * identifier supply 0 as the offset. Note that the offset feature of mmap is + * disabled in both cases, you can only mmap starting a position 0. + */ + +/** + * @brief Prepares the buffer for CPU access. + * + * Input is a pointer to a hwmem_set_domain_request struct. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_SET_CPU_DOMAIN_IOC _IOW('W', 4, struct hwmem_set_domain_request) + +/** + * DEPRECATED: Set sync domain from driver instead! + * + * @brief Prepares the buffer for access by any DMA hardware. + * + * Input is a pointer to a hwmem_set_domain_request struct. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_SET_SYNC_DOMAIN_IOC _IOW('W', 5, struct hwmem_set_domain_request) + +/** + * DEPRECATED: Pin from driver instead! + * + * @brief Pins the buffer. + * + * Input is a pointer to a hwmem_pin_request struct. Only contiguous buffers + * can be pinned from user space. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_PIN_IOC _IOWR('W', 6, struct hwmem_pin_request) + +/** + * DEPRECATED: Unpin from driver instead! + * + * @brief Unpins the buffer. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_UNPIN_IOC _IO('W', 7) + +/** + * @brief Set access rights for buffer. + * + * Input is a pointer to a hwmem_set_access_request struct. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_SET_ACCESS_IOC _IOW('W', 8, struct hwmem_set_access_request) + +/** + * @brief Get buffer information. + * + * Input is a pointer to a hwmem_get_info_request struct. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_GET_INFO_IOC _IOWR('W', 9, struct hwmem_get_info_request) + +/** + * @brief Export the buffer identifier for use in another process. + * + * The global name will not increase the buffers reference count and will + * therefore not keep the buffer alive. + * + * Input is the buffer identifier. If 0 is specified the buffer associated with + * the current file instance will be exported. + * + * @return A global buffer name on success, or a negative error code. + */ +#define HWMEM_EXPORT_IOC _IO('W', 10) + +/** + * @brief Import a buffer to allow local access to the buffer. + * + * Input is the buffer's global name. + * + * @return The imported buffer's identifier on success, or a negative error + * code. + */ +#define HWMEM_IMPORT_IOC _IO('W', 11) + +/** + * @brief Import a buffer to allow local access to the buffer using the current + * fd. + * + * Input is the buffer's global name. + * + * @return Zero on success, or a negative error code. + */ +#define HWMEM_IMPORT_FD_IOC _IO('W', 12) + +#ifdef __KERNEL__ + +/* Kernel API */ + +/** + * @brief Values defining memory domain. + */ +enum hwmem_domain { + /** + * @brief This value specifies the neutral memory domain. Setting this + * domain will syncronize all supported memory domains. + */ + HWMEM_DOMAIN_SYNC = 0, + /** + * @brief This value specifies the CPU memory domain. + */ + HWMEM_DOMAIN_CPU, +}; + +struct hwmem_alloc; + +/** + * @brief Structure defining a region of a memory buffer. + * + * A buffer is defined to contain a number of equally sized blocks. Each block + * has a part of it included in the region [<start>-<end>). That is + * <end>-<start> bytes. Each block is <size> bytes long. Total number of bytes + * in the region is (<end> - <start>) * <count>. First byte of the region is + * <offset> + <start> bytes into the buffer. + * + * Here's an example of a region in a graphics buffer (X = buffer, R = region): + * + * XXXXXXXXXXXXXXXXXXXX \ + * XXXXXXXXXXXXXXXXXXXX |-- offset = 60 + * XXXXXXXXXXXXXXXXXXXX / + * XXRRRRRRRRXXXXXXXXXX \ + * XXRRRRRRRRXXXXXXXXXX |-- count = 4 + * XXRRRRRRRRXXXXXXXXXX | + * XXRRRRRRRRXXXXXXXXXX / + * XXXXXXXXXXXXXXXXXXXX + * --| start = 2 + * ----------| end = 10 + * --------------------| size = 20 + */ +struct hwmem_region { + /** + * @brief The first block's offset from beginning of buffer. + */ + size_t offset; + /** + * @brief The number of blocks included in this region. + */ + size_t count; + /** + * @brief The index of the first byte included in this block. + */ + size_t start; + /** + * @brief The index of the last byte included in this block plus one. + */ + size_t end; + /** + * @brief The size in bytes of each block. + */ + size_t size; +}; + +struct hwmem_mem_chunk { + phys_addr_t paddr; + size_t size; +}; + +/** + * @brief Allocates <size> number of bytes. + * + * @param size Number of bytes to allocate. All allocations are page aligned. + * @param flags Allocation options. + * @param def_access Default buffer access rights. + * @param mem_type Memory type. + * + * @return Pointer to allocation, or a negative error code. + */ +struct hwmem_alloc *hwmem_alloc(size_t size, enum hwmem_alloc_flags flags, + enum hwmem_access def_access, enum hwmem_mem_type mem_type); + +/** + * @brief Release a previously allocated buffer. + * When last reference is released, the buffer will be freed. + * + * @param alloc Buffer to be released. + */ +void hwmem_release(struct hwmem_alloc *alloc); + +/** + * @brief Set the buffer domain and prepare it for access. + * + * @param alloc Buffer to be prepared. + * @param access Flags defining memory access mode of the call. + * @param domain Value specifying the memory domain. + * @param region Structure defining the minimum area of the buffer to be + * prepared. + * + * @return Zero on success, or a negative error code. + */ +int hwmem_set_domain(struct hwmem_alloc *alloc, enum hwmem_access access, + enum hwmem_domain domain, struct hwmem_region *region); + +/** + * @brief Pins the buffer. + * + * Notice that the number of mem chunks a buffer consists of can change at any + * time if the buffer is not pinned. Because of this one can not assume that + * pin will succeed if <mem_chunks> has the length specified by a previous call + * to pin as the buffer layout may have changed between the calls. There are + * two ways of handling this situation, keep redoing the pin procedure till it + * succeeds or allocate enough mem chunks for the worst case ("buffer size" / + * "page size" mem chunks). Contiguous buffers always require only one mem + * chunk. + * + * @param alloc Buffer to be pinned. + * @param mem_chunks Pointer to array of mem chunks. + * @param mem_chunks_length Pointer to variable that contains the length of + * <mem_chunks> array. On success the number of written mem chunks will be + * stored in this variable. If the call fails with -ENOSPC the required length + * of <mem_chunks> will be stored in this variable. + * + * @return Zero on success, or a negative error code. + */ +int hwmem_pin(struct hwmem_alloc *alloc, struct hwmem_mem_chunk *mem_chunks, + size_t *mem_chunks_length); + +/** + * @brief Unpins the buffer. + * + * @param alloc Buffer to be unpinned. + */ +void hwmem_unpin(struct hwmem_alloc *alloc); + +/** + * @brief Map the buffer to user space. + * + * @param alloc Buffer to be mapped. + * + * @return Zero on success, or a negative error code. + */ +int hwmem_mmap(struct hwmem_alloc *alloc, struct vm_area_struct *vma); + +/** + * @brief Map the buffer for use in the kernel. + * + * This function implicitly pins the buffer. + * + * @param alloc Buffer to be mapped. + * + * @return Pointer to buffer, or a negative error code. + */ +void *hwmem_kmap(struct hwmem_alloc *alloc); + +/** + * @brief Un-map a buffer previously mapped with hwmem_kmap. + * + * This function implicitly unpins the buffer. + * + * @param alloc Buffer to be un-mapped. + */ +void hwmem_kunmap(struct hwmem_alloc *alloc); + +/** + * @brief Set access rights for buffer. + * + * @param alloc Buffer to set rights for. + * @param access Access value indicating what is allowed. + * @param pid Process ID to set rights for. + */ +int hwmem_set_access(struct hwmem_alloc *alloc, enum hwmem_access access, + pid_t pid); + +/** + * @brief Get buffer information. + * + * @param alloc Buffer to get information about. + * @param size Pointer to size output variable. Can be NULL. + * @param size Pointer to memory type output variable. Can be NULL. + * @param size Pointer to access rights output variable. Can be NULL. + */ +void hwmem_get_info(struct hwmem_alloc *alloc, size_t *size, + enum hwmem_mem_type *mem_type, enum hwmem_access *access); + +/** + * @brief Allocate a global buffer name. + * Generated buffer name is valid in all processes. Consecutive calls will get + * the same name for the same buffer. + * + * @param alloc Buffer to be made public. + * + * @return Positive global name on success, or a negative error code. + */ +s32 hwmem_get_name(struct hwmem_alloc *alloc); + +/** + * @brief Import the global buffer name to allow local access to the buffer. + * This call will add a buffer reference. Resulting buffer should be + * released with a call to hwmem_release. + * + * @param name A valid global buffer name. + * + * @return Pointer to allocation, or a negative error code. + */ +struct hwmem_alloc *hwmem_resolve_by_name(s32 name); + +/* Integration */ + +struct hwmem_allocator_api { + void *(*alloc)(void *instance, size_t size); + void (*free)(void *instance, void *alloc); + phys_addr_t (*get_alloc_paddr)(void *alloc); + void *(*get_alloc_kaddr)(void *instance, void *alloc); + size_t (*get_alloc_size)(void *alloc); +}; + +struct hwmem_mem_type_struct { + enum hwmem_mem_type id; + struct hwmem_allocator_api allocator_api; + void *allocator_instance; +}; + +extern struct hwmem_mem_type_struct *hwmem_mem_types; +extern unsigned int hwmem_num_mem_types; + +#endif + +#endif /* _HWMEM_H_ */ diff --git a/include/linux/hwmon.h b/include/linux/hwmon.h index 6b6ee702b00..8e891b5a777 100644 --- a/include/linux/hwmon.h +++ b/include/linux/hwmon.h @@ -15,11 +15,16 @@ #define _HWMON_H_ #include <linux/device.h> +#include <linux/notifier.h> struct device *hwmon_device_register(struct device *dev); void hwmon_device_unregister(struct device *dev); +int hwmon_notifier_register(struct notifier_block *nb); +int hwmon_notifier_unregister(struct notifier_block *nb); +void hwmon_notify(unsigned long val, void *v); + /* Scale user input to sensible values */ static inline int SENSORS_LIMIT(long value, long low, long high) { diff --git a/include/linux/input/bu21013.h b/include/linux/input/bu21013.h index 05e03284b92..143f433b9ee 100644 --- a/include/linux/input/bu21013.h +++ b/include/linux/input/bu21013.h @@ -1,5 +1,5 @@ /* - * Copyright (C) ST-Ericsson SA 2010 + * Copyright (C) ST-Ericsson SA 2009 * Author: Naveen Kumar G <naveen.gaddipati@stericsson.com> for ST-Ericsson * License terms:GNU General Public License (GPL) version 2 */ @@ -9,32 +9,36 @@ /** * struct bu21013_platform_device - Handle the platform data - * @cs_en: pointer to the cs enable function - * @cs_dis: pointer to the cs disable function - * @irq_read_val: pointer to read the pen irq value function + * @cs_en: pointer to the cs enable function + * @cs_dis: pointer to the cs disable function + * @irq_read_val: pointer to read the pen irq value function + * @x_max_res: xmax resolution + * @y_max_res: ymax resolution * @touch_x_max: touch x max * @touch_y_max: touch y max * @cs_pin: chip select pin * @irq: irq pin - * @ext_clk: external clock flag + * @has_ext_clk: has external clock + * @enable_ext_clk: enable external clock + * @portrait: portrait mode flag * @x_flip: x flip flag * @y_flip: y flip flag - * @wakeup: wakeup flag - * * This is used to handle the platform data - */ + **/ struct bu21013_platform_device { int (*cs_en)(int reset_pin); int (*cs_dis)(int reset_pin); int (*irq_read_val)(void); + int x_max_res; + int y_max_res; int touch_x_max; int touch_y_max; unsigned int cs_pin; unsigned int irq; - bool ext_clk; + bool has_ext_clk; + bool enable_ext_clk; + bool portrait; bool x_flip; bool y_flip; - bool wakeup; }; - #endif diff --git a/include/linux/kexec.h b/include/linux/kexec.h index 0d7d6a1b172..9943c5dd618 100644 --- a/include/linux/kexec.h +++ b/include/linux/kexec.h @@ -120,6 +120,7 @@ struct kimage { /* kexec interface functions */ extern void machine_kexec(struct kimage *image); +extern void machine_crash_swreset(void); extern int machine_kexec_prepare(struct kimage *image); extern void machine_kexec_cleanup(struct kimage *image); extern asmlinkage long sys_kexec_load(unsigned long entry, @@ -170,6 +171,7 @@ unsigned long paddr_vmcoreinfo_note(void); extern struct kimage *kexec_image; extern struct kimage *kexec_crash_image; +extern struct atomic_notifier_head crash_percpu_notifier_list; #ifndef kexec_flush_icache_page #define kexec_flush_icache_page(page) diff --git a/include/linux/led-lm3530.h b/include/linux/led-lm3530.h index 8eb12357a11..2794e3b9e1d 100644 --- a/include/linux/led-lm3530.h +++ b/include/linux/led-lm3530.h @@ -58,6 +58,12 @@ #define LM3530_ALS_IMPD_700Ohm (0x0E) #define LM3530_ALS_IMPD_667Ohm (0x0F) +/* + * If lm3530 does not use a gpio for HWEN, set LM3530_NO_HWEN_GPIO + * for hw_en_gpio in lm3530_platform data member + */ +#define LM3530_NO_HWEN_GPIO -1 + enum lm3530_mode { LM3530_BL_MODE_MANUAL = 0, /* "man" */ LM3530_BL_MODE_ALS, /* "als" */ @@ -87,6 +93,7 @@ enum lm3530_als_mode { * @als_vmin: als input voltage calibrated for max brightness in mV * @als_vmax: als input voltage calibrated for min brightness in mV * @brt_val: brightness value (0-255) + * @hw_en_gpio: GPIO line for LM3530 HWEN */ struct lm3530_platform_data { enum lm3530_mode mode; @@ -107,6 +114,8 @@ struct lm3530_platform_data { u32 als_vmax; u8 brt_val; + + int hw_en_gpio; }; #endif /* _LINUX_LED_LM3530_H__ */ diff --git a/include/linux/leds-ab5500.h b/include/linux/leds-ab5500.h new file mode 100644 index 00000000000..9ba9ac61d90 --- /dev/null +++ b/include/linux/leds-ab5500.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2011 ST-Ericsson SA. + * + * License Terms: GNU General Public License v2 + * + * Simple driver for HVLED in ST-Ericsson AB5500 Analog baseband Controller + * + * Author: Shreshtha Kumar SAHU <shreshthakumar.sahu@stericsson.com> + */ + +#define AB5500_HVLED0 0 +#define AB5500_HVLED1 1 +#define AB5500_HVLED2 2 +#define AB5500_HVLEDS_MAX 3 + +enum ab5500_fade_delay { + AB5500_FADE_DELAY_BYPASS = 0, + AB5500_FADE_DELAY_HALFSEC, + AB5500_FADE_DELAY_ONESEC, + AB5500_FADE_DELAY_TWOSEC +}; + +struct ab5500_led_conf { + char *name; + u8 led_id; + u8 max_current; + u8 fade_hi; + u8 fade_lo; + bool led_on; +}; + +struct ab5500_hvleds_platform_data { + bool hw_fade; + struct ab5500_led_conf leds[AB5500_HVLEDS_MAX]; +}; diff --git a/include/linux/leds_pwm.h b/include/linux/leds_pwm.h index 33a07116748..9c5eab6e086 100644 --- a/include/linux/leds_pwm.h +++ b/include/linux/leds_pwm.h @@ -11,6 +11,7 @@ struct led_pwm { u8 active_low; unsigned max_brightness; unsigned pwm_period_ns; + unsigned int lth_brightness; }; struct led_pwm_platform_data { diff --git a/include/linux/mfd/ab8500/bm.h b/include/linux/mfd/ab8500/bm.h new file mode 100644 index 00000000000..a4c4519ab11 --- /dev/null +++ b/include/linux/mfd/ab8500/bm.h @@ -0,0 +1,547 @@ +/* + * Copyright ST-Ericsson 2009. + * + * Author: Arun Murthy <arun.murthy@stericsson.com> + * Licensed under GPLv2. + */ + +#ifndef _AB8500_BM_H +#define _AB8500_BM_H + +#include <linux/kernel.h> + +/* + * System control 2 register offsets. + * bank = 0x02 + */ +#define AB8500_MAIN_WDOG_CTRL_REG 0x01 +#define AB8500_LOW_BAT_REG 0x03 +#define AB8500_BATT_OK_REG 0x04 +/* + * USB/ULPI register offsets + * Bank : 0x5 + */ +#define AB8500_USB_LINE_STAT_REG 0x80 + +/* + * Charger / status register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_STATUS1_REG 0x00 +#define AB8500_CH_STATUS2_REG 0x01 +#define AB8500_CH_USBCH_STAT1_REG 0x02 +#define AB8500_CH_USBCH_STAT2_REG 0x03 +#define AB8500_CH_FSM_STAT_REG 0x04 +#define AB8500_CH_STAT_REG 0x05 + +/* + * Charger / control register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_VOLT_LVL_REG 0x40 +#define AB8500_CH_VOLT_LVL_MAX_REG 0x41 /*Only in Cut2.0*/ +#define AB8500_CH_OPT_CRNTLVL_REG 0x42 +#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x43 /*Only in Cut2.0*/ +#define AB8500_CH_WD_TIMER_REG 0x50 +#define AB8500_CHARG_WD_CTRL 0x51 +#define AB8500_BTEMP_HIGH_TH 0x52 +#define AB8500_LED_INDICATOR_PWM_CTRL 0x53 +#define AB8500_LED_INDICATOR_PWM_DUTY 0x54 +#define AB8500_BATT_OVV 0x55 +#define AB8500_CHARGER_CTRL 0x56 +#define AB8500_BAT_CTRL_CURRENT_SOURCE 0x60 /*Only in Cut2.0*/ + +/* + * Charger / main control register offsets + * Bank : 0x0B + */ +#define AB8500_MCH_CTRL1 0x80 +#define AB8500_MCH_CTRL2 0x81 +#define AB8500_MCH_IPT_CURLVL_REG 0x82 +#define AB8500_CH_WD_REG 0x83 + +/* + * Charger / USB control register offsets + * Bank : 0x0B + */ +#define AB8500_USBCH_CTRL1_REG 0xC0 +#define AB8500_USBCH_CTRL2_REG 0xC1 +#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2 + +/* + * Gas Gauge register offsets + * Bank : 0x0C + */ +#define AB8500_GASG_CC_CTRL_REG 0x00 +#define AB8500_GASG_CC_ACCU1_REG 0x01 +#define AB8500_GASG_CC_ACCU2_REG 0x02 +#define AB8500_GASG_CC_ACCU3_REG 0x03 +#define AB8500_GASG_CC_ACCU4_REG 0x04 +#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x05 +#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x06 +#define AB8500_GASG_CC_SMPL_CNVL_REG 0x07 +#define AB8500_GASG_CC_SMPL_CNVH_REG 0x08 +#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x09 +#define AB8500_GASG_CC_OFFSET_REG 0x0A +#define AB8500_GASG_CC_NCOV_ACCU 0x10 +#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x11 +#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x12 +#define AB8500_GASG_CC_NCOV_ACCU_MED 0x13 +#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x14 + +/* + * Interrupt register offsets + * Bank : 0x0E + */ +#define AB8500_IT_SOURCE2_REG 0x01 +#define AB8500_IT_SOURCE21_REG 0x14 + +/* + * RTC register offsets + * Bank: 0x0F + */ +#define AB8500_RTC_BACKUP_CHG_REG 0x0C +#define AB8500_RTC_CC_CONF_REG 0x01 +#define AB8500_RTC_CTRL_REG 0x0B + +/* + * OTP register offsets + * Bank : 0x15 + */ +#define AB8500_OTP_CONF_15 0x0E + +/* GPADC constants from AB8500 spec, UM0836 */ +#define ADC_RESOLUTION 1024 +#define ADC_CH_MAIN_MIN 0 +#define ADC_CH_MAIN_MAX 20030 +#define ADC_CH_VBUS_MIN 0 +#define ADC_CH_VBUS_MAX 20030 +#define ADC_CH_VBAT_MIN 2300 +#define ADC_CH_VBAT_MAX 4800 +#define ADC_CH_BKBAT_MIN 0 +#define ADC_CH_BKBAT_MAX 3200 + +/* Main charge i/p current */ +#define MAIN_CH_IP_CUR_0P9A 0x80 +#define MAIN_CH_IP_CUR_1P0A 0x90 +#define MAIN_CH_IP_CUR_1P1A 0xA0 +#define MAIN_CH_IP_CUR_1P2A 0xB0 +#define MAIN_CH_IP_CUR_1P3A 0xC0 +#define MAIN_CH_IP_CUR_1P4A 0xD0 +#define MAIN_CH_IP_CUR_1P5A 0xE0 + +/* ChVoltLevel */ +#define CH_VOL_LVL_3P5 0x00 +#define CH_VOL_LVL_4P0 0x14 +#define CH_VOL_LVL_4P05 0x16 +#define CH_VOL_LVL_4P1 0x1B +#define CH_VOL_LVL_4P15 0x20 +#define CH_VOL_LVL_4P2 0x25 +#define CH_VOL_LVL_4P6 0x4D + +/* ChOutputCurrentLevel */ +#define CH_OP_CUR_LVL_0P1 0x00 +#define CH_OP_CUR_LVL_0P2 0x01 +#define CH_OP_CUR_LVL_0P3 0x02 +#define CH_OP_CUR_LVL_0P4 0x03 +#define CH_OP_CUR_LVL_0P5 0x04 +#define CH_OP_CUR_LVL_0P6 0x05 +#define CH_OP_CUR_LVL_0P7 0x06 +#define CH_OP_CUR_LVL_0P8 0x07 +#define CH_OP_CUR_LVL_0P9 0x08 +#define CH_OP_CUR_LVL_1P4 0x0D +#define CH_OP_CUR_LVL_1P5 0x0E +#define CH_OP_CUR_LVL_1P6 0x0F + +/* BTEMP High thermal limits */ +#define BTEMP_HIGH_TH_57_0 0x00 +#define BTEMP_HIGH_TH_52 0x01 +#define BTEMP_HIGH_TH_57_1 0x02 +#define BTEMP_HIGH_TH_62 0x03 + +/* current is mA */ +#define USB_0P1A 100 +#define USB_0P2A 200 +#define USB_0P3A 300 +#define USB_0P4A 400 +#define USB_0P5A 500 + +#define LOW_BAT_3P1V 0x20 +#define LOW_BAT_2P3V 0x00 +#define LOW_BAT_RESET 0x01 +#define LOW_BAT_ENABLE 0x01 + +/* Backup battery constants */ +#define BUP_ICH_SEL_50UA 0x00 +#define BUP_ICH_SEL_150UA 0x04 +#define BUP_ICH_SEL_300UA 0x08 +#define BUP_ICH_SEL_700UA 0x0C + +#define BUP_VCH_SEL_2P5V 0x00 +#define BUP_VCH_SEL_2P6V 0x01 +#define BUP_VCH_SEL_2P8V 0x02 +#define BUP_VCH_SEL_3P1V 0x03 + +/* Battery OVV constants */ +#define BATT_OVV_ENA 0x02 +#define BATT_OVV_TH_3P7 0x00 +#define BATT_OVV_TH_4P75 0x01 + +/* VBUS OVV constants */ +#define VBUS_OVV_SELECT_MASK 0x78 +#define VBUS_OVV_SELECT_5P6V 0x00 +#define VBUS_OVV_SELECT_5P7V 0x08 +#define VBUS_OVV_SELECT_5P8V 0x10 +#define VBUS_OVV_SELECT_5P9V 0x18 +#define VBUS_OVV_SELECT_6P0V 0x20 +#define VBUS_OVV_SELECT_6P1V 0x28 +#define VBUS_OVV_SELECT_6P2V 0x30 +#define VBUS_OVV_SELECT_6P3V 0x38 + +#define VBUS_AUTO_IN_CURR_LIM_ENA 0x04 + +/* Fuel Gauge constants */ +#define RESET_ACCU 0x02 +#define READ_REQ 0x01 +#define CC_DEEP_SLEEP_ENA 0x02 +#define CC_PWR_UP_ENA 0x01 +#define CC_SAMPLES_40 0x28 +#define RD_NCONV_ACCU_REQ 0x01 +#define CC_CALIB 0x08 +#define CC_INTAVGOFFSET_ENA 0x10 +#define CC_MUXOFFSET 0x80 +#define CC_INT_CAL_N_AVG_MASK 0x60 +#define CC_INT_CAL_SAMPLES_16 0x40 +#define CC_INT_CAL_SAMPLES_8 0x20 +#define CC_INT_CAL_SAMPLES_4 0x00 + +/* RTC constants */ +#define RTC_BUP_CH_ENA 0x10 + +/* BatCtrl Current Source Constants */ +#define BAT_CTRL_7U_ENA 0x01 +#define BAT_CTRL_20U_ENA 0x02 +#define BAT_CTRL_CMP_ENA 0x04 +#define FORCE_BAT_CTRL_CMP_HIGH 0x08 +#define BAT_CTRL_PULL_UP_ENA 0x10 + +/* Battery type */ +#define BATTERY_UNKNOWN 00 + +/* + * ADC for the battery thermistor. + * When using the ADC_THERM_BATCTRL the battery ID resistor is combined with + * a NTC resistor to both identify the battery and to measure its temperature. + * Different phone manufactures uses different techniques to both identify the + * battery and to read its temperature. + */ +enum adc_therm { + ADC_THERM_BATCTRL, + ADC_THERM_BATTEMP, +}; + +/** + * struct res_to_temp - defines one point in a temp to res curve. To + * be used in battery packs that combines the identification resistor with a + * NTC resistor. + * @temp: battery pack temperature in Celcius + * @resist: NTC resistor net total resistance + */ +struct res_to_temp { + int temp; + int resist; +}; + +/** + * struct batres_vs_temp - defines one point in a temp vs battery internal + * resistance curve. + * @temp: battery pack temperature in Celcius + * @resist: battery internal reistance in mOhm + */ +struct batres_vs_temp { + int temp; + int resist; +}; + +/** + * struct v_to_cap - Table for translating voltage to capacity + * @voltage: Voltage in mV + * @capacity: Capacity in percent + */ +struct v_to_cap { + int voltage; + int capacity; +}; + +/* Forward declaration */ +struct ab8500_fg; + +/** + * struct ab8500_fg_parameters - Fuel gauge algorithm parameters, in seconds + * if not specified + * @recovery_sleep_timer: Time between measurements while recovering + * @recovery_total_time: Total recovery time + * @init_timer: Measurement interval during startup + * @init_discard_time: Time we discard voltage measurement at startup + * @init_total_time: Total init time during startup + * @high_curr_time: Time current has to be high to go to recovery + * @accu_charging: FG accumulation time while charging + * @accu_high_curr: FG accumulation time in high current mode + * @high_curr_threshold: High current threshold, in mA + * @lowbat_threshold: Low battery threshold, in mV + * @battok_falling_th_sel0 Threshold in mV for battOk signal sel0 + * Resolution in 50 mV step. + * @battok_raising_th_sel1 Threshold in mV for battOk signal sel1 + * Resolution in 50 mV step. + * @user_cap_limit Capacity reported from user must be within this + * limit to be considered as sane, in percentage + * points. + * @maint_thres This is the threshold where we stop reporting + * battery full while in maintenance, in per cent + */ +struct ab8500_fg_parameters { + int recovery_sleep_timer; + int recovery_total_time; + int init_timer; + int init_discard_time; + int init_total_time; + int high_curr_time; + int accu_charging; + int accu_high_curr; + int high_curr_threshold; + int lowbat_threshold; + int battok_falling_th_sel0; + int battok_raising_th_sel1; + int user_cap_limit; + int maint_thres; +}; + +/** + * struct ab8500_charger_maximization - struct used by the board config. + * @use_maxi: Enable maximization for this battery type + * @maxi_chg_curr: Maximum charger current allowed + * @maxi_wait_cycles: cycles to wait before setting charger current + * @charger_curr_step delta between two charger current settings (mA) + */ +struct ab8500_maxim_parameters { + bool ena_maxi; + int chg_curr; + int wait_cycles; + int charger_curr_step; +}; + +/** + * struct battery_type - different batteries supported + * @name: battery technology + * @resis_high: battery upper resistance limit + * @resis_low: battery lower resistance limit + * @charge_full_design: Maximum battery capacity in mAh + * @nominal_voltage: Nominal voltage of the battery in mV + * @termination_vol: max voltage upto which battery can be charged + * @termination_curr battery charging termination current in mA + * @recharge_vol battery voltage limit that will trigger a new + * full charging cycle in the case where maintenan- + * -ce charging has been disabled + * @normal_cur_lvl: charger current in normal state in mA + * @normal_vol_lvl: charger voltage in normal state in mV + * @maint_a_cur_lvl: charger current in maintenance A state in mA + * @maint_a_vol_lvl: charger voltage in maintenance A state in mV + * @maint_a_chg_timer_h: charge time in maintenance A state + * @maint_b_cur_lvl: charger current in maintenance B state in mA + * @maint_b_vol_lvl: charger voltage in maintenance B state in mV + * @maint_b_chg_timer_h: charge time in maintenance B state + * @low_high_cur_lvl: charger current in temp low/high state in mA + * @low_high_vol_lvl: charger voltage in temp low/high state in mV' + * @battery_resistance: battery inner resistance in mOhm. + * @n_r_t_tbl_elements: number of elements in r_to_t_tbl + * @r_to_t_tbl: table containing resistance to temp points + * @n_v_cap_tbl_elements: number of elements in v_to_cap_tbl + * @v_to_cap_tbl: Voltage to capacity (in %) table + * @n_batres_tbl_elements number of elements in the batres_tbl + * @batres_tbl battery internal resistance vs temperature table + */ +struct battery_type { + int name; + int resis_high; + int resis_low; + int charge_full_design; + int nominal_voltage; + int termination_vol; + int termination_curr; + int recharge_vol; + int normal_cur_lvl; + int normal_vol_lvl; + int maint_a_cur_lvl; + int maint_a_vol_lvl; + int maint_a_chg_timer_h; + int maint_b_cur_lvl; + int maint_b_vol_lvl; + int maint_b_chg_timer_h; + int low_high_cur_lvl; + int low_high_vol_lvl; + int battery_resistance; + int n_temp_tbl_elements; + struct res_to_temp *r_to_t_tbl; + int n_v_cap_tbl_elements; + struct v_to_cap *v_to_cap_tbl; + int n_batres_tbl_elements; + struct batres_vs_temp *batres_tbl; +}; + +/** + * struct ab8500_bm_capacity_levels - ab8500 capacity level data + * @critical: critical capacity level in percent + * @low: low capacity level in percent + * @normal: normal capacity level in percent + * @high: high capacity level in percent + * @full: full capacity level in percent + */ +struct ab8500_bm_capacity_levels { + int critical; + int low; + int normal; + int high; + int full; +}; + +/** + * struct ab8500_bm_charger_parameters - Charger specific parameters + * @usb_volt_max: maximum allowed USB charger voltage in mV + * @usb_curr_max: maximum allowed USB charger current in mA + * @ac_volt_max: maximum allowed AC charger voltage in mV + * @ac_curr_max: maximum allowed AC charger current in mA + */ +struct ab8500_bm_charger_parameters { + int usb_volt_max; + int usb_curr_max; + int ac_volt_max; + int ac_curr_max; +}; + +/** + * struct ab8500_bm_data - ab8500 battery management data + * @temp_under under this temp, charging is stopped + * @temp_low between this temp and temp_under charging is reduced + * @temp_high between this temp and temp_over charging is reduced + * @temp_over over this temp, charging is stopped + * @temp_interval_chg temperature measurement interval in s when charging + * @temp_interval_nochg temperature measurement interval in s when not charging + * @main_safety_tmr_h safety timer for main charger + * @usb_safety_tmr_h safety timer for usb charger + * @bkup_bat_v voltage which we charge the backup battery with + * @bkup_bat_i current which we charge the backup battery with + * @no_maintenance indicates that maintenance charging is disabled + * @adc_therm placement of thermistor, batctrl or battemp adc + * @chg_unknown_bat flag to enable charging of unknown batteries + * @enable_overshoot flag to enable VBAT overshoot control + * @fg_res resistance of FG resistor in 0.1mOhm + * @n_btypes number of elements in array bat_type + * @batt_id index of the identified battery in array bat_type + * @interval_charging charge alg cycle period time when charging (sec) + * @interval_not_charging charge alg cycle period time when not charging (sec) + * @temp_hysteresis temperature hysteresis + * @gnd_lift_resistance Battery ground to phone ground resistance (mOhm) + * @maxi: maximization parameters + * @cap_levels capacity in percent for the different capacity levels + * @bat_type table of supported battery types + * @chg_params charger parameters + * @fg_params fuel gauge parameters + */ +struct ab8500_bm_data { + int temp_under; + int temp_low; + int temp_high; + int temp_over; + int temp_interval_chg; + int temp_interval_nochg; + int main_safety_tmr_h; + int usb_safety_tmr_h; + int bkup_bat_v; + int bkup_bat_i; + bool no_maintenance; + bool chg_unknown_bat; + bool enable_overshoot; + enum adc_therm adc_therm; + int fg_res; + int n_btypes; + int batt_id; + int interval_charging; + int interval_not_charging; + int temp_hysteresis; + int gnd_lift_resistance; + const struct ab8500_maxim_parameters *maxi; + const struct ab8500_bm_capacity_levels *cap_levels; + const struct battery_type *bat_type; + const struct ab8500_bm_charger_parameters *chg_params; + const struct ab8500_fg_parameters *fg_params; +}; + +struct ab8500_charger_platform_data { + char **supplied_to; + size_t num_supplicants; + bool autopower_cfg; +}; + +struct ab8500_btemp_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct ab8500_fg_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct ab8500_chargalg_platform_data { + char **supplied_to; + size_t num_supplicants; +}; +struct ab8500_btemp; +struct ab8500_gpadc; +struct ab8500_fg; +#ifdef CONFIG_AB8500_BM +void ab8500_fg_reinit(void); +void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA); +struct ab8500_btemp *ab8500_btemp_get(void); +int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp); +struct ab8500_fg *ab8500_fg_get(void); +int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev); +int ab8500_fg_inst_curr_start(struct ab8500_fg *di); +int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res); + +#else +static void ab8500_fg_reinit(void) +{ +} +static void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA) +{ +} +static struct ab8500_btemp *ab8500_btemp_get(void) +{ + return NULL; +} +static int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp) +{ + return 0; +} +struct ab8500_fg *ab8500_fg_get(void) +{ + return NULL; +} +static int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev) +{ + return -ENODEV; +} + +static inline int ab8500_fg_inst_curr_start(struct ab8500_fg *di) +{ + return -ENODEV; +} + +static inline int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res) +{ + return -ENODEV; +} + +#endif +#endif /* _AB8500_BM_H */ diff --git a/include/linux/mfd/ab8500/denc-regs.h b/include/linux/mfd/ab8500/denc-regs.h new file mode 100644 index 00000000000..a6683ca7470 --- /dev/null +++ b/include/linux/mfd/ab8500/denc-regs.h @@ -0,0 +1,357 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson AB8500 DENC related registers + * + * Author: Marcus Tunnissen <marcel.tuennissen@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __AB8500_DENC_H +#define __AB8500_DENC_H + +#define AB8500_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define AB8500_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define AB8500_CTRL3 0x00000200 +#define AB8500_CTRL3_TH_SD_ENA_SHIFT 3 +#define AB8500_CTRL3_TH_SD_ENA_MASK 0x00000008 +#define AB8500_CTRL3_TH_SD_ENA(__x) \ + AB8500_VAL2REG(AB8500_CTRL3, TH_SD_ENA, __x) +#define AB8500_CTRL3_RESET_DENC_N_SHIFT 2 +#define AB8500_CTRL3_RESET_DENC_N_MASK 0x00000004 +#define AB8500_CTRL3_RESET_DENC_N(__x) \ + AB8500_VAL2REG(AB8500_CTRL3, RESET_DENC_N, __x) +#define AB8500_CTRL3_RESET_AUD_N_SHIFT 1 +#define AB8500_CTRL3_RESET_AUD_N_MASK 0x00000002 +#define AB8500_CTRL3_RESET_AUD_N(__x) \ + AB8500_VAL2REG(AB8500_CTRL3, RESET_AUD_N, __x) +#define AB8500_CTRL3_CLK_32K_OUT2_IS_SHIFT 0 +#define AB8500_CTRL3_CLK_32K_OUT2_IS_MASK 0x00000001 +#define AB8500_CTRL3_CLK_32K_OUT2_IS(__x) \ + AB8500_VAL2REG(AB8500_CTRL3, CLK_32K_OUT2_IS, __x) +#define AB8500_SYS_ULP_CLK_CONF 0x0000020A +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA_SHIFT 7 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA_MASK 0x00000080 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_PD_ENA, __x) +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA_SHIFT 6 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA_MASK 0x00000040 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_BUF_ENA, __x) +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE_SHIFT 5 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE_MASK 0x00000020 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, ULP_CLK_STRE, __x) +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV_SHIFT 4 +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV_MASK 0x00000010 +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_INV, __x) +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN_SHIFT 3 +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN_MASK 0x00000008 +#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_DE_IN, __x) +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE_SHIFT 2 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE_MASK 0x00000004 +#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_STRE, __x) +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_SHIFT 0 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_MASK 0x00000003 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_NO_FUNC 0 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_AS_OUTPUT 1 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_AS_INPUT 2 +#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF(__x) \ + AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, ULP_CLK_CONF, \ + AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_##__x) +#define AB8500_SYS_CLK_CTRL 0x0000020C +#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID_SHIFT 2 +#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID_MASK 0x00000004 +#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID(__x) \ + AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, USB_CLK_VALID, __x) +#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID_SHIFT 1 +#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID_MASK 0x00000002 +#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID(__x) \ + AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, TVOUT_CLK_VALID, __x) +#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA_SHIFT 0 +#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA_MASK 0x00000001 +#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA(__x) \ + AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, TVOUT_PLL_ENA, __x) +#define AB8500_REGU_MISC1 0x00000380 +#define AB8500_REGU_MISC1_V_TVOUT_LP_SHIFT 7 +#define AB8500_REGU_MISC1_V_TVOUT_LP_MASK 0x00000080 +#define AB8500_REGU_MISC1_V_TVOUT_LP(__x) \ + AB8500_VAL2REG(AB8500_REGU_MISC1, V_TVOUT_LP, __x) +#define AB8500_REGU_MISC1_V_INT_CORE_12_LP_SHIFT 6 +#define AB8500_REGU_MISC1_V_INT_CORE_12_LP_MASK 0x00000040 +#define AB8500_REGU_MISC1_V_INT_CORE_12_LP(__x) \ + AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_LP, __x) +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_SHIFT 3 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_MASK 0x00000038 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_2V 0 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_225V 1 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_25V 2 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_275V 3 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_3V 4 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_325V 5 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_35V 6 +#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL(__x) \ + AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_SEL, \ + AB8500_REGU_MISC1_V_INT_CORE_12_SEL_##__x) +#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA_SHIFT 2 +#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA_MASK 0x00000004 +#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA(__x) \ + AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_ENA, __x) +#define AB8500_REGU_MISC1_V_TVOUT_ENA_SHIFT 1 +#define AB8500_REGU_MISC1_V_TVOUT_ENA_MASK 0x00000002 +#define AB8500_REGU_MISC1_V_TVOUT_ENA(__x) \ + AB8500_VAL2REG(AB8500_REGU_MISC1, V_TVOUT_ENA, __x) +#define AB8500_VAUX12_REGU 0x00000409 +#define AB8500_VAUX12_REGU_VAUX_1_SHIFT 2 +#define AB8500_VAUX12_REGU_VAUX_1_MASK 0x0000000C +#define AB8500_VAUX12_REGU_VAUX_1_DISABLE 0 +#define AB8500_VAUX12_REGU_VAUX_1_FORCE_HP 1 +#define AB8500_VAUX12_REGU_VAUX_1_BY_CTRL_REG 2 +#define AB8500_VAUX12_REGU_VAUX_1_FORCE_LP 3 +#define AB8500_VAUX12_REGU_VAUX_1(__x) \ + AB8500_VAL2REG(AB8500_VAUX12_REGU, VAUX_1, \ + AB8500_VAUX12_REGU_VAUX_1_##__x) +#define AB8500_VAUX12_REGU_VAUX_2_SHIFT 0 +#define AB8500_VAUX12_REGU_VAUX_2_MASK 0x00000003 +#define AB8500_VAUX12_REGU_VAUX_2_DISABLE 0 +#define AB8500_VAUX12_REGU_VAUX_2_FORCE_HP 1 +#define AB8500_VAUX12_REGU_VAUX_2_BY_CTRL_REG 2 +#define AB8500_VAUX12_REGU_VAUX_2_FORCE_LP 3 +#define AB8500_VAUX12_REGU_VAUX_2(__x) \ + AB8500_VAL2REG(AB8500_VAUX12_REGU, VAUX_2, \ + AB8500_VAUX12_REGU_VAUX_2_##__x) +#define AB8500_VAUX1_SEL 0x0000041F +#define AB8500_VAUX1_SEL_VAL_SHIFT 0 +#define AB8500_VAUX1_SEL_VAL_MASK 0x0000000F +#define AB8500_VAUX1_SEL_VAL_1_1V 0 +#define AB8500_VAUX1_SEL_VAL_1_2V 1 +#define AB8500_VAUX1_SEL_VAL_1_3V 2 +#define AB8500_VAUX1_SEL_VAL_1_4V 3 +#define AB8500_VAUX1_SEL_VAL_1_5V 4 +#define AB8500_VAUX1_SEL_VAL_1_8V 5 +#define AB8500_VAUX1_SEL_VAL_1_85V 6 +#define AB8500_VAUX1_SEL_VAL_1_9V 7 +#define AB8500_VAUX1_SEL_VAL_2_5V 8 +#define AB8500_VAUX1_SEL_VAL_2_65V 9 +#define AB8500_VAUX1_SEL_VAL_2_7V 10 +#define AB8500_VAUX1_SEL_VAL_2_75V 11 +#define AB8500_VAUX1_SEL_VAL_2_8V 12 +#define AB8500_VAUX1_SEL_VAL_2_9V 13 +#define AB8500_VAUX1_SEL_VAL_3_0V 14 +#define AB8500_VAUX1_SEL_VAL_3_3V 15 +#define AB8500_VAUX1_SEL_VAL(__x) \ + AB8500_VAL2REG(AB8500_VAUX1_SEL, VAL, AB8500_VAUX1_SEL_VAL_##__x) +#define AB8500_DENC_CONF0 0x00000600 +#define AB8500_DENC_CONF0_STD_SHIFT 6 +#define AB8500_DENC_CONF0_STD_MASK 0x000000C0 +#define AB8500_DENC_CONF0_STD_PAL_BDGHI 0 +#define AB8500_DENC_CONF0_STD_PAL_N 1 +#define AB8500_DENC_CONF0_STD_NTSC_M 2 +#define AB8500_DENC_CONF0_STD_PAL_M 3 +#define AB8500_DENC_CONF0_STD(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF0, STD, AB8500_DENC_CONF0_STD_##__x) +#define AB8500_DENC_CONF0_SYNC_SHIFT 3 +#define AB8500_DENC_CONF0_SYNC_MASK 0x00000038 +#define AB8500_DENC_CONF0_SYNC_F_BASED_SLAVE 1 +#define AB8500_DENC_CONF0_SYNC_AUTO_TEST 7 +#define AB8500_DENC_CONF0_SYNC(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF0, SYNC, AB8500_DENC_CONF0_SYNC_##__x) +#define AB8500_DENC_CONF1 0x00000601 +#define AB8500_DENC_CONF1_BLK_LI_SHIFT 7 +#define AB8500_DENC_CONF1_BLK_LI_MASK 0x00000080 +#define AB8500_DENC_CONF1_BLK_LI_PARTIAL 0 +#define AB8500_DENC_CONF1_BLK_LI_FULL 1 +#define AB8500_DENC_CONF1_BLK_LI(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF1, BLK_LI, \ + AB8500_DENC_CONF1_BLK_LI_##__x) +#define AB8500_DENC_CONF1_FLT_SHIFT 5 +#define AB8500_DENC_CONF1_FLT_MASK 0x00000060 +#define AB8500_DENC_CONF1_FLT_1_1MHZ 0 +#define AB8500_DENC_CONF1_FLT_1_3MHZ 1 +#define AB8500_DENC_CONF1_FLT_1_6MHZ 2 +#define AB8500_DENC_CONF1_FLT_1_9MHZ 3 +#define AB8500_DENC_CONF1_FLT(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF1, FLT, AB8500_DENC_CONF1_FLT_##__x) +#define AB8500_DENC_CONF1_CO_KI_SHIFT 3 +#define AB8500_DENC_CONF1_CO_KI_MASK 0x00000008 +#define AB8500_DENC_CONF1_CO_KI(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF1, CO_KI, __x) +#define AB8500_DENC_CONF1_SETUP_MAIN_SHIFT 2 +#define AB8500_DENC_CONF1_SETUP_MAIN_MASK 0x00000004 +#define AB8500_DENC_CONF1_SETUP_MAIN_BLACK_EQ_BLANK 0 +#define AB8500_DENC_CONF1_SETUP_MAIN_BLACK_GT_BLANK 1 +#define AB8500_DENC_CONF1_SETUP_MAIN(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF1, SETUP_MAIN, \ + AB8500_DENC_CONF1_SETUP_MAIN_##__x) +#define AB8500_DENC_CONF1_CC_SHIFT 0 +#define AB8500_DENC_CONF1_CC_MASK 0x00000003 +#define AB8500_DENC_CONF1_CC_NONE 0 +#define AB8500_DENC_CONF1_CC_FIELD_1 1 +#define AB8500_DENC_CONF1_CC_FIELD_2 2 +#define AB8500_DENC_CONF1_CC_ALL 3 +#define AB8500_DENC_CONF1_CC(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF1, CC, AB8500_DENC_CONF1_CC_##__x) +#define AB8500_DENC_CONF2 0x00000602 +#define AB8500_DENC_CONF2_N_INTRL_SHIFT 7 +#define AB8500_DENC_CONF2_N_INTRL_MASK 0x00000080 +#define AB8500_DENC_CONF2_N_INTRL(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, N_INTRL, __x) +#define AB8500_DENC_CONF2_EN_RST_SHIFT 6 +#define AB8500_DENC_CONF2_EN_RST_MASK 0x00000040 +#define AB8500_DENC_CONF2_EN_RST(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, EN_RST, __x) +#define AB8500_DENC_CONF2_BURST_EN_SHIFT 5 +#define AB8500_DENC_CONF2_BURST_EN_MASK 0x00000020 +#define AB8500_DENC_CONF2_BURST_EN(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, BURST_EN, __x) +#define AB8500_DENC_CONF2_SEL_RST_SHIFT 4 +#define AB8500_DENC_CONF2_SEL_RST_MASK 0x00000010 +#define AB8500_DENC_CONF2_SEL_RST_USE_HW_VAL 0 +#define AB8500_DENC_CONF2_SEL_RST_USE_PROG_VAL 1 +#define AB8500_DENC_CONF2_SEL_RST(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, SEL_RST, \ + AB8500_DENC_CONF2_SEL_RST_##__x) +#define AB8500_DENC_CONF2_RST_OSC_BUF_SHIFT 2 +#define AB8500_DENC_CONF2_RST_OSC_BUF_MASK 0x00000004 +#define AB8500_DENC_CONF2_RST_OSC_BUF(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, RST_OSC_BUF, __x) +#define AB8500_DENC_CONF2_VAL_RST_SHIFT 0 +#define AB8500_DENC_CONF2_VAL_RST_MASK 0x00000003 +#define AB8500_DENC_CONF2_VAL_RST_ALL_LINES 0 +#define AB8500_DENC_CONF2_VAL_RST_EVERY_2ND_FIELD 1 +#define AB8500_DENC_CONF2_VAL_RST_EVERY_4TH_FIELD 2 +#define AB8500_DENC_CONF2_VAL_RST_EVERY_8TH_FIELD 3 +#define AB8500_DENC_CONF2_VAL_RST(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF2, VAL_RST, \ + AB8500_DENC_CONF2_VAL_RST_##__x) +#define AB8500_DENC_CONF6 0x00000606 +#define AB8500_DENC_CONF6_SOFT_RESET_SHIFT 7 +#define AB8500_DENC_CONF6_SOFT_RESET_MASK 0x00000080 +#define AB8500_DENC_CONF6_SOFT_RESET(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF6, SOFT_RESET, __x) +#define AB8500_DENC_CONF6_JUMP_SHIFT 6 +#define AB8500_DENC_CONF6_JUMP_MASK 0x00000040 +#define AB8500_DENC_CONF6_JUMP(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF6, JUMP, __x) +#define AB8500_DENC_CONF6_DEC_NINC_SHIFT 5 +#define AB8500_DENC_CONF6_DEC_NINC_MASK 0x00000020 +#define AB8500_DENC_CONF6_DEC_NINC(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF6, DEC_NINC, __x) +#define AB8500_DENC_CONF6_FREE_JUMP_SHIFT 4 +#define AB8500_DENC_CONF6_FREE_JUMP_MASK 0x00000010 +#define AB8500_DENC_CONF6_FREE_JUMP(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF6, FREE_JUMP, __x) +#define AB8500_DENC_CONF6_MAX_DYN_SHIFT 0 +#define AB8500_DENC_CONF6_MAX_DYN_MASK 0x00000001 +#define AB8500_DENC_CONF6_MAX_DYN(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF6, MAX_DYN, __x) +#define AB8500_DENC_CONF8 0x00000608 +#define AB8500_DENC_CONF8_PH_RST_MODE_SHIFT 6 +#define AB8500_DENC_CONF8_PH_RST_MODE_MASK 0x000000C0 +#define AB8500_DENC_CONF8_PH_RST_MODE_DISABLED 0 +#define AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_PHASE_BUF 1 +#define AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_INC_DFS 2 +#define AB8500_DENC_CONF8_PH_RST_MODE_RESET 3 +#define AB8500_DENC_CONF8_PH_RST_MODE(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF8, PH_RST_MODE, \ + AB8500_DENC_CONF8_PH_RST_MODE_##__x) +#define AB8500_DENC_CONF8_VAL_422_MUX_SHIFT 4 +#define AB8500_DENC_CONF8_VAL_422_MUX_MASK 0x00000010 +#define AB8500_DENC_CONF8_VAL_422_MUX_TEST 0 +#define AB8500_DENC_CONF8_VAL_422_MUX_ACTIVE 1 +#define AB8500_DENC_CONF8_VAL_422_MUX(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF8, VAL_422_MUX, \ + AB8500_DENC_CONF8_VAL_422_MUX_##__x) +#define AB8500_DENC_CONF8_BLK_ALL_SHIFT 3 +#define AB8500_DENC_CONF8_BLK_ALL_MASK 0x00000008 +#define AB8500_DENC_CONF8_BLK_ALL(__x) \ + AB8500_VAL2REG(AB8500_DENC_CONF8, BLK_ALL, __x) +#define AB8500_TVOUT_CTRL 0x00000680 +#define AB8500_TVOUT_CTRL_TV_LOAD_RC_SHIFT 6 +#define AB8500_TVOUT_CTRL_TV_LOAD_RC_MASK 0x00000040 +#define AB8500_TVOUT_CTRL_TV_LOAD_RC(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL, TV_LOAD_RC, __x) +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_SHIFT 3 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_MASK 0x00000038 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_0_5S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_1S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_1_5S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_2S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_2_5S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_3S 0 +#define AB8500_TVOUT_CTRL_PLUG_TV_TIME(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL, PLUG_TV_TIME, \ + AB8500_TVOUT_CTRL_PLUG_TV_TIME_##__x) +#define AB8500_TVOUT_CTRL_TV_PLUG_ON_SHIFT 2 +#define AB8500_TVOUT_CTRL_TV_PLUG_ON_MASK 0x00000004 +#define AB8500_TVOUT_CTRL_TV_PLUG_ON(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL, TV_PLUG_ON, __x) +#define AB8500_TVOUT_CTRL_DAC_CTRL0_SHIFT 1 +#define AB8500_TVOUT_CTRL_DAC_CTRL0_MASK 0x00000002 +#define AB8500_TVOUT_CTRL_DAC_CTRL0(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL, DAC_CTRL0, __x) +#define AB8500_TVOUT_CTRL_DAC_CTRL1_SHIFT 0 +#define AB8500_TVOUT_CTRL_DAC_CTRL1_MASK 0x00000001 +#define AB8500_TVOUT_CTRL_DAC_CTRL1(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL, DAC_CTRL1, __x) +#define AB8500_TVOUT_CTRL2 0x00000681 +#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN_SHIFT 1 +#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN_MASK 0x00000002 +#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL2, SWAP_DDR_DATA_IN, __x) +#define AB8500_TVOUT_CTRL2_DENC_DDR_SHIFT 0 +#define AB8500_TVOUT_CTRL2_DENC_DDR_MASK 0x00000001 +#define AB8500_TVOUT_CTRL2_DENC_DDR(__x) \ + AB8500_VAL2REG(AB8500_TVOUT_CTRL2, DENC_DDR, __x) +#define AB8500_IT_MASK1 0x00000E40 +#define AB8500_IT_MASK1_PON_KEY1_DBR_SHIFT 7 +#define AB8500_IT_MASK1_PON_KEY1_DBR_MASK 0x00000080 +#define AB8500_IT_MASK1_PON_KEY1_DBR(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY1_DBR, __x) +#define AB8500_IT_MASK1_PON_KEY1_DBF_SHIFT 6 +#define AB8500_IT_MASK1_PON_KEY1_DBF_MASK 0x00000040 +#define AB8500_IT_MASK1_PON_KEY1_DBF(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY1_DBF, __x) +#define AB8500_IT_MASK1_PON_KEY2_DBR_SHIFT 5 +#define AB8500_IT_MASK1_PON_KEY2_DBR_MASK 0x00000020 +#define AB8500_IT_MASK1_PON_KEY2_DBR(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY2_DBR, __x) +#define AB8500_IT_MASK1_PON_KEY2_DBF_SHIFT 4 +#define AB8500_IT_MASK1_PON_KEY2_DBF_MASK 0x00000010 +#define AB8500_IT_MASK1_PON_KEY2_DBF(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY2_DBF, __x) +#define AB8500_IT_MASK1_TEMP_WARN_SHIFT 3 +#define AB8500_IT_MASK1_TEMP_WARN_MASK 0x00000008 +#define AB8500_IT_MASK1_TEMP_WARN(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, TEMP_WARN, __x) +#define AB8500_IT_MASK1_PLUG_TV_DET_SHIFT 2 +#define AB8500_IT_MASK1_PLUG_TV_DET_MASK 0x00000004 +#define AB8500_IT_MASK1_PLUG_TV_DET(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, PLUG_TV_DET, __x) +#define AB8500_IT_MASK1_UNPLUG_TV_DET_SHIFT 1 +#define AB8500_IT_MASK1_UNPLUG_TV_DET_MASK 0x00000002 +#define AB8500_IT_MASK1_UNPLUG_TV_DET(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, UNPLUG_TV_DET, __x) +#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK_SHIFT 0 +#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK_MASK 0x00000001 +#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK(__x) \ + AB8500_VAL2REG(AB8500_IT_MASK1, MAIN_EXT_CH_NOK, __x) +#define AB8500_REV 0x00001080 +#define AB8500_REV_FULL_MASK_SHIFT 4 +#define AB8500_REV_FULL_MASK_MASK 0x000000F0 +#define AB8500_REV_FULL_MASK(__x) \ + AB8500_VAL2REG(AB8500_REV, FULL_MASK, __x) +#define AB8500_REV_METAL_FIX_SHIFT 0 +#define AB8500_REV_METAL_FIX_MASK 0x0000000F +#define AB8500_REV_METAL_FIX(__x) \ + AB8500_VAL2REG(AB8500_REV, METAL_FIX, __x) + +#endif /* __AB8500_DENC_H */ diff --git a/include/linux/mfd/ab8500/denc.h b/include/linux/mfd/ab8500/denc.h new file mode 100644 index 00000000000..25a09a2c2bd --- /dev/null +++ b/include/linux/mfd/ab8500/denc.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * AB8500 tvout driver interface + * + * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __AB8500_DENC__H__ +#define __AB8500_DENC__H__ + +#include <linux/platform_device.h> + +struct ab8500_denc_platform_data { + /* Platform info */ + bool ddr_enable; + bool ddr_little_endian; +}; + +enum ab8500_denc_TV_std { + TV_STD_PAL_BDGHI, + TV_STD_PAL_N, + TV_STD_PAL_M, + TV_STD_NTSC_M, +}; + +enum ab8500_denc_cr_filter_bandwidth { + TV_CR_NTSC_LOW_DEF_FILTER, + TV_CR_PAL_LOW_DEF_FILTER, + TV_CR_NTSC_HIGH_DEF_FILTER, + TV_CR_PAL_HIGH_DEF_FILTER, +}; + +enum ab8500_denc_phase_reset_mode { + TV_PHASE_RST_MOD_DISABLE, + TV_PHASE_RST_MOD_FROM_PHASE_BUF, + TV_PHASE_RST_MOD_FROM_INC_DFS, + TV_PHASE_RST_MOD_RST, +}; + +enum ab8500_denc_plug_time { + TV_PLUG_TIME_0_5S, + TV_PLUG_TIME_1S, + TV_PLUG_TIME_1_5S, + TV_PLUG_TIME_2S, + TV_PLUG_TIME_2_5S, + TV_PLUG_TIME_3S, +}; + +struct ab8500_denc_conf { + /* register settings for DENC_configuration */ + bool act_output; + enum ab8500_denc_TV_std TV_std; + bool progressive; + bool test_pattern; + bool partial_blanking; + bool blank_all; + bool black_level_setup; + enum ab8500_denc_cr_filter_bandwidth cr_filter; + bool suppress_col; + enum ab8500_denc_phase_reset_mode phase_reset_mode; + bool dac_enable; + bool act_dc_output; +}; + +struct platform_device *ab8500_denc_get_device(void); +void ab8500_denc_put_device(struct platform_device *pdev); + +void ab8500_denc_reset(struct platform_device *pdev, bool hard); +void ab8500_denc_power_up(struct platform_device *pdev); +void ab8500_denc_power_down(struct platform_device *pdev); + +void ab8500_denc_conf(struct platform_device *pdev, + struct ab8500_denc_conf *conf); +void ab8500_denc_conf_plug_detect(struct platform_device *pdev, + bool enable, bool load_RC, + enum ab8500_denc_plug_time time); +void ab8500_denc_mask_int_plug_det(struct platform_device *pdev, bool plug, + bool unplug); +#endif /* __AB8500_DENC__H__ */ diff --git a/include/linux/mfd/ab8500/ux500_chargalg.h b/include/linux/mfd/ab8500/ux500_chargalg.h new file mode 100644 index 00000000000..f04e47ff56a --- /dev/null +++ b/include/linux/mfd/ab8500/ux500_chargalg.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _UX500_CHARGALG_H +#define _UX500_CHARGALG_H + +#include <linux/power_supply.h> + +#define psy_to_ux500_charger(x) container_of((x), \ + struct ux500_charger, psy) + +/* Forward declaration */ +struct ux500_charger; + +struct ux500_charger_ops { + int (*enable) (struct ux500_charger *, int, int, int); + int (*kick_wd) (struct ux500_charger *); + int (*update_curr) (struct ux500_charger *, int); +}; + +/** + * struct ux500_charger - power supply ux500 charger sub class + * @psy power supply base class + * @ops ux500 charger operations + * @max_out_volt maximum output charger voltage in mV + * @max_out_curr maximum output charger current in mA + */ +struct ux500_charger { + struct power_supply psy; + struct ux500_charger_ops ops; + int max_out_volt; + int max_out_curr; +}; + +#endif diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h index 9970337ff04..36e61a96cc8 100644 --- a/include/linux/mfd/abx500.h +++ b/include/linux/mfd/abx500.h @@ -1,6 +1,6 @@ /* - * Copyright (C) 2007-2009 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 + * Copyright (C) ST-Ericsson SA 2010 + * License terms: GNU General Public License v2 * AB3100 core access functions * Author: Linus Walleij <linus.walleij@stericsson.com> * @@ -178,6 +178,12 @@ int abx500_get_chip_id(struct device *dev); int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); +#define abx500_get abx500_get_register_interruptible +#define abx500_set abx500_set_register_interruptible +#define abx500_get_page abx500_get_register_page_interruptible +#define abx500_set_page abx500_set_register_page_interruptible +#define abx500_mask_and_set abx500_mask_and_set_register_interruptible + struct abx500_ops { int (*get_chip_id) (struct device *); int (*get_register) (struct device *, u8, u8, u8 *); @@ -189,6 +195,252 @@ struct abx500_ops { int (*startup_irq_enabled) (struct device *, unsigned int); }; -int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops); +/* Battery driver related data */ +/* + * ADC for the battery thermistor. + * When using the ABx500_ADC_THERM_BATCTRL the battery ID resistor is combined + * with a NTC resistor to both identify the battery and to measure its + * temperature. Different phone manufactures uses different techniques to both + * identify the battery and to read its temperature. + */ +enum abx500_adc_therm { + ABx500_ADC_THERM_BATCTRL, + ABx500_ADC_THERM_BATTEMP, +}; + +/** + * struct abx500_res_to_temp - defines one point in a temp to res curve. To + * be used in battery packs that combines the identification resistor with a + * NTC resistor. + * @temp: battery pack temperature in Celcius + * @resist: NTC resistor net total resistance + */ +struct abx500_res_to_temp { + int temp; + int resist; +}; + +/** + * struct abx500_v_to_cap - Table for translating voltage to capacity + * @voltage: Voltage in mV + * @capacity: Capacity in percent + */ +struct abx500_v_to_cap { + int voltage; + int capacity; +}; + +/* Forward declaration */ +struct abx500_fg; + +/** + * struct abx500_fg_parameters - Fuel gauge algorithm parameters, in seconds + * if not specified + * @recovery_sleep_timer: Time between measurements while recovering + * @recovery_total_time: Total recovery time + * @init_timer: Measurement interval during startup + * @init_discard_time: Time we discard voltage measurement at startup + * @init_total_time: Total init time during startup + * @high_curr_time: Time current has to be high to go to recovery + * @accu_charging: FG accumulation time while charging + * @accu_high_curr: FG accumulation time in high current mode + * @high_curr_threshold: High current threshold, in mA + * @lowbat_threshold: Low battery threshold, in mV + * @overbat_threshold: Over battery threshold, in mV + */ +struct abx500_fg_parameters { + int recovery_sleep_timer; + int recovery_total_time; + int init_timer; + int init_discard_time; + int init_total_time; + int high_curr_time; + int accu_charging; + int accu_high_curr; + int high_curr_threshold; + int lowbat_threshold; + int overbat_threshold; +}; + +/** + * struct abx500_charger_maximization - struct used by the board config. + * @use_maxi: Enable maximization for this battery type + * @maxi_chg_curr: Maximum charger current allowed + * @maxi_wait_cycles: cycles to wait before setting charger current + * @charger_curr_step delta between two charger current settings (mA) + */ +struct abx500_maxim_parameters { + bool ena_maxi; + int chg_curr; + int wait_cycles; + int charger_curr_step; +}; + +/** + * struct abx500_battery_type - different batteries supported + * @name: battery technology + * @resis_high: battery upper resistance limit + * @resis_low: battery lower resistance limit + * @charge_full_design: Maximum battery capacity in mAh + * @nominal_voltage: Nominal voltage of the battery in mV + * @termination_vol: max voltage upto which battery can be charged + * @termination_curr battery charging termination current in mA + * @recharge_vol battery voltage limit that will trigger a new + * full charging cycle in the case where maintenan- + * -ce charging has been disabled + * @normal_cur_lvl: charger current in normal state in mA + * @normal_vol_lvl: charger voltage in normal state in mV + * @maint_a_cur_lvl: charger current in maintenance A state in mA + * @maint_a_vol_lvl: charger voltage in maintenance A state in mV + * @maint_a_chg_timer_h: charge time in maintenance A state + * @maint_b_cur_lvl: charger current in maintenance B state in mA + * @maint_b_vol_lvl: charger voltage in maintenance B state in mV + * @maint_b_chg_timer_h: charge time in maintenance B state + * @low_high_cur_lvl: charger current in temp low/high state in mA + * @low_high_vol_lvl: charger voltage in temp low/high state in mV' + * @battery_resistance: battery inner resistance in mOhm. + * @n_r_t_tbl_elements: number of elements in r_to_t_tbl + * @r_to_t_tbl: table containing resistance to temp points + * @n_v_cap_tbl_elements: number of elements in v_to_cap_tbl + * @v_to_cap_tbl: Voltage to capacity (in %) table + */ +struct abx500_battery_type { + int name; + int resis_high; + int resis_low; + int charge_full_design; + int nominal_voltage; + int termination_vol; + int termination_curr; + int recharge_vol; + int normal_cur_lvl; + int normal_vol_lvl; + int maint_a_cur_lvl; + int maint_a_vol_lvl; + int maint_a_chg_timer_h; + int maint_b_cur_lvl; + int maint_b_vol_lvl; + int maint_b_chg_timer_h; + int low_high_cur_lvl; + int low_high_vol_lvl; + int battery_resistance; + int n_temp_tbl_elements; + struct abx500_res_to_temp *r_to_t_tbl; + int n_v_cap_tbl_elements; + struct abx500_v_to_cap *v_to_cap_tbl; +}; + +/** + * struct abx500_bm_capacity_levels - abx500 capacity level data + * @critical: critical capacity level in percent + * @low: low capacity level in percent + * @normal: normal capacity level in percent + * @high: high capacity level in percent + * @full: full capacity level in percent + */ +struct abx500_bm_capacity_levels { + int critical; + int low; + int normal; + int high; + int full; +}; + +/** + * struct abx500_bm_charger_parameters - Charger specific parameters + * @usb_volt_max: maximum allowed USB charger voltage in mV + * @usb_curr_max: maximum allowed USB charger current in mA + * @ac_volt_max: maximum allowed AC charger voltage in mV + * @ac_curr_max: maximum allowed AC charger current in mA + */ +struct abx500_bm_charger_parameters { + int usb_volt_max; + int usb_curr_max; + int ac_volt_max; + int ac_curr_max; +}; + +/** + * struct abx500_bm_data - abx500 battery management data + * @temp_under under this temp, charging is stopped + * @temp_low between this temp and temp_under charging is reduced + * @temp_high between this temp and temp_over charging is reduced + * @temp_over over this temp, charging is stopped + * @main_safety_tmr_h safety timer for main charger + * @usb_safety_tmr_h safety timer for usb charger + * @bkup_bat_v voltage which we charge the backup battery with + * @bkup_bat_i current which we charge the backup battery with + * @no_maintenance indicates that maintenance charging is disabled + * @abx500_adc_therm placement of thermistor, batctrl or battemp adc + * @chg_unknown_bat flag to enable charging of unknown batteries + * @enable_overshoot flag to enable VBAT overshoot control + * @fg_res resistance of FG resistor in 0.1mOhm + * @n_btypes number of elements in array bat_type + * @batt_id index of the identified battery in array bat_type + * @interval_charging charge alg cycle period time when charging (sec) + * @interval_not_charging charge alg cycle period time when not charging (sec) + * @temp_hysteresis temperature hysteresis + * @maxi: maximization parameters + * @cap_levels capacity in percent for the different capacity levels + * @bat_type table of supported battery types + * @chg_params charger parameters + * @fg_params fuel gauge parameters + */ +struct abx500_bm_data { + int temp_under; + int temp_low; + int temp_high; + int temp_over; + int temp_now; + int main_safety_tmr_h; + int usb_safety_tmr_h; + int bkup_bat_v; + int bkup_bat_i; + bool no_maintenance; + bool chg_unknown_bat; + bool enable_overshoot; + enum abx500_adc_therm adc_therm; + int fg_res; + int n_btypes; + int batt_id; + int interval_charging; + int interval_not_charging; + int temp_hysteresis; + const struct abx500_maxim_parameters *maxi; + const struct abx500_bm_capacity_levels *cap_levels; + const struct abx500_battery_type *bat_type; + const struct abx500_bm_charger_parameters *chg_params; + const struct abx500_fg_parameters *fg_params; +}; + +struct abx500_chargalg_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct abx500_charger_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct abx500_btemp_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct abx500_fg_platform_data { + char **supplied_to; + size_t num_supplicants; +}; + +struct abx500_bm_plat_data { + struct abx500_bm_data *battery; + struct abx500_charger_platform_data *charger; + struct abx500_btemp_platform_data *btemp; + struct abx500_fg_platform_data *fg; + struct abx500_chargalg_platform_data *chargalg; +}; + +int abx500_register_ops(struct device *dev, struct abx500_ops *ops); void abx500_remove_ops(struct device *dev); #endif diff --git a/include/linux/mfd/abx500/ab5500-bm.h b/include/linux/mfd/abx500/ab5500-bm.h new file mode 100644 index 00000000000..05ebc8c3840 --- /dev/null +++ b/include/linux/mfd/abx500/ab5500-bm.h @@ -0,0 +1,116 @@ +/* + * Copyright ST-Ericsson 2011. + * + * Author: Arun Murthy <arun.murthy@stericsson.com> + * Licensed under GPLv2. + */ + +#ifndef _AB5500_BM_H +#define _AB5500_BM_H + +#define AB5500_MCB 0x2F +/* + * USB/ULPI register offsets + * Bank : 0x5 + */ +#define AB5500_USB_LINE_STATUS 0x80 +#define AB5500_USB_PHY_STATUS 0x89 +#define AB5500_CHGFSM_CHARGER_DETECT 0xBF +#define AB5500_CHGFSM_USB_BTEMP_CURR_LIM 0xAD +#define AB5500_USB_LINE_CTRL2 0x82 +#define AB5500_USB_OTG_CTRL 0x87 + +/* + * Charger / control register offfsets + * Bank : 0x0B + */ +#define AB5500_CVBUSM 0x11 +#define AB5500_LEDT 0x12 +#define AB5500_VSRC 0x13 +#define AB5500_ICSR 0x14 +#define AB5500_OCSRV 0x15 +#define AB5500_CVREC 0x16 +#define AB5500_CREVS 0x17 +#define AB5500_CCTRL 0x18 +#define AB5500_TBDATA 0x19 +#define AB5500_CPWM 0x1A +#define AB5500_DCIOCURRENT 0x1B +#define AB5500_USB_HS_CURR_LIM 0x1C +#define AB5500_WALL_HS_CURR_LIM 0x1D + +/* + * FG, Battcom and ACC registers offsets + * Bank : 0x0C + */ +#define AB5500_FG_CH0 0x00 +#define AB5500_FG_CH1 0x01 +#define AB5500_FG_CH2 0x02 +#define AB5500_FG_DIS_CH0 0x03 +#define AB5500_FG_DIS_CH1 0x04 +#define AB5500_FG_DIS_CH2 0x05 +#define AB5500_FGDIS_COUNT0 0x06 +#define AB5500_FGDIS_COUNT1 0x07 +#define AB5500_FG_VAL_COUNT0 0x08 +#define AB5500_FG_VAL_COUNT1 0x09 +#define AB5500_FGDIR_READ0 0x0A +#define AB5500_FGDIR_READ1 0x0B +#define AB5500_FG_CONTROL_A 0x0C +#define AB5500_FG_CONTROL_B 0x0F +#define AB5500_FG_CONTROL_C 0x10 +#define AB5500_FG_DIS 0x0D +#define AB5500_FG_EOC 0x0E +#define AB5500_FG_CB 0x0F +#define AB5500_FG_CC 0x10 +#define AB5500_UIOR 0x1A +#define AB5500_UART 0x1B +#define AB5500_URI 0x1C +#define AB5500_UART_RQ 0x1D +#define AB5500_ACC_DETECT1 0x20 +#define AB5500_ACC_DETECT2 0x21 +#define AB5500_ACC_DETECTCTRL 0x23 +#define AB5500_ACC_AVCTRL 0x24 +#define AB5500_ACC_DETECT3_DEG_LITCH_TIME 0x30 +#define AB5500_ACC_DETECT3_KEY_PRESS_TIME 0x31 +#define AB5500_ACC_DETECT3_LONG_KEY_TIME 0x32 +#define AB5500_ACC_DETECT3_TIME_READ_MS 0x33 +#define AB5500_ACC_DETECT3_TIME_READ_LS 0x34 +#define AB5500_ACC_DETECT3_CONTROL 0x35 +#define AB5500_ACC_DETECT3_LEVEL 0x36 +#define AB5500_ACC_DETECT3_TIMER_READ_CTL 0x37 + +/* + * Interrupt register offsets + * Bank : 0x0E + */ +#define AB5500_IT_SOURCE8 0x28 +#define AB5500_IT_SOURCE9 0x29 + +/* BatCtrl Current Source Constants */ +#define BAT_CTRL_7U_ENA (0x01 << 0) +#define BAT_CTRL_15U_ENA (0x01 << 1) +#define BAT_CTRL_30U_ENA (0x01 << 2) +#define BAT_CTRL_60U_ENA (0x01 << 3) +#define BAT_CTRL_120U_ENA (0x01 << 4) +#define BAT_CTRL_CMP_ENA 0x04 +#define FORCE_BAT_CTRL_CMP_HIGH 0x08 +#define BAT_CTRL_PULL_UP_ENA 0x10 + +/* Battery type */ +#define BATTERY_UNKNOWN 0 + +#ifdef CONFIG_AB5500_BM +struct ab5500_btemp *ab5500_btemp_get(void); +int ab5500_btemp_get_batctrl_temp(struct ab5500_btemp *btemp); +void ab5500_fg_reinit(void); +#else +static inline struct ab5500_btemp *ab5500_btemp_get(void) +{ + return 0; +} +static inline int ab5500_btemp_get_batctrl_temp(struct ab5500_btemp *btemp) +{ + return 0; +} +static inline void ab5500_fg_reinit(void) {} +#endif +#endif /* _AB5500_BM_H */ diff --git a/include/linux/mfd/abx500/ab5500-gpadc.h b/include/linux/mfd/abx500/ab5500-gpadc.h new file mode 100644 index 00000000000..67dc3cc9034 --- /dev/null +++ b/include/linux/mfd/abx500/ab5500-gpadc.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010 ST-Ericsson SA + * Licensed under GPLv2. + * + * Author: Vijaya Kumar K <vijay.kilari@stericsson.com> + */ + +#ifndef _AB5500_GPADC_H +#define _AB5500_GPADC_H + +/* + * GPADC source: + * The BTEMP_BALL and PCB_TEMP are same. They differ if the + * battery supports internal NTC resistor connected to BDATA + * line. In this case, the BTEMP_BALL correspondss to BDATA + * of GPADC as per AB5500 product spec. + */ + +#define BTEMP_BALL 0 +#define ACC_DETECT2 1 +#define ACC_DETECT3 2 +#define MAIN_BAT_V 3 +#define MAIN_BAT_V_TXON 4 +#define VBUS_V 5 +#define USB_CHARGER_C 6 +#define BK_BAT_V 7 +#define DIE_TEMP 8 +#define PCB_TEMP 9 +#define XTAL_TEMP 10 +#define USB_ID 11 +#define BAT_CTRL 12 +/* VBAT with TXON only min trigger */ +#define MAIN_BAT_V_TXON_TRIG_MIN 13 +/* VBAT with TX off only min trigger */ +#define MAIN_BAT_V_TRIG_MIN 14 +#define GPADC0_V 15 + +/* + * Frequency of auto adc conversion + */ +#define MS1000 0x0 +#define MS500 0x1 +#define MS200 0x2 +#define MS100 0x3 +#define MS10 0x4 + +struct ab5500_gpadc; + +/* + * struct adc_auto_input - AB5500 GPADC auto trigger + * @adc_mux Mux input + * @freq freq of conversion + * @min min value for trigger + * @max max value for trigger + * @auto_adc_callback notification callback + */ +struct adc_auto_input { + u8 mux; + u8 freq; + int min; + int max; + int (*auto_adc_callback)(int mux); +}; + +struct ab5500_gpadc *ab5500_gpadc_get(const char *name); +int ab5500_gpadc_convert(struct ab5500_gpadc *gpadc, u8 input); +int ab5500_gpadc_convert_auto(struct ab5500_gpadc *gpadc, + struct adc_auto_input *auto_input); + +#endif /* _AB5500_GPADC_H */ diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h index a720051ae93..3dd9f9f7e68 100644 --- a/include/linux/mfd/abx500/ab5500.h +++ b/include/linux/mfd/abx500/ab5500.h @@ -24,6 +24,10 @@ enum ab5500_devid { AB5500_DEVID_VIDEO, AB5500_DEVID_DBIECI, AB5500_DEVID_ONSWA, + AB5500_DEVID_CHARGALG, + AB5500_DEVID_BTEMP, + AB5500_DEVID_TEMPMON, + AB5500_DEVID_ACCDET, AB5500_NUM_DEVICES, }; @@ -92,8 +96,9 @@ enum ab5500_banks_addr { #define AB5500_IT_SOURCE21_REG 0x35 #define AB5500_IT_SOURCE22_REG 0x36 #define AB5500_IT_SOURCE23_REG 0x37 +#define AB5500_IT_SOURCE24_REG 0x38 -#define AB5500_NUM_IRQ_REGS 23 +#define AB5500_NUM_IRQ_REGS 25 /** * struct ab5500 @@ -118,6 +123,7 @@ struct ab5500 { char chip_name[32]; u8 chip_id; struct mutex irq_lock; + u32 num_event_reg; u32 abb_events; u8 mask[AB5500_NUM_IRQ_REGS]; u8 oldmask[AB5500_NUM_IRQ_REGS]; @@ -129,12 +135,31 @@ struct ab5500 { #endif }; +#ifndef CONFIG_AB5500_CORE +static inline int ab5500_clock_rtc_enable(int num, bool enable) +{ + return -ENOSYS; +} +#else +extern int ab5500_clock_rtc_enable(int num, bool enable); +#endif + +/* Forward Declaration */ +struct ab5500_regulator_platform_data; + struct ab5500_platform_data { struct {unsigned int base; unsigned int count; } irq; void *dev_data[AB5500_NUM_DEVICES]; + size_t dev_data_sz[AB5500_NUM_DEVICES]; struct abx500_init_settings *init_settings; unsigned int init_settings_sz; bool pm_power_off; + struct ab5500_regulator_platform_data *regulator; + struct ab5500_usbgpio_platform_data *usb; + struct abx500_accdet_platform_data *accdet; }; +struct ab5500_ponkey_platform_data { + u8 shutdown_secs; +}; #endif /* MFD_AB5500_H */ diff --git a/include/linux/mfd/abx500/ab8500-gpadc.h b/include/linux/mfd/abx500/ab8500-gpadc.h index 252966769d9..fa706c5a04a 100644 --- a/include/linux/mfd/abx500/ab8500-gpadc.h +++ b/include/linux/mfd/abx500/ab8500-gpadc.h @@ -26,7 +26,7 @@ struct ab8500_gpadc; -struct ab8500_gpadc *ab8500_gpadc_get(char *name); +struct ab8500_gpadc *ab8500_gpadc_get(void); int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel); int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel); int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h index 488a8c920a2..d88e3025317 100644 --- a/include/linux/mfd/abx500/ab8500-gpio.h +++ b/include/linux/mfd/abx500/ab8500-gpio.h @@ -8,6 +8,8 @@ #ifndef _AB8500_GPIO_H #define _AB8500_GPIO_H +#include <mach/gpio.h> + /* * Platform data to register a block: only the initial gpio/irq number. */ @@ -16,6 +18,62 @@ struct ab8500_gpio_platform_data { int gpio_base; u32 irq_base; u8 config_reg[7]; + u8 config_direction[6]; + u8 config_pullups[6]; +}; + +enum ab8500_pin { + AB8500_PIN_GPIO1 = AB8500_GPIO_BASE, + AB8500_PIN_GPIO2, + AB8500_PIN_GPIO3, + AB8500_PIN_GPIO4, + AB8500_PIN_GPIO5, + AB8500_PIN_GPIO6, + AB8500_PIN_GPIO7, + AB8500_PIN_GPIO8, + AB8500_PIN_GPIO9, + AB8500_PIN_GPIO10, + AB8500_PIN_GPIO11, + AB8500_PIN_GPIO12, + AB8500_PIN_GPIO13, + AB8500_PIN_GPIO14, + AB8500_PIN_GPIO15, + AB8500_PIN_GPIO16, + AB8500_PIN_GPIO17, + AB8500_PIN_GPIO18, + AB8500_PIN_GPIO19, + AB8500_PIN_GPIO20, + AB8500_PIN_GPIO21, + AB8500_PIN_GPIO22, + AB8500_PIN_GPIO23, + AB8500_PIN_GPIO24, + AB8500_PIN_GPIO25, + AB8500_PIN_GPIO26, + AB8500_PIN_GPIO27, + AB8500_PIN_GPIO28, + AB8500_PIN_GPIO29, + AB8500_PIN_GPIO30, + AB8500_PIN_GPIO31, + AB8500_PIN_GPIO32, + AB8500_PIN_GPIO33, + AB8500_PIN_GPIO34, + AB8500_PIN_GPIO35, + AB8500_PIN_GPIO36, + AB8500_PIN_GPIO37, + AB8500_PIN_GPIO38, + AB8500_PIN_GPIO39, + AB8500_PIN_GPIO40, + AB8500_PIN_GPIO41, + AB8500_PIN_GPIO42, }; +int ab8500_config_pulldown(struct device *dev, + enum ab8500_pin gpio, bool enable); + +int ab8500_gpio_config_select(struct device *dev, + enum ab8500_pin gpio, bool gpio_select); + +int ab8500_gpio_config_get_select(struct device *dev, + enum ab8500_pin gpio, bool *gpio_select); + #endif /* _AB8500_GPIO_H */ diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h index 10da0291f8f..504725bebfe 100644 --- a/include/linux/mfd/abx500/ab8500-sysctrl.h +++ b/include/linux/mfd/abx500/ab8500-sysctrl.h @@ -37,6 +37,11 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) return ab8500_sysctrl_write(reg, bits, 0); } +/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */ +struct ab8500_sysctrl_platform_data { + u8 initial_req_buf_config[8]; +}; + /* Registers */ #define AB8500_TURNONSTATUS 0x100 #define AB8500_RESETSTATUS 0x101 diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h index 838c6b487cc..d3a50db5003 100644 --- a/include/linux/mfd/abx500/ab8500.h +++ b/include/linux/mfd/abx500/ab8500.h @@ -157,7 +157,6 @@ struct ab8500 { struct device *dev; struct mutex lock; struct mutex irq_lock; - int irq_base; int irq; u8 chip_id; @@ -172,27 +171,46 @@ struct ab8500 { u8 oldmask[AB8500_NUM_IRQ_REGS]; }; -struct regulator_reg_init; -struct regulator_init_data; +struct ab8500_regulator_platform_data; +struct ab8500_accdet_platform_data; +struct ab8500_denc_platform_data; +struct ab8500_audio_platform_data; struct ab8500_gpio_platform_data; +struct ab8500_sysctrl_platform_data; /** * struct ab8500_platform_data - AB8500 platform data + * @pm_power_off: Should machine pm power off hook be registered or not + * @thermal_power_off_pending: Set if there was a thermal alarm + * @thermal_set_time_sec: Time of the thermal alarm + * @thermal_time_out: Time out before the thermal alarm should be ignored * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used * @init: board-specific initialization after detection of ab8500 - * @num_regulator_reg_init: number of regulator init registers - * @regulator_reg_init: regulator init registers - * @num_regulator: number of regulators * @regulator: machine-specific constraints for regulators + * @accdet: machine-specific Accessory detection data + * @battery: machine-specific battery management data + * @charger: machine-specific charger data + * @btemp: machine-specific battery temp data */ struct ab8500_platform_data { int irq_base; + bool pm_power_off; + bool thermal_power_off_pending; + long thermal_set_time_sec; + long thermal_time_out; void (*init) (struct ab8500 *); - int num_regulator_reg_init; - struct ab8500_regulator_reg_init *regulator_reg_init; - int num_regulator; - struct regulator_init_data *regulator; + struct ab8500_regulator_platform_data *regulator; + struct abx500_accdet_platform_data *accdet; + struct ab8500_bm_data *battery; + struct ab8500_denc_platform_data *denc; + struct ab8500_audio_platform_data *audio; + struct ab8500_charger_platform_data *charger; + struct ab8500_btemp_platform_data *btemp; + struct ab8500_fg_platform_data *fg; + struct ab8500_chargalg_platform_data *chargalg; struct ab8500_gpio_platform_data *gpio; + struct ab8500_sysctrl_platform_data *sysctrl; + struct abx500_usbgpio_platform_data *usb; }; extern int __devinit ab8500_init(struct ab8500 *ab8500); diff --git a/include/linux/mfd/abx500/ux500_chargalg.h b/include/linux/mfd/abx500/ux500_chargalg.h new file mode 100644 index 00000000000..f04e47ff56a --- /dev/null +++ b/include/linux/mfd/abx500/ux500_chargalg.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _UX500_CHARGALG_H +#define _UX500_CHARGALG_H + +#include <linux/power_supply.h> + +#define psy_to_ux500_charger(x) container_of((x), \ + struct ux500_charger, psy) + +/* Forward declaration */ +struct ux500_charger; + +struct ux500_charger_ops { + int (*enable) (struct ux500_charger *, int, int, int); + int (*kick_wd) (struct ux500_charger *); + int (*update_curr) (struct ux500_charger *, int); +}; + +/** + * struct ux500_charger - power supply ux500 charger sub class + * @psy power supply base class + * @ops ux500 charger operations + * @max_out_volt maximum output charger voltage in mV + * @max_out_curr maximum output charger current in mA + */ +struct ux500_charger { + struct power_supply psy; + struct ux500_charger_ops ops; + int max_out_volt; + int max_out_curr; +}; + +#endif diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h index 9890687f582..681c8f99bf1 100644 --- a/include/linux/mfd/db5500-prcmu.h +++ b/include/linux/mfd/db5500-prcmu.h @@ -24,12 +24,53 @@ void db5500_prcmu_get_abb_event_buffer(void __iomem **buf); int prcmu_resetout(u8 resoutn, u8 state); int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +u8 db5500_prcmu_get_power_state_result(void); int db5500_prcmu_config_esram0_deep_sleep(u8 state); void db5500_prcmu_system_reset(u16 reset_code); u16 db5500_prcmu_get_reset_code(void); -bool db5500_prcmu_is_ac_wake_requested(void); +#ifdef CONFIG_UX500_SOC_DB5500 +void prcmu_modem_req(void); +void prcmu_modem_rel(void); +void prcmu_ape_ack(void); +#endif +bool db5500_prcmu_is_modem_requested(void); +void db5500_prcmu_modem_reset(void); int db5500_prcmu_set_arm_opp(u8 opp); int db5500_prcmu_get_arm_opp(void); +int db5500_prcmu_set_ape_opp(u8 opp); +int db5500_prcmu_get_ape_opp(void); +int db5500_prcmu_set_ddr_opp(u8 opp); +int db5500_prcmu_get_ddr_opp(void); + +u32 db5500_prcmu_read(unsigned int reg); +void db5500_prcmu_write(unsigned int reg, u32 value); +void db5500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); + +static inline unsigned long prcmu_clock_rate(u8 clock) +{ + return 0; +} + +static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} +int db5500_prcmu_get_hotdog(void); +int db5500_prcmu_config_hotdog(u8 threshold); +int db5500_prcmu_config_hotmon(u8 low, u8 high); +int db5500_prcmu_start_temp_sense(u16 cycles32k); +int db5500_prcmu_stop_temp_sense(void); + +int db5500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off); +int db5500_prcmu_enable_a9wdog(u8 id); +int db5500_prcmu_disable_a9wdog(u8 id); +int db5500_prcmu_kick_a9wdog(u8 id); +int db5500_prcmu_load_a9wdog(u8 id, u32 timeout); #else /* !CONFIG_UX500_SOC_DB5500 */ @@ -50,6 +91,11 @@ static inline int db5500_prcmu_request_clock(u8 clock, bool enable) return 0; } +static inline unsigned long db5500_prcmu_clock_rate(u8 clock) +{ + return 0; +} + static inline int db5500_prcmu_set_display_clocks(void) { return 0; @@ -72,6 +118,16 @@ static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} +static inline long db5500_prcmu_round_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline int db5500_prcmu_set_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + static inline int prcmu_resetout(u8 resoutn, u8 state) { return 0; @@ -91,6 +147,11 @@ static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, return 0; } +static inline u8 db5500_prcmu_get_power_state_result(void) +{ + return 0; +} + static inline void db5500_prcmu_system_reset(u16 reset_code) {} static inline u16 db5500_prcmu_get_reset_code(void) @@ -98,11 +159,18 @@ static inline u16 db5500_prcmu_get_reset_code(void) return 0; } -static inline bool db5500_prcmu_is_ac_wake_requested(void) +static inline void db5500_prcmu_modem_reset(void) {} +static inline bool db5500_prcmu_is_modem_requested(void) { return 0; } +#ifdef CONFIG_UX500_SOC_DB5500 +static void prcmu_ape_ack(void) {} +static void prcmu_modem_req(void) {} +static void prcmu_modem_rel(void) {} +#endif + static inline int db5500_prcmu_set_arm_opp(u8 opp) { return 0; @@ -113,6 +181,83 @@ static inline int db5500_prcmu_get_arm_opp(void) return 0; } +static inline int db5500_prcmu_set_ape_opp(u8 opp) +{ + return 0; +} + +static inline int db5500_prcmu_get_ape_opp(void) +{ + return 0; +} + +static inline int db5500_prcmu_set_ddr_opp(u8 opp) +{ + return 0; +} + +static inline int db5500_prcmu_get_ddr_opp(void) +{ + return 0; +} + +static inline u32 db5500_prcmu_read(unsigned int reg) +{ + return 0; +} + +static inline void db5500_prcmu_write(unsigned int reg, u32 value) {} + +static inline void db5500_prcmu_write_masked(unsigned int reg, u32 mask, + u32 value) {} + +static inline int db5500_prcmu_get_hotdog(void) +{ + return -ENOSYS; +} +static inline int db5500_prcmu_config_hotdog(u8 threshold) +{ + return 0; +} + +static inline int db5500_prcmu_config_hotmon(u8 low, u8 high) +{ + return 0; +} + +static inline int db5500_prcmu_start_temp_sense(u16 cycles32k) +{ + return 0; +} +static inline int db5500_prcmu_stop_temp_sense(void) +{ + return 0; +} + +static inline int db5500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) +{ + return 0; +} + +static inline int db5500_prcmu_enable_a9wdog(u8 id) +{ + return 0; +} + +static inline int db5500_prcmu_disable_a9wdog(u8 id) +{ + return 0; +} + +static inline int db5500_prcmu_kick_a9wdog(u8 id) +{ + return 0; +} + +static inline int db5500_prcmu_load_a9wdog(u8 id, u32 timeout) +{ + return 0; +} #endif /* CONFIG_MFD_DB5500_PRCMU */ diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 60d27f7bfc1..260537fbc54 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -11,6 +11,24 @@ #define __MFD_DB8500_PRCMU_H #include <linux/interrupt.h> +#include <linux/bitops.h> + +/* + * Registers + */ +#define DB8500_PRCM_GPIOCR 0x138 +#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0) +#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9) +#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11) +#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23) + +#define DB8500_PRCM_LINE_VALUE 0x170 +#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3) + +#define DB8500_PRCM_DSI_SW_RESET 0x324 +#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0) +#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1) +#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2) /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ @@ -163,84 +181,6 @@ enum hw_acc_state { }; /** - * enum mbox_2_arm_stat - Status messages definition for mbox_arm - * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been - * completed - * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been - * completed - * @SLEEPOK: The apExecute to apSleep state transition has been completed - * @IDLEOK: The apExecute to apIdle state transition has been completed - * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed - * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going - * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going - * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on - * going - * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on - * going - * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has - * been completed - * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going - * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going - * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been - * completed - * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going - * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going - * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been - * completed - * @INIT_STATUS: Status init - */ -enum ap_pwrsttr_status { - BOOT_TO_EXECUTEOK = 0xFF, - DEEPSLEEPOK = 0xFE, - SLEEPOK = 0xFD, - IDLEOK = 0xFC, - SOFTRESETOK = 0xFB, - SOFTRESETGO = 0xFA, - BOOT_TO_EXECUTE = 0xF9, - EXECUTE_TO_DEEPSLEEP = 0xF8, - DEEPSLEEP_TO_EXECUTE = 0xF7, - DEEPSLEEP_TO_EXECUTEOK = 0xF6, - EXECUTE_TO_SLEEP = 0xF5, - SLEEP_TO_EXECUTE = 0xF4, - SLEEP_TO_EXECUTEOK = 0xF3, - EXECUTE_TO_IDLE = 0xF2, - IDLE_TO_EXECUTE = 0xF1, - IDLE_TO_EXECUTEOK = 0xF0, - RDYTODS_RETURNTOEXE = 0xEF, - NORDYTODS_RETURNTOEXE = 0xEE, - EXETOSLEEP_RETURNTOEXE = 0xED, - EXETOIDLE_RETURNTOEXE = 0xEC, - INIT_STATUS = 0xEB, - - /*error messages */ - INITERROR = 0x00, - PLLARMLOCKP_ER = 0x01, - PLLDDRLOCKP_ER = 0x02, - PLLSOCLOCKP_ER = 0x03, - PLLSOCK1LOCKP_ER = 0x04, - ARMWFI_ER = 0x05, - SYSCLKOK_ER = 0x06, - I2C_NACK_DATA_ER = 0x07, - BOOT_ER = 0x08, - I2C_STATUS_ALWAYS_1 = 0x0A, - I2C_NACK_REG_ADDR_ER = 0x0B, - I2C_NACK_DATA0123_ER = 0x1B, - I2C_NACK_ADDR_ER = 0x1F, - CURAPPWRSTISNOT_BOOT = 0x20, - CURAPPWRSTISNOT_EXECUTE = 0x21, - CURAPPWRSTISNOT_SLEEPMODE = 0x22, - CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, - FIFO4500WUISNOT_WUPEVENT = 0x24, - PLL32KLOCKP_ER = 0x29, - DDRDEEPSLEEPOK_ER = 0x2A, - ROMCODEREADY_ER = 0x50, - WUPBEFOREDS = 0x51, - DDRCONFIG_ER = 0x52, - WUPBEFORESLEEP = 0x53, - WUPBEFOREIDLE = 0x54 -}; /* earlier called as mbox_2_arm_stat */ - -/** * enum dvfs_stat - DVFS status messages definition * @DVFS_GO: A state transition DVFS is on going * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP @@ -457,6 +397,25 @@ enum hw_acc_dev { NUM_HW_ACC }; +/** + * enum prcmu_power_status - results from set_power_state + * @PRCMU_SLEEP_OK: Sleep went ok + * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok + * @PRCMU_IDLE_OK: Idle went ok + * @PRCMU_DEEPIDLE_OK: DeepIdle went ok + * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected + * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected + * + */ +enum prcmu_power_status { + PRCMU_SLEEP_OK = 0xf3, + PRCMU_DEEP_SLEEP_OK = 0xf6, + PRCMU_IDLE_OK = 0xf0, + PRCMU_DEEPIDLE_OK = 0xe3, + PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91, + PRCMU_ARMPENDINGIT_ER = 0x93, +}; + /* * Definitions for autonomous power management configuration. */ @@ -493,6 +452,18 @@ struct prcmu_auto_pm_config { u8 sva_policy; }; +#define PRCMU_FW_PROJECT_U8500 2 +#define PRCMU_FW_PROJECT_U9500 4 +#define PRCMU_FW_PROJECT_U8500_C2 7 +#define PRCMU_FW_PROJECT_U9500_C2 11 + +struct prcmu_fw_version { + u8 project; + u8 api_version; + u8 func_version; + u8 errata; +}; + #ifdef CONFIG_MFD_DB8500_PRCMU void db8500_prcmu_early_init(void); @@ -500,42 +471,36 @@ int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); bool prcmu_has_arm_maxopp(void); -bool prcmu_is_u8400(void); -int prcmu_set_ape_opp(u8 opp); -int prcmu_get_ape_opp(void); +struct prcmu_fw_version *prcmu_get_fw_version(void); int prcmu_request_ape_opp_100_voltage(bool enable); int prcmu_release_usb_wakeup_state(void); -int prcmu_set_ddr_opp(u8 opp); -int prcmu_get_ddr_opp(void); /* NOTE! Use regulator framework instead */ int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle); bool prcmu_is_auto_pm_enabled(void); -int prcmu_config_clkout(u8 clkout, u8 source, u8 div); -int prcmu_set_clock_divider(u8 clock, u8 divider); -int prcmu_config_hotdog(u8 threshold); -int prcmu_config_hotmon(u8 low, u8 high); -int prcmu_start_temp_sense(u16 cycles32k); -int prcmu_stop_temp_sense(void); + +int db8500_prcmu_config_hotdog(u8 threshold); +int db8500_prcmu_config_hotmon(u8 low, u8 high); +int db8500_prcmu_start_temp_sense(u16 cycles32k); +int db8500_prcmu_stop_temp_sense(void); int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_modem_reset(void); -void prcmu_enable_spi2(void); -void prcmu_disable_spi2(void); +void db8500_prcmu_modem_reset(void); -int prcmu_config_a9wdog(u8 num, bool sleep_auto_off); -int prcmu_enable_a9wdog(u8 id); -int prcmu_disable_a9wdog(u8 id); -int prcmu_kick_a9wdog(u8 id); -int prcmu_load_a9wdog(u8 id, u32 val); +int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off); +int db8500_prcmu_enable_a9wdog(u8 id); +int db8500_prcmu_disable_a9wdog(u8 id); +int db8500_prcmu_kick_a9wdog(u8 id); +int db8500_prcmu_load_a9wdog(u8 id, u32 val); void db8500_prcmu_system_reset(u16 reset_code); int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +u8 db8500_prcmu_get_power_state_result(void); void db8500_prcmu_enable_wakeups(u32 wakeups); int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); int db8500_prcmu_request_clock(u8 clock, bool enable); @@ -549,6 +514,14 @@ u16 db8500_prcmu_get_reset_code(void); bool db8500_prcmu_is_ac_wake_requested(void); int db8500_prcmu_set_arm_opp(u8 opp); int db8500_prcmu_get_arm_opp(void); +int db8500_prcmu_set_ape_opp(u8 opp); +int db8500_prcmu_get_ape_opp(void); +int db8500_prcmu_set_ddr_opp(u8 opp); +int db8500_prcmu_get_ddr_opp(void); + +u32 db8500_prcmu_read(unsigned int reg); +void db8500_prcmu_write(unsigned int reg, u32 value); +void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); #else /* !CONFIG_MFD_DB8500_PRCMU */ @@ -574,17 +547,17 @@ static inline bool prcmu_has_arm_maxopp(void) return false; } -static inline bool prcmu_is_u8400(void) +static inline struct prcmu_fw_version *prcmu_get_fw_version(void) { - return false; + return NULL; } -static inline int prcmu_set_ape_opp(u8 opp) +static inline int db8500_prcmu_set_ape_opp(u8 opp) { return 0; } -static inline int prcmu_get_ape_opp(void) +static inline int db8500_prcmu_get_ape_opp(void) { return APE_100_OPP; } @@ -599,12 +572,12 @@ static inline int prcmu_release_usb_wakeup_state(void) return 0; } -static inline int prcmu_set_ddr_opp(u8 opp) +static inline int db8500_prcmu_set_ddr_opp(u8 opp) { return 0; } -static inline int prcmu_get_ddr_opp(void) +static inline int db8500_prcmu_get_ddr_opp(void) { return DDR_100_OPP; } @@ -613,7 +586,6 @@ static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) { return 0; } - static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle) { @@ -624,32 +596,22 @@ static inline bool prcmu_is_auto_pm_enabled(void) return false; } -static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) -{ - return 0; -} - -static inline int prcmu_set_clock_divider(u8 clock, u8 divider) -{ - return 0; -} - -static inline int prcmu_config_hotdog(u8 threshold) +static inline int db8500_prcmu_config_hotdog(u8 threshold) { return 0; } -static inline int prcmu_config_hotmon(u8 low, u8 high) +static inline int db8500_prcmu_config_hotmon(u8 low, u8 high) { return 0; } -static inline int prcmu_start_temp_sense(u16 cycles32k) +static inline int db8500_prcmu_start_temp_sense(u16 cycles32k) { return 0; } -static inline int prcmu_stop_temp_sense(void) +static inline int db8500_prcmu_stop_temp_sense(void) { return 0; } @@ -668,22 +630,17 @@ static inline void prcmu_ac_wake_req(void) {} static inline void prcmu_ac_sleep_req(void) {} -static inline void prcmu_modem_reset(void) {} +static inline void db8500_prcmu_modem_reset(void) {} -static inline int prcmu_enable_spi2(void) -{ - return 0; -} +static inline void db8500_prcmu_system_reset(u16 reset_code) {} -static inline int prcmu_disable_spi2(void) +static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) { return 0; } -static inline void db8500_prcmu_system_reset(u16 reset_code) {} - -static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) +static inline u8 db8500_prcmu_get_power_state_result(void) { return 0; } @@ -729,27 +686,27 @@ static inline u16 db8500_prcmu_get_reset_code(void) return 0; } -static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) +static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) { return 0; } -static inline int prcmu_enable_a9wdog(u8 id) +static inline int db8500_prcmu_enable_a9wdog(u8 id) { return 0; } -static inline int prcmu_disable_a9wdog(u8 id) +static inline int db8500_prcmu_disable_a9wdog(u8 id) { return 0; } -static inline int prcmu_kick_a9wdog(u8 id) +static inline int db8500_prcmu_kick_a9wdog(u8 id) { return 0; } -static inline int prcmu_load_a9wdog(u8 id, u32 val) +static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val) { return 0; } @@ -769,6 +726,16 @@ static inline int db8500_prcmu_get_arm_opp(void) return 0; } +static inline u32 db8500_prcmu_read(unsigned int reg) +{ + return 0; +} + +static inline void db8500_prcmu_write(unsigned int reg, u32 value) {} + +static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask, + u32 value) {} + #endif /* !CONFIG_MFD_DB8500_PRCMU */ #endif /* __MFD_DB8500_PRCMU_H */ diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index bac942f959c..e99fecda5f6 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -10,7 +10,7 @@ #include <linux/interrupt.h> #include <linux/notifier.h> -#include <asm/mach-types.h> +#include <linux/err.h> /* PRCMU Wakeup defines */ enum prcmu_wakeup_index { @@ -80,6 +80,29 @@ enum prcmu_wakeup_index { #define EPOD_STATE_ON_CLK_OFF 0x03 #define EPOD_STATE_ON 0x04 +/* DB5500 CLKOUT IDs */ +enum { + DB5500_CLKOUT0 = 0, + DB5500_CLKOUT1, +}; + +/* DB5500 CLKOUTx sources */ +enum { + DB5500_CLKOUT_REF_CLK_SEL0, + DB5500_CLKOUT_RTC_CLK0_SEL0, + DB5500_CLKOUT_ULP_CLK_SEL0, + DB5500_CLKOUT_STATIC0, + DB5500_CLKOUT_REFCLK, + DB5500_CLKOUT_ULPCLK, + DB5500_CLKOUT_ARMCLK, + DB5500_CLKOUT_SYSACC0CLK, + DB5500_CLKOUT_SOC0PLLCLK, + DB5500_CLKOUT_SOC1PLLCLK, + DB5500_CLKOUT_DDRPLLCLK, + DB5500_CLKOUT_TVCLK, + DB5500_CLKOUT_IRDACLK, +}; + /* * CLKOUT sources */ @@ -111,6 +134,7 @@ enum prcmu_clock { PRCMU_MSP1CLK, PRCMU_I2CCLK, PRCMU_SDMMCCLK, + PRCMU_SPARE1CLK, PRCMU_SLIMCLK, PRCMU_PER1CLK, PRCMU_PER2CLK, @@ -139,12 +163,20 @@ enum prcmu_clock { PRCMU_IRRCCLK, PRCMU_SIACLK, PRCMU_SVACLK, + PRCMU_ACLK, PRCMU_NUM_REG_CLOCKS, PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, + PRCMU_CDCLK, PRCMU_TIMCLK, PRCMU_PLLSOC0, PRCMU_PLLSOC1, PRCMU_PLLDDR, + PRCMU_PLLDSI, + PRCMU_DSI0CLK, + PRCMU_DSI1CLK, + PRCMU_DSI0ESCCLK, + PRCMU_DSI1ESCCLK, + PRCMU_DSI2ESCCLK, }; /** @@ -153,12 +185,14 @@ enum prcmu_clock { * @APE_NO_CHANGE: The APE operating point is unchanged * @APE_100_OPP: The new APE operating point is ape100opp * @APE_50_OPP: 50% + * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. */ enum ape_opp { APE_OPP_INIT = 0x00, APE_NO_CHANGE = 0x01, APE_100_OPP = 0x02, - APE_50_OPP = 0x03 + APE_50_OPP = 0x03, + APE_50_PARTLY_25_OPP = 0xFF, }; /** @@ -218,9 +252,11 @@ enum ddr_pwrst { #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) +#include <mach/id.h> + static inline void __init prcmu_early_init(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_early_init(); else return db8500_prcmu_early_init(); @@ -229,7 +265,7 @@ static inline void __init prcmu_early_init(void) static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_set_power_state(state, keep_ulp_clk, keep_ap_pll); else @@ -237,17 +273,25 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, keep_ap_pll); } +static inline u8 prcmu_get_power_state_result(void) +{ + if (cpu_is_u5500()) + return db5500_prcmu_get_power_state_result(); + else + return db8500_prcmu_get_power_state_result(); +} + static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { - if (machine_is_u5500()) - return -EINVAL; + if (cpu_is_u5500()) + return db5500_prcmu_set_epod(epod_id, epod_state); else return db8500_prcmu_set_epod(epod_id, epod_state); } static inline void prcmu_enable_wakeups(u32 wakeups) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_enable_wakeups(wakeups); else db8500_prcmu_enable_wakeups(wakeups); @@ -260,7 +304,7 @@ static inline void prcmu_disable_wakeups(void) static inline void prcmu_config_abb_event_readout(u32 abb_events) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_config_abb_event_readout(abb_events); else db8500_prcmu_config_abb_event_readout(abb_events); @@ -268,7 +312,7 @@ static inline void prcmu_config_abb_event_readout(u32 abb_events) static inline void prcmu_get_abb_event_buffer(void __iomem **buf) { - if (machine_is_u5500()) + if (cpu_is_u5500()) db5500_prcmu_get_abb_event_buffer(buf); else db8500_prcmu_get_abb_event_buffer(buf); @@ -281,36 +325,66 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div); static inline int prcmu_request_clock(u8 clock, bool enable) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_request_clock(clock, enable); else return db8500_prcmu_request_clock(clock, enable); } -int prcmu_set_ape_opp(u8 opp); -int prcmu_get_ape_opp(void); -int prcmu_set_ddr_opp(u8 opp); -int prcmu_get_ddr_opp(void); +unsigned long prcmu_clock_rate(u8 clock); +long prcmu_round_clock_rate(u8 clock, unsigned long rate); +int prcmu_set_clock_rate(u8 clock, unsigned long rate); + +static inline int prcmu_set_ddr_opp(u8 opp) +{ + if (cpu_is_u5500()) + return db5500_prcmu_set_ddr_opp(opp); + else + return db8500_prcmu_set_ddr_opp(opp); +} +static inline int prcmu_get_ddr_opp(void) +{ + if (cpu_is_u5500()) + return db5500_prcmu_get_ddr_opp(); + else + return db8500_prcmu_get_ddr_opp(); +} static inline int prcmu_set_arm_opp(u8 opp) { - if (machine_is_u5500()) - return -EINVAL; + if (cpu_is_u5500()) + return db5500_prcmu_set_arm_opp(opp); else return db8500_prcmu_set_arm_opp(opp); } static inline int prcmu_get_arm_opp(void) { - if (machine_is_u5500()) - return -EINVAL; + if (cpu_is_u5500()) + return db5500_prcmu_get_arm_opp(); else return db8500_prcmu_get_arm_opp(); } +static inline int prcmu_set_ape_opp(u8 opp) +{ + if (cpu_is_u5500()) + return db5500_prcmu_set_ape_opp(opp); + else + return db8500_prcmu_set_ape_opp(opp); +} + +static inline int prcmu_get_ape_opp(void) +{ + if (cpu_is_u5500()) + return db5500_prcmu_get_ape_opp(); + else + return db8500_prcmu_get_ape_opp(); +} + static inline void prcmu_system_reset(u16 reset_code) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_system_reset(reset_code); else return db8500_prcmu_system_reset(reset_code); @@ -318,7 +392,7 @@ static inline void prcmu_system_reset(u16 reset_code) static inline u16 prcmu_get_reset_code(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_get_reset_code(); else return db8500_prcmu_get_reset_code(); @@ -326,18 +400,25 @@ static inline u16 prcmu_get_reset_code(void) void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_modem_reset(void); +static inline void prcmu_modem_reset(void) +{ + if (cpu_is_u5500()) + return db5500_prcmu_modem_reset(); + else + return db8500_prcmu_modem_reset(); +} + static inline bool prcmu_is_ac_wake_requested(void) { - if (machine_is_u5500()) - return db5500_prcmu_is_ac_wake_requested(); + if (cpu_is_u5500()) + return db5500_prcmu_is_modem_requested(); else return db8500_prcmu_is_ac_wake_requested(); } static inline int prcmu_set_display_clocks(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_set_display_clocks(); else return db8500_prcmu_set_display_clocks(); @@ -345,7 +426,7 @@ static inline int prcmu_set_display_clocks(void) static inline int prcmu_disable_dsipll(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_disable_dsipll(); else return db8500_prcmu_disable_dsipll(); @@ -353,7 +434,7 @@ static inline int prcmu_disable_dsipll(void) static inline int prcmu_enable_dsipll(void) { - if (machine_is_u5500()) + if (cpu_is_u5500()) return db5500_prcmu_enable_dsipll(); else return db8500_prcmu_enable_dsipll(); @@ -361,11 +442,107 @@ static inline int prcmu_enable_dsipll(void) static inline int prcmu_config_esram0_deep_sleep(u8 state) { - if (machine_is_u5500()) - return -EINVAL; + if (cpu_is_u5500()) + return db5500_prcmu_config_esram0_deep_sleep(state); else return db8500_prcmu_config_esram0_deep_sleep(state); } + +static inline int prcmu_config_hotdog(u8 threshold) +{ + if (cpu_is_u5500()) + return db5500_prcmu_config_hotdog(threshold); + else + return db8500_prcmu_config_hotdog(threshold); +} + +static inline int prcmu_config_hotmon(u8 low, u8 high) +{ + if (cpu_is_u5500()) + return db5500_prcmu_config_hotmon(low, high); + else + return db8500_prcmu_config_hotmon(low, high); +} + +static inline int prcmu_start_temp_sense(u16 cycles32k) +{ + if (cpu_is_u5500()) + return db5500_prcmu_start_temp_sense(cycles32k); + else + return db8500_prcmu_start_temp_sense(cycles32k); +} + +static inline int prcmu_stop_temp_sense(void) +{ + if (cpu_is_u5500()) + return db5500_prcmu_stop_temp_sense(); + else + return db8500_prcmu_stop_temp_sense(); +} + +static inline u32 prcmu_read(unsigned int reg) +{ + if (cpu_is_u5500()) + return db5500_prcmu_read(reg); + else + return db8500_prcmu_read(reg); +} + +static inline void prcmu_write(unsigned int reg, u32 value) +{ + if (cpu_is_u5500()) + db5500_prcmu_write(reg, value); + else + db8500_prcmu_write(reg, value); +} + +static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) +{ + if (cpu_is_u5500()) + db5500_prcmu_write_masked(reg, mask, value); + else + db8500_prcmu_write_masked(reg, mask, value); +} + +static inline int prcmu_enable_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return db5500_prcmu_enable_a9wdog(id); + else + return db8500_prcmu_enable_a9wdog(id); +} + +static inline int prcmu_disable_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return db5500_prcmu_disable_a9wdog(id); + else + return db8500_prcmu_disable_a9wdog(id); +} + +static inline int prcmu_kick_a9wdog(u8 id) +{ + if (cpu_is_u5500()) + return db5500_prcmu_kick_a9wdog(id); + else + return db8500_prcmu_kick_a9wdog(id); +} + +static inline int prcmu_load_a9wdog(u8 id, u32 timeout) +{ + if (cpu_is_u5500()) + return db5500_prcmu_load_a9wdog(id, timeout); + else + return db8500_prcmu_load_a9wdog(id, timeout); +} + +static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) +{ + if (cpu_is_u5500()) + return db5500_prcmu_config_a9wdog(num, sleep_auto_off); + else + return db8500_prcmu_config_a9wdog(num, sleep_auto_off); +} #else static inline void __init prcmu_early_init(void) {} @@ -405,6 +582,21 @@ static inline int prcmu_request_clock(u8 clock, bool enable) return 0; } +static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) +{ + return 0; +} + +static inline unsigned long prcmu_clock_rate(u8 clock) +{ + return 0; +} + static inline int prcmu_set_ape_opp(u8 opp) { return 0; @@ -480,14 +672,133 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf) *buf = NULL; } +static inline int prcmu_config_hotdog(u8 threshold) +{ + return 0; +} + +static inline int prcmu_config_hotmon(u8 low, u8 high) +{ + return 0; +} + +static inline int prcmu_start_temp_sense(u16 cycles32k) +{ + return 0; +} + +static inline int prcmu_stop_temp_sense(void) +{ + return 0; +} + +static inline u32 prcmu_read(unsigned int reg) +{ + return 0; +} + +static inline void prcmu_write(unsigned int reg, u32 value) {} + +static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} + +#endif + +static inline void prcmu_set(unsigned int reg, u32 bits) +{ + prcmu_write_masked(reg, bits, bits); +} + +static inline void prcmu_clear(unsigned int reg, u32 bits) +{ + prcmu_write_masked(reg, bits, 0); +} + +#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) + +/** + * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. + */ +static inline void prcmu_enable_spi2(void) +{ + if (cpu_is_u8500()) + prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); +} + +/** + * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. + */ +static inline void prcmu_disable_spi2(void) +{ + if (cpu_is_u8500()) + prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); +} + +/** + * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD + * and UARTMOD on OtherAlternateC3. + */ +static inline void prcmu_enable_stm_mod_uart(void) +{ + if (cpu_is_u8500()) { + prcmu_set(DB8500_PRCM_GPIOCR, + (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | + DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); + } +} + +/** + * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD + * and UARTMOD on OtherAlternateC3. + */ +static inline void prcmu_disable_stm_mod_uart(void) +{ + if (cpu_is_u8500()) { + prcmu_clear(DB8500_PRCM_GPIOCR, + (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | + DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); + } +} + +/** + * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1. + */ +static inline void prcmu_enable_stm_ape(void) +{ + if (cpu_is_u8500()) { + prcmu_set(DB8500_PRCM_GPIOCR, + DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); + } +} + +/** + * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1. + */ +static inline void prcmu_disable_stm_ape(void) +{ + if (cpu_is_u8500()) { + prcmu_clear(DB8500_PRCM_GPIOCR, + DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); + } +} + +#else + +static inline void prcmu_enable_spi2(void) {} +static inline void prcmu_disable_spi2(void) {} +static inline void prcmu_enable_stm_mod_uart(void) {} +static inline void prcmu_disable_stm_mod_uart(void) {} +static inline void prcmu_enable_stm_ape(void) {} +static inline void prcmu_disable_stm_ape(void) {} + #endif /* PRCMU QoS APE OPP class */ #define PRCMU_QOS_APE_OPP 1 #define PRCMU_QOS_DDR_OPP 2 +#define PRCMU_QOS_ARM_OPP 3 #define PRCMU_QOS_DEFAULT_VALUE -1 -#ifdef CONFIG_UX500_PRCMU_QOS_POWER +#ifdef CONFIG_DBX500_PRCMU_QOS_POWER unsigned long prcmu_qos_get_cpufreq_opp_delay(void); void prcmu_qos_set_cpufreq_opp_delay(unsigned long); @@ -500,6 +811,7 @@ int prcmu_qos_add_notifier(int prcmu_qos_class, struct notifier_block *notifier); int prcmu_qos_remove_notifier(int prcmu_qos_class, struct notifier_block *notifier); +void prcmu_qos_voice_call_override(bool enable); #else @@ -543,7 +855,7 @@ static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, { return 0; } - +static inline void prcmu_qos_voice_call_override(bool enable) {} #endif #endif /* __MACH_PRCMU_H */ diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index ca1d7a34760..3e86d53f3d5 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -114,7 +114,7 @@ struct matrix_keymap_data; * @no_autorepeat: disable key autorepeat */ struct stmpe_keypad_platform_data { - struct matrix_keymap_data *keymap_data; + const struct matrix_keymap_data *keymap_data; unsigned int debounce_ms; unsigned int scan_count; bool no_autorepeat; diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h new file mode 100644 index 00000000000..8c5385c2191 --- /dev/null +++ b/include/linux/mfd/tc35892.h @@ -0,0 +1,146 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License, version 2 + */ + +#ifndef __LINUX_MFD_TC35892_H +#define __LINUX_MFD_TC35892_H + +#include <linux/device.h> + +#define TC35892_RSTCTRL_IRQRST (1 << 4) +#define TC35892_RSTCTRL_TIMRST (1 << 3) +#define TC35892_RSTCTRL_ROTRST (1 << 2) +#define TC35892_RSTCTRL_KBDRST (1 << 1) +#define TC35892_RSTCTRL_GPIRST (1 << 0) + + +#define TC35892_MANFCODE 0x80 +#define TC35892_MANFCODE_MAGIC 0x03 +#define TC35892_VERSION 0x81 +#define TC35892_RSTCTRL 0x82 +#define TC35892_EXTRSTN 0x83 +#define TC35892_RSTINTCLR 0x84 +#define TC35892_CLKMODE 0x88 +#define TC35892_CLKCFG 0x89 +#define TC35892_CLKEN 0x8A +#define TC35892_IRQST 0x91 + +#define TC35892_DRIVE0_L 0xA0 +#define TC35892_DRIVE0_H 0xA1 +#define TC35892_DRIVE1_L 0xA2 +#define TC35892_DRIVE1_H 0xA3 +#define TC35892_DRIVE2_L 0xA4 +#define TC35892_DRIVE2_H 0XA5 +#define TC35892_DRIVE3 0xA6 +#define TC35892_IOCFG 0xA7 + +#define TC35892_IOPC0_L 0xAA +#define TC35892_IOPC0_H 0xAB +#define TC35892_IOPC1_L 0xAC +#define TC35892_IOPC1_H 0xAD +#define TC35892_IOPC2_L 0xAE +#define TC35892_IOPC2_H 0xAF + +#define TC35892_GPIODATA0 0xC0 +#define TC35892_GPIOMASK0 0xC1 +#define TC35892_GPIODATA1 0xC2 +#define TC35892_GPIOMASK1 0xC3 +#define TC35892_GPIODATA2 0xC4 +#define TC35892_GPIOMASK2 0xC5 +#define TC35892_GPIODIR0 0xC6 +#define TC35892_GPIODIR1 0xC7 +#define TC35892_GPIODIR2 0xC8 +#define TC35892_GPIOIS0 0xC9 +#define TC35892_GPIOIS1 0xCA +#define TC35892_GPIOIS2 0xCB +#define TC35892_GPIOIBE0 0xCC +#define TC35892_GPIOIBE1 0xCD +#define TC35892_GPIOIBE2 0xCE +#define TC35892_GPIOIEV0 0xCF +#define TC35892_GPIOIEV1 0xD0 +#define TC35892_GPIOIEV2 0xD1 +#define TC35892_GPIOIE0 0xD2 +#define TC35892_GPIOIE1 0xD3 +#define TC35892_GPIOIE2 0xD4 +#define TC35892_GPIORIS0 0xD6 +#define TC35892_GPIORIS1 0xD7 +#define TC35892_GPIORIS2 0xD8 +#define TC35892_GPIOMIS0 0xD9 +#define TC35892_GPIOMIS1 0xDA +#define TC35892_GPIOMIS2 0xDB +#define TC35892_GPIOIC0 0xDC +#define TC35892_GPIOIC1 0xDD +#define TC35892_GPIOIC2 0xDE +#define TC35892_GPIOODM0 0xE0 +#define TC35892_GPIOODE0 0xE1 +#define TC35892_GPIOODM1 0xE2 +#define TC35892_GPIOODE1 0xE3 +#define TC35892_GPIOODM2 0xE4 +#define TC35892_GPIOODE2 0xE5 + +#define TC35892_GPIOSYNC0 0xE6 +#define TC35892_GPIOSYNC1 0xE7 +#define TC35892_GPIOSYNC2 0xE8 + +#define TC35892_GPIOWAKE0 0xE9 +#define TC35892_GPIOWAKE1 0xEA +#define TC35892_GPIOWAKE2 0xEB + +#define TC35892_INT_GPIIRQ 0 +#define TC35892_INT_TI0IRQ 1 +#define TC35892_INT_TI1IRQ 2 +#define TC35892_INT_TI2IRQ 3 +#define TC35892_INT_ROTIRQ 5 +#define TC35892_INT_KBDIRQ 6 +#define TC35892_INT_PORIRQ 7 + +#define TC35892_NR_INTERNAL_IRQS 8 +#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) + +struct tc35892 { + struct mutex lock; + struct device *dev; + struct i2c_client *i2c; + + int irq_base; + int num_gpio; + struct tc35892_platform_data *pdata; +}; + +extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data); +extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg); +extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length, + u8 *values); +extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length, + const u8 *values); +extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val); + +/** + * struct tc35892_gpio_platform_data - TC35892 GPIO platform data + * @gpio_base: first gpio number assigned to TC35892. A maximum of + * %TC35892_NR_GPIOS GPIOs will be allocated. + * @setup: callback for board-specific initialization + * @remove: callback for board-specific teardown + */ +struct tc35892_gpio_platform_data { + int gpio_base; + void (*setup)(struct tc35892 *tc35892, unsigned gpio_base); + void (*remove)(struct tc35892 *tc35892, unsigned gpio_base); +}; + +/** + * struct tc35892_platform_data - TC35892 platform data + * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used. + * @gpio: GPIO-specific platform data + */ +struct tc35892_platform_data { + int irq_base; + struct tc35892_gpio_platform_data *gpio; +}; + +#define TC35892_NR_GPIOS 24 +#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) + +#endif diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h index 16c76e124f9..b8c6a941071 100644 --- a/include/linux/mfd/tc3589x.h +++ b/include/linux/mfd/tc3589x.h @@ -31,20 +31,43 @@ enum tx3589x_block { #define TC3589x_EVTCODE_FIFO 0x10 #define TC3589x_KBDMFS 0x8F -#define TC3589x_IRQST 0x91 - -#define TC3589x_MANFCODE_MAGIC 0x03 #define TC3589x_MANFCODE 0x80 +#define TC3589x_MANFCODE_MAGIC 0x03 #define TC3589x_VERSION 0x81 -#define TC3589x_IOCFG 0xA7 +#define TC3589x_RSTCTRL 0x82 +#define TC3589x_EXTRSTN 0x83 +#define TC3589x_RSTINTCLR 0x84 #define TC3589x_CLKMODE 0x88 #define TC3589x_CLKCFG 0x89 #define TC3589x_CLKEN 0x8A +#define TC3589x_IRQST 0x91 -#define TC3589x_RSTCTRL 0x82 -#define TC3589x_EXTRSTN 0x83 -#define TC3589x_RSTINTCLR 0x84 +#define TC3589x_DRIVE0_L 0xA0 +#define TC3589x_DRIVE0_H 0xA1 +#define TC3589x_DRIVE1_L 0xA2 +#define TC3589x_DRIVE1_H 0xA3 +#define TC3589x_DRIVE2_L 0xA4 +#define TC3589x_DRIVE2_H 0XA5 +#define TC3589x_DRIVE3 0xA6 +#define TC3589x_IOCFG 0xA7 + +#define TC3589x_IOPC0_L 0xAA +#define TC3589x_IOPC0_H 0xAB +#define TC3589x_IOPC1_L 0xAC +#define TC3589x_IOPC1_H 0xAD +#define TC3589x_IOPC2_L 0xAE +#define TC3589x_IOPC2_H 0xAF + +#define TC3589x_GPIODATA0 0xC0 +#define TC3589x_GPIOMASK0 0xC1 +#define TC3589x_GPIODATA1 0xC2 +#define TC3589x_GPIOMASK1 0xC3 +#define TC3589x_GPIODATA2 0xC4 +#define TC3589x_GPIOMASK2 0xC5 +#define TC3589x_GPIODIR0 0xC6 +#define TC3589x_GPIODIR1 0xC7 +#define TC3589x_GPIODIR2 0xC8 /* Pull up/down configuration registers */ #define TC3589x_IOCFG 0xA7 @@ -75,17 +98,12 @@ enum tx3589x_block { #define TC3589x_GPIOIC0 0xDC #define TC3589x_GPIOIC1 0xDD #define TC3589x_GPIOIC2 0xDE - -#define TC3589x_GPIODATA0 0xC0 -#define TC3589x_GPIOMASK0 0xc1 -#define TC3589x_GPIODATA1 0xC2 -#define TC3589x_GPIOMASK1 0xc3 -#define TC3589x_GPIODATA2 0xC4 -#define TC3589x_GPIOMASK2 0xC5 - -#define TC3589x_GPIODIR0 0xC6 -#define TC3589x_GPIODIR1 0xC7 -#define TC3589x_GPIODIR2 0xC8 +#define TC3589x_GPIOODM0 0xE0 +#define TC3589x_GPIOODE0 0xE1 +#define TC3589x_GPIOODM1 0xE2 +#define TC3589x_GPIOODE1 0xE3 +#define TC3589x_GPIOODM2 0xE4 +#define TC3589x_GPIOODE2 0xE5 #define TC3589x_GPIOSYNC0 0xE6 #define TC3589x_GPIOSYNC1 0xE7 @@ -95,13 +113,6 @@ enum tx3589x_block { #define TC3589x_GPIOWAKE1 0xEA #define TC3589x_GPIOWAKE2 0xEB -#define TC3589x_GPIOODM0 0xE0 -#define TC3589x_GPIOODE0 0xE1 -#define TC3589x_GPIOODM1 0xE2 -#define TC3589x_GPIOODE1 0xE3 -#define TC3589x_GPIOODM2 0xE4 -#define TC3589x_GPIOODE2 0xE5 - #define TC3589x_INT_GPIIRQ 0 #define TC3589x_INT_TI0IRQ 1 #define TC3589x_INT_TI1IRQ 2 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index ee2b0363c04..37f995176bb 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -318,6 +318,11 @@ struct mmc_host { int detect_change; /* card detect flag */ struct mmc_hotplug hotplug; + struct delayed_work resume; /* deferred resume work */ + unsigned int pm_state; /* used for deferred resume */ +#define MMC_HOST_DEFERRED_RESUME (1 << 0) +#define MMC_HOST_NEEDS_RESUME (1 << 1) + const struct mmc_bus_ops *bus_ops; /* current bus driver */ unsigned int bus_refs; /* reference counter */ @@ -366,6 +371,7 @@ static inline void *mmc_priv(struct mmc_host *host) extern int mmc_suspend_host(struct mmc_host *); extern int mmc_resume_host(struct mmc_host *); +extern void mmc_resume_host_sync(struct mmc_host *); extern int mmc_power_save_host(struct mmc_host *host); extern int mmc_power_restore_host(struct mmc_host *host); @@ -464,4 +470,15 @@ static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) return host->ios.clock; } #endif + +static inline int mmc_host_deferred_resume(struct mmc_host *host) +{ + return host->pm_state & MMC_HOST_DEFERRED_RESUME; +} + +static inline int mmc_host_needs_resume(struct mmc_host *host) +{ + return host->pm_state & MMC_HOST_NEEDS_RESUME; +} + #endif /* LINUX_MMC_HOST_H */ diff --git a/include/linux/regulator/ab5500.h b/include/linux/regulator/ab5500.h new file mode 100644 index 00000000000..b5a8dec0be6 --- /dev/null +++ b/include/linux/regulator/ab5500.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + */ + +#ifndef __LINUX_REGULATOR_AB5500_H +#define __LINUX_REGULATOR_AB5500_H + +enum ab5500_regulator_id { + AB5500_LDO_G, + AB5500_LDO_H, + AB5500_LDO_K, + AB5500_LDO_L, + AB5500_LDO_VDIGMIC, + AB5500_LDO_SIM, + AB5500_BIAS2, + AB5500_NUM_REGULATORS, +}; + +struct regulator_init_data; + +struct ab5500_regulator_data { + bool off_is_lowpower; +}; + +struct ab5500_regulator_platform_data { + struct regulator_init_data *regulator; + struct ab5500_regulator_data *data; + int num_regulator; +}; + +#endif diff --git a/include/linux/regulator/ab8500-debug.h b/include/linux/regulator/ab8500-debug.h new file mode 100644 index 00000000000..01655fc7fc1 --- /dev/null +++ b/include/linux/regulator/ab8500-debug.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * Authors: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson + */ + +#ifndef __LINUX_MFD_AB8500_REGULATOR_DEBUG_H +#define __LINUX_MFD_AB8500_REGULATOR_DEBUG_H + +#ifdef CONFIG_REGULATOR_AB8500_DEBUG +/* AB8500 debug force/restore functions */ +void ab8500_regulator_debug_force(void); +void ab8500_regulator_debug_restore(void); +#else +static inline void ab8500_regulator_debug_force(void) {} +static inline void ab8500_regulator_debug_restore(void) {} +#endif + +#endif diff --git a/include/linux/regulator/ab8500.h b/include/linux/regulator/ab8500.h index 76579f964a2..1c721867919 100644 --- a/include/linux/regulator/ab8500.h +++ b/include/linux/regulator/ab8500.h @@ -10,6 +10,8 @@ #ifndef __LINUX_MFD_AB8500_REGULATOR_H #define __LINUX_MFD_AB8500_REGULATOR_H +#include <linux/platform_device.h> + /* AB8500 regulators */ enum ab8500_regulator_id { AB8500_LDO_AUX1, @@ -17,25 +19,28 @@ enum ab8500_regulator_id { AB8500_LDO_AUX3, AB8500_LDO_INTCORE, AB8500_LDO_TVOUT, - AB8500_LDO_USB, AB8500_LDO_AUDIO, AB8500_LDO_ANAMIC1, AB8500_LDO_ANAMIC2, AB8500_LDO_DMIC, AB8500_LDO_ANA, + AB8500_SYSCLKREQ_2, + AB8500_SYSCLKREQ_4, AB8500_NUM_REGULATORS, }; /* AB8500 register initialization */ struct ab8500_regulator_reg_init { int id; + u8 mask; u8 value; }; -#define INIT_REGULATOR_REGISTER(_id, _value) \ - { \ - .id = _id, \ - .value = _value, \ +#define INIT_REGULATOR_REGISTER(_id, _mask, _value) \ + { \ + .id = _id, \ + .mask = _mask, \ + .value = _value, \ } /* AB8500 registers */ @@ -67,8 +72,38 @@ enum ab8500_regulator_reg { AB8500_REGUCTRL2SPARE, AB8500_REGUCTRLDISCH, AB8500_REGUCTRLDISCH2, - AB8500_VSMPS1SEL1, AB8500_NUM_REGULATOR_REGISTERS, }; +/* AB8500 external regulators */ +struct ab8500_ext_regulator_cfg { + bool hwreq; /* requires hw mode or high power mode */ +}; + +enum ab8500_ext_regulator_id { + AB8500_EXT_SUPPLY1, + AB8500_EXT_SUPPLY2, + AB8500_EXT_SUPPLY3, + AB8500_NUM_EXT_REGULATORS, +}; + +/* AB8500 regulator platform data */ +struct ab8500_regulator_platform_data { + int num_reg_init; + struct ab8500_regulator_reg_init *reg_init; + int num_regulator; + struct regulator_init_data *regulator; + int num_ext_regulator; + struct regulator_init_data *ext_regulator; +}; + +/* AB8500 external regulator functions (internal) */ +#ifdef CONFIG_REGULATOR_AB8500_EXT +__devinit int ab8500_ext_regulator_init(struct platform_device *pdev); +__devexit int ab8500_ext_regulator_exit(struct platform_device *pdev); +#else +inline __devinit int ab8500_ext_regulator_init(struct platform_device *pdev) {} +inline __devexit int ab8500_ext_regulator_exit(struct platform_device *pdev) {} +#endif + #endif diff --git a/include/linux/regulator/db5500-prcmu.h b/include/linux/regulator/db5500-prcmu.h new file mode 100644 index 00000000000..fee68795867 --- /dev/null +++ b/include/linux/regulator/db5500-prcmu.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson + * + * Interface to power domain regulators on DB5500 + */ + +#ifndef __DB5500_REGULATOR_H__ +#define __DB5500_REGULATOR_H__ + +#include <linux/regulator/dbx500-prcmu.h> + +/* Number of DB5500 regulators and regulator enumeration */ +enum db5500_regulator_id { + DB5500_REGULATOR_VAPE, + DB5500_REGULATOR_SWITCH_SGA, + DB5500_REGULATOR_SWITCH_HVA, + DB5500_REGULATOR_SWITCH_SIA, + DB5500_REGULATOR_SWITCH_DISP, + DB5500_REGULATOR_SWITCH_ESRAM12, + DB5500_NUM_REGULATORS +}; + +#endif diff --git a/include/linux/regulator/dbx500-prcmu.h b/include/linux/regulator/dbx500-prcmu.h new file mode 100644 index 00000000000..2ecb34c56aa --- /dev/null +++ b/include/linux/regulator/dbx500-prcmu.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) ST Ericsson SA 2011 + * + * License Terms: GNU General Public License v2 + * + */ +#ifndef __LINUX_REGULATOR_DBX500_H +#define __LINUX_REGULATOR_DBX500_H + +struct ux500_regulator; + +#ifdef CONFIG_REGULATOR +/* + * NOTE! The device will be connected to the correct regulator by this + * new framework. A list with connections will match up dev_name(dev) + * to the specific regulator. This follows the same principle as the + * normal regulator framework. + * + * This framework shall only be used in special cases when a regulator + * has to be enabled/disabled in atomic context. + */ + +/** + * ux500_regulator_get() + * + * @dev: Drivers device struct + * + * Returns a ux500_regulator struct. Shall be used as argument for + * ux500_regulator_atomic_enable/disable calls. + * Return ERR_PTR(-EINVAL) upon no matching regulator found. + */ +struct ux500_regulator *__must_check ux500_regulator_get(struct device *dev); + +/** + * ux500_regulator_atomic_enable() + * + * @regulator: Regulator handle, provided from ux500_regulator_get. + * + * The enable/disable functions keep an internal counter, so every + * enable must be paired with an disable in order to turn off regulator. + */ +int ux500_regulator_atomic_enable(struct ux500_regulator *regulator); + +/** + * ux500_regulator_atomic_disable() + * + * @regulator: Regulator handle, provided from ux500_regulator_get. + * + */ +int ux500_regulator_atomic_disable(struct ux500_regulator *regulator); + +/** + * ux500_regulator_put() + * + * @regulator: Regulator handle, provided from ux500_regulator_get. + */ +void ux500_regulator_put(struct ux500_regulator *regulator); + +#else + +static inline struct ux500_regulator *__must_check +ux500_regulator_get(struct device *dev) +{ + return ERR_PTR(-EINVAL); +} + +static inline int +ux500_regulator_atomic_enable(struct ux500_regulator *regulator) +{ + return -EINVAL; +} + +static inline int +ux500_regulator_atomic_disable(struct ux500_regulator *regulator) +{ + return -EINVAL; +} + +static inline void ux500_regulator_put(struct ux500_regulator *regulator) +{ +} +#endif /* CONFIG_REGULATOR */ + +#ifdef CONFIG_REGULATOR_DEBUG +void ux500_regulator_suspend_debug(void); +void ux500_regulator_resume_debug(void); +#else +static inline void ux500_regulator_suspend_debug(void) { } +static inline void ux500_regulator_resume_debug(void) { } +#endif + +#endif diff --git a/include/linux/spi/stm_msp.h b/include/linux/spi/stm_msp.h new file mode 100644 index 00000000000..501023105cb --- /dev/null +++ b/include/linux/spi/stm_msp.h @@ -0,0 +1,126 @@ +/* + * include/linux/spi/stm_msp.h + * + * Copyright (C) 2010 STMicroelectronics Pvt. Ltd. + * + * Author: Sachin Verma <sachin.verma@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _STM_MSP_H +#define _STM_MSP_H + +#include <linux/device.h> + +/* CHIP select/deselect commands */ +enum spi_chip_select { + SPI_CHIP_SELECT, + SPI_CHIP_DESELECT +}; + +/* Common configuration for different SPI controllers */ +enum spi_loopback { + SPI_LOOPBACK_DISABLED, + SPI_LOOPBACK_ENABLED +}; + +enum spi_hierarchy { + SPI_MASTER, + SPI_SLAVE +}; + +/* Endianess of FIFO Data */ +enum spi_fifo_endian { + SPI_FIFO_MSB, + SPI_FIFO_LSB +}; + +/* SPI mode of operation (Communication modes) */ +enum spi_mode { + SPI_INTERRUPT_TRANSFER, + SPI_POLLING_TRANSFER, +}; + +enum msp_data_size { + MSP_DATA_BITS_DEFAULT = -1, + MSP_DATA_BITS_8 = 0x00, + MSP_DATA_BITS_10, + MSP_DATA_BITS_12, + MSP_DATA_BITS_14, + MSP_DATA_BITS_16, + MSP_DATA_BITS_20, + MSP_DATA_BITS_24, + MSP_DATA_BITS_32, +}; + +enum msp_clk_src { + MSP_INTERNAL_CLK = 0x0, + MSP_EXTERNAL_CLK, +}; + +struct msp_clock_params { + enum msp_clk_src clk_src; + /* value from 0 to 1023 */ + u16 sckdiv; + /* Used only when MSPSCK clocks the sample rate + * generator (SCKSEL = 1Xb): + * 0b: The rising edge of MSPSCK clocks the sample rate generator + * 1b: The falling edge of MSPSCK clocks the sample rate generator */ + int sckpol; +}; + +/* Motorola SPI protocol specific definitions */ +enum spi_clk_phase { + SPI_CLK_ZERO_CYCLE_DELAY = 0x0, /* Receive data on rising edge. */ + SPI_CLK_HALF_CYCLE_DELAY /* Receive data on falling edge. */ +}; + +/* SPI Clock Polarity */ +enum spi_clk_pol { + SPI_CLK_POL_IDLE_LOW, /* Low inactive level */ + SPI_CLK_POL_IDLE_HIGH /* High inactive level */ +}; + +struct motorola_spi_proto_params { + enum spi_clk_phase clk_phase; + enum spi_clk_pol clk_pol; +}; + +struct stm_msp_config_chip { + struct device *dev; + enum spi_loopback lbm; + enum spi_hierarchy hierarchy; + enum spi_fifo_endian endian_rx; + enum spi_fifo_endian endian_tx; + enum spi_mode com_mode; + enum msp_data_size data_size; + struct msp_clock_params clk_freq; + int spi_burst_mode_enable; + struct motorola_spi_proto_params proto_params; + u32 freq; + void (*cs_control)(u32 control); +}; + +/** + * struct stm_msp_controller - device.platform_data for SPI controller devices. + * + * @num_chipselect: chipselects are used to distinguish individual + * SPI slaves, and are numbered from zero to num_chipselects - 1. + * each slave has a chipselect signal, but it's common that not + * every chipselect is connected to a slave. + */ +struct stm_msp_controller { + u8 num_chipselect; + u32 id; + u32 base_addr; + char *device_name; +}; +#endif /* _STM_MSP_H */ diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h new file mode 100644 index 00000000000..05e5529a6aa --- /dev/null +++ b/include/linux/sys_soc.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) ST-Ericsson SA 2011 + * Author: Maxime Coquelin <maxime.coquelin-nonst@stericsson.com> for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2 + */ +#ifndef __SYS_SOC_H +#define __SYS_SOC_H + +#include <linux/kobject.h> + +/** + * struct sys_soc_info - SoC exports related informations + * @name: name of the export + * @info: pointer on the key to export + * @get_info: callback to retrieve key if info field is NULL + * @attr: export's sysdev class attribute + */ +struct sysfs_soc_info { + const char *info; + ssize_t (*get_info)(char *buf, struct sysfs_soc_info *); + struct kobj_attribute attr; +}; + +ssize_t show_soc_info(struct kobject *, struct kobj_attribute *, char *); + +#define SYSFS_SOC_ATTR_VALUE(_name, _value) { \ + .attr.attr.name = _name, \ + .attr.attr.mode = S_IRUGO, \ + .attr.show = show_soc_info, \ + .info = _value, \ +} + +#define SYSFS_SOC_ATTR_CALLBACK(_name, _callback) { \ + .attr.attr.name = _name, \ + .attr.attr.mode = S_IRUGO, \ + .attr.show = show_soc_info, \ + .get_info = _callback, \ +} + +/** + * register_sys_soc - register the soc information + * @name: name of the machine + * @info: pointer on the info table to export + * @num: number of info to export + * + * NOTE: This function must only be called once + */ +int register_sysfs_soc(struct sysfs_soc_info *info, size_t num); + +#endif /* __SYS_SOC_H */ diff --git a/include/linux/tee.h b/include/linux/tee.h new file mode 100644 index 00000000000..c0f8f11d58d --- /dev/null +++ b/include/linux/tee.h @@ -0,0 +1,314 @@ +/* + * Trusted Execution Environment (TEE) interface for TrustZone enabled ARM CPUs. + * + * Copyright (C) ST-Ericsson SA 2010 + * Author: Shujuan Chen <shujuan.chen@stericsson.com> + * Author: Martin Hovang <martin.xm.hovang@stericsson.com> + * Author: Joakim Bech <joakim.xx.bech@stericsson.com> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef TEE_H +#define TEE_H + +/* tee_cmd id values */ +#define TEED_OPEN_SESSION 0x00000000U +#define TEED_CLOSE_SESSION 0x00000001U +#define TEED_INVOKE 0x00000002U + +/* tee_retval id values */ +#define TEED_SUCCESS 0x00000000U +#define TEED_ERROR_GENERIC 0xFFFF0000U +#define TEED_ERROR_ACCESS_DENIED 0xFFFF0001U +#define TEED_ERROR_CANCEL 0xFFFF0002U +#define TEED_ERROR_ACCESS_CONFLICT 0xFFFF0003U +#define TEED_ERROR_EXCESS_DATA 0xFFFF0004U +#define TEED_ERROR_BAD_FORMAT 0xFFFF0005U +#define TEED_ERROR_BAD_PARAMETERS 0xFFFF0006U +#define TEED_ERROR_BAD_STATE 0xFFFF0007U +#define TEED_ERROR_ITEM_NOT_FOUND 0xFFFF0008U +#define TEED_ERROR_NOT_IMPLEMENTED 0xFFFF0009U +#define TEED_ERROR_NOT_SUPPORTED 0xFFFF000AU +#define TEED_ERROR_NO_DATA 0xFFFF000BU +#define TEED_ERROR_OUT_OF_MEMORY 0xFFFF000CU +#define TEED_ERROR_BUSY 0xFFFF000DU +#define TEED_ERROR_COMMUNICATION 0xFFFF000EU +#define TEED_ERROR_SECURITY 0xFFFF000FU +#define TEED_ERROR_SHORT_BUFFER 0xFFFF0010U + +/* TEE origin codes */ +#define TEED_ORIGIN_DRIVER 0x00000002U +#define TEED_ORIGIN_TEE 0x00000003U +#define TEED_ORIGIN_TEE_APPLICATION 0x00000004U + +#define TEE_UUID_CLOCK_SIZE 8 + +#define TEEC_CONFIG_PAYLOAD_REF_COUNT 4 + +/* + * Flag constants indicating which of the memory references in an open session + * or invoke command operation payload (TEEC_Operation) that are used. + */ +#define TEEC_MEMREF_0_USED 0x00000001 +#define TEEC_MEMREF_1_USED 0x00000002 +#define TEEC_MEMREF_2_USED 0x00000004 +#define TEEC_MEMREF_3_USED 0x00000008 + +/* + * Flag constants indicating the data transfer direction of memory in + * TEEC_SharedMemory and TEEC_MemoryReference. TEEC_MEM_INPUT signifies data + * transfer direction from the client application to the TEE. TEEC_MEM_OUTPUT + * signifies data transfer direction from the TEE to the client application. + */ +#define TEEC_MEM_INPUT 0x00000001 +#define TEEC_MEM_OUTPUT 0x00000002 + +/* + * Session login methods, for use in TEEC_OpenSession() as parameter + * connectionMethod. Type is t_uint32. + * + * TEEC_LOGIN_PUBLIC No login data is provided. + */ +#define TEEC_LOGIN_PUBLIC 0x0 + +/* + * Exposed functions (command_id) in the static TA + */ +#define TEE_STA_GET_PRODUCT_CONFIG 10 +#define TEE_STA_SET_L2CC_PREFETCH_CTRL_REGISTER 11 + +/* Flags indicating run-time environment */ +#define TEE_RT_FLAGS_NORMAL 0x00000000 +#define TEE_RT_FLAGS_MASK_ITP_PROD 0x00000001 +#define TEE_RT_FLAGS_MODEM_DEBUG 0x00000002 +#define TEE_RT_FLAGS_RNG_REG_PUBLIC 0x00000004 +#define TEE_RT_FLAGS_JTAG_ENABLED 0x00000008 + +/* + * Product id numbers + */ +#define TEE_PRODUCT_ID_UNKNOWN 0 +#define TEE_PRODUCT_ID_8400 1 +#define TEE_PRODUCT_ID_8500 2 +#define TEE_PRODUCT_ID_9500 3 +#define TEE_PRODUCT_ID_5500 4 +#define TEE_PRODUCT_ID_7400 5 +#define TEE_PRODUCT_ID_8500C 6 + +/* Flags indicating fuses */ +#define TEE_FUSE_FLAGS_MODEM_DISABLE 0x00000001 + +/** + * struct tee_product_config - System configuration structure. + * + * @product_id: Product identification. + * @rt_flags: Runtime configuration flags. + * @fuse_flags: Fuse flags. + * + */ +struct tee_product_config { + uint32_t product_id; + uint32_t rt_flags; + uint32_t fuse_flags; +}; + +/** + * struct tee_uuid - Structure that represent an uuid. + * @timeLow: The low field of the time stamp. + * @timeMid: The middle field of the time stamp. + * @timeHiAndVersion: The high field of the timestamp multiplexed + * with the version number. + * @clockSeqAndNode: The clock sequence and the node. + * + * This structure have different naming (camel case) to comply with Global + * Platforms TEE Client API spec. This type is defined in RFC4122. + */ +struct tee_uuid { + uint32_t timeLow; + uint16_t timeMid; + uint16_t timeHiAndVersion; + uint8_t clockSeqAndNode[TEE_UUID_CLOCK_SIZE]; +}; + +/** + * struct tee_sharedmemory - Shared memory block for TEE. + * @buffer: The in/out data to TEE. + * @size: The size of the data. + * @flags: Variable telling whether it is a in, out or in/out parameter. + */ +struct tee_sharedmemory { + void *buffer; + size_t size; + uint32_t flags; +}; + +/** + * struct tee_operation - Payload for sessions or invoke operation. + * @shm: Array containing the shared memory buffers. + * @flags: Tells which if memory buffers that are in use. + */ +struct tee_operation { + struct tee_sharedmemory shm[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + uint32_t flags; +}; + +struct tee_context {}; + +/** + * struct tee_session - The session of an open tee device. + * @state: The current state in the linux kernel. + * @err: Error code (as in Global Platform TEE Client API spec) + * @origin: Origin for the error code (also from spec). + * @id: Implementation defined type, 0 if not used. + * @vaddr: Virtual address for the memrefs. + * @ta: The trusted application. + * @uuid: The uuid for the trusted application. + * @cmd: The command to be executed in the trusted application. + * @driver_cmd: The command type in the driver. This is used from a client (user + * space to tell the Linux kernel whether it's a open-, + * close-session or if it is an invoke command. + * @ta_size: The size of the trusted application. + * @op: The payload for the trusted application. + * @sync: Mutex to handle multiple use of clients. + * + * This structure is mainly used in the Linux kernel as a session context for + * ongoing operations. Other than that it is also used in the communication with + * the user space. + */ +struct tee_session { + uint32_t state; + uint32_t err; + uint32_t origin; + uint32_t id; + uint32_t *vaddr[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + void *ta; + struct tee_uuid *uuid; + unsigned int cmd; + unsigned int driver_cmd; + unsigned int ta_size; + struct tee_operation *op; + struct mutex *sync; +}; + +/** + * struct tee_read - Contains the error message and the origin. + * @err: Error code (as in Global Platform TEE Client API spec) + * @origin: Origin for the error code (also from spec). + * + * This is used by user space when a user space application wants to get more + * information about an error. + */ +struct tee_read { + unsigned int err; /* return value */ + unsigned int origin; /* error origin */ +}; + +/** + * Function that handles the function calls to trusted applications. + * @param ts: The session of a operation to be executed. + * @param sec_cmd: The type of command to be executed, open-, close-session, + * invoke command. + */ +int call_sec_world(struct tee_session *ts, int sec_cmd); + + +/** + * teec_initialize_context() - Initializes a context holding connection + * information on the specific TEE. + * @param name: A zero-terminated string identifying the TEE to connect to. + * If name is set to NULL, the default TEE is connected to. + * NULL is the only supported value in this version of the + * API implementation. + * @param context: The context structure which is to be initialized. + * + * Initializes a context holding connection information between the calling + * client application and the TEE designated by the name string. + */ +int teec_initialize_context(const char *name, struct tee_context *context); + +/** + * teec_finalize_context() - Destroys a context holding connection information + * on the specific TEE. + * @param context: The context to be destroyed. + * + * This function destroys an initialized TEE context, closing the connection + * between the client application and the TEE. This function must only be + * called when all sessions related to this TEE context have been closed and + * all shared memory blocks have been released. + */ +int teec_finalize_context(struct tee_context *context); + +/** + * teec_open_session() - Opens a new session with the specified trusted + * application. + * @param context: The initialized TEE context structure in which scope to + * open the session. + * @param session: The session to initialize. + * @param destination: A structure identifying the trusted application with + * which to open a session. If this is set to NULL the + * operation TEEC_MEMREF_0 is expected to contain the blob + * which holds the Trusted Application. + * @param connection_method: The connection method to use. + * @param connection_data: Any data necessary to connect with the chosen + * connection method. Not supported should be set to + * NULL. + * @param operation: An operation structure to use in the session. May be + * set to NULL to signify no operation structure needed. + * If destination is set to NULL, TEEC_MEMREF_0 is + * expected to hold the TA binary as described above. + * @param error_origin: A parameter which will hold the error origin if this + * function returns any value other than TEEC_SUCCESS. + * + * Opens a new session with the specified trusted application. Only + * connectionMethod == TEEC_LOGIN_PUBLIC is supported. connectionData and + * operation shall be set to NULL. + */ +int teec_open_session(struct tee_context *context, struct tee_session *session, + const struct tee_uuid *destination, + unsigned int connection_method, + void *connection_data, struct tee_operation *operation, + unsigned int *error_origin); + +/** + * teec_close_session() - Closes the session which has been opened with the + * specific trusted application. + * @param session: The opened session to close. + * + * Closes the session which has been opened with the specific trusted + * application. + */ +int teec_close_session(struct tee_session *session); + +/** + * teec_invoke_command() - Executes a command in the specified trusted + * application. + * @param destination: A structure identifying the trusted application. + * @param command_id: Identifier of the command in the trusted application to + * invoke. + * @param operation: An operation structure to use in the invoke command. May + * be set to NULL to signify no operation structure needed. + * @param error_origin: A parameter which will hold the error origin if this + * function returns any value other than TEEC_SUCCESS. + * + * Executes a command in the specified trusted application. + */ +int teec_invoke_command(struct tee_session *session, unsigned int command_id, + struct tee_operation *operation, + unsigned int *error_origin); + +/** + * teec_allocate_shared_memory() - Allocate shared memory for TEE. + * @param context: The initialized TEE context structure in which scope to + * open the session. + * @param shared_memory: Pointer to the allocated shared memory. + */ +int teec_allocate_shared_memory(struct tee_context *context, + struct tee_sharedmemory *shared_memory); + +/** + * teec_release_shared_memory() - Free the shared memory. + * @param shared_memory: Pointer to the shared memory to be freed. + */ +void teec_release_shared_memory(struct tee_sharedmemory *shared_memory); + +#endif diff --git a/include/linux/usb.h b/include/linux/usb.h index 69d845739bc..25c1cbf75d8 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -372,7 +372,15 @@ struct usb_bus { * limit. Because the arrays need to add a bit for hub status data, we * do 31, so plus one evens out to four bytes. */ + +#ifdef CONFIG_ARCH_U8500 +/** +* On U8500 platform we support 16 ports only +*/ +#define USB_MAXCHILDREN (16) +#else #define USB_MAXCHILDREN (31) +#endif struct usb_tt; diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index da653b5c713..e5c900a3d94 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -476,6 +476,8 @@ struct usb_gadget_ops { int (*start)(struct usb_gadget_driver *, int (*bind)(struct usb_gadget *)); int (*stop)(struct usb_gadget_driver *); + struct usb_ep* (*configure_ep)(struct usb_gadget *, u8 type, + struct usb_endpoint_descriptor *); }; /** diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h index d87f44f5b04..010b40d1b52 100644 --- a/include/linux/usb/otg.h +++ b/include/linux/usb/otg.h @@ -41,6 +41,9 @@ enum usb_xceiv_events { USB_EVENT_ID, /* id was grounded */ USB_EVENT_CHARGER, /* usb dedicated charger */ USB_EVENT_ENUMERATED, /* gadget driver enumerated */ + USB_EVENT_RIDA, + USB_EVENT_RIDB, + USB_EVENT_RIDC, }; struct otg_transceiver; diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h index 5e11f8a1f86..1db39e15a1a 100644 --- a/include/linux/videodev2.h +++ b/include/linux/videodev2.h @@ -1629,6 +1629,64 @@ enum v4l2_mpeg_mfc51_video_force_frame_type { #define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53) #define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54) +/* Private Base control IDs specific to the CG2900 FM driver as defined by V4L2 */ +#define V4L2_CID_CG2900_RADIO_PRIVATE_BASE (V4L2_CID_PRIVATE_BASE | 0x1000) +#define V4L2_CID_CG2900_RADIO_BANDSCAN (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+1) +enum v4l2_cg2900_radio_bandscan { + V4L2_CG2900_RADIO_BANDSCAN_START = 0, + V4L2_CG2900_RADIO_BANDSCAN_STOP = 1, +}; +#define V4L2_CID_CG2900_RADIO_BANDSCAN_GET_RESULTS (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+2) +#define V4L2_CID_CG2900_RADIO_BLOCKSCAN_START (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+3) +#define V4L2_CID_CG2900_RADIO_BLOCKSCAN_GET_RESULTS (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+4) +#define V4L2_CID_CG2900_RADIO_CHIP_STATE (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+5) +enum v4l2_cg2900_radio_chip_state { + V4L2_CG2900_RADIO_STANDBY = 0, + V4L2_CG2900_RADIO_POWERUP = 1, +}; +#define V4L2_CID_CG2900_RADIO_RSSI_THRESHOLD (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+6) +#define V4L2_CID_CG2900_RADIO_SELECT_ANTENNA (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+7) +enum v4l2_cg2900_radio_select_antenna { + V4L2_CG2900_RADIO_EMBEDDED_ANTENNA = 0, + V4L2_CG2900_RADIO_WIRED_ANTENNA = 1, +}; +#define V4L2_CID_CG2900_RADIO_RDS_AF_UPDATE_START (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+8) +#define V4L2_CID_CG2900_RADIO_RDS_AF_UPDATE_GET_RESULT (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+9) +#define V4L2_CID_CG2900_RADIO_RDS_AF_SWITCH_START (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+10) +#define V4L2_CID_CG2900_RADIO_RDS_AF_SWITCH_GET_RESULT (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+11) +#define V4L2_CID_CG2900_RADIO_TEST_TONE_GENERATOR_SET_STATUS (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+12) +enum v4l2_cg2900_radio_test_tone_generator_set_status { + V4L2_CG2900_RADIO_TEST_TONE_GEN_OFF = 0, + V4L2_CG2900_RADIO_TEST_TONE_GEN_ON_W_SRC = 1, + V4L2_CG2900_RADIO_TEST_TONE_GENERATOR_ON_WO_SRC = 2, +}; +#define V4L2_CID_CG2900_RADIO_TEST_TONE_CONNECT (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+13) +enum v4l2_cg2900_radio_test_tone_generator { + V4L2_CG2900_RADIO_TEST_TONE_NORMAL_AUDIO = 0, + V4L2_CG2900_RADIO_TEST_TONE_ZERO = 1, + V4L2_CG2900_RADIO_TEST_TONE_TONE_1 = 2, + V4L2_CG2900_RADIO_TEST_TONE_TONE_2 = 3, + V4L2_CG2900_RADIO_TEST_TONE_TONE_SUM = 4, +}; +#define V4L2_CID_CG2900_RADIO_TEST_TONE_SET_PARAMS (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+14) +#define V4L2_CID_CG2900_RADIO_TUNE_DEEMPHASIS (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+15) +enum v4l2_cg2900_radio_deemphasis { + V4L2_CG2900_RADIO_DEEMPHASIS_DISABLED = 0, + V4L2_CG2900_RADIO_DEEMPHASIS_50_uS = 1, + V4L2_CG2900_RADIO_DEEMPHASIS_75_uS = 2, +}; +#define V4L2_CID_CG2900_RADIO_GET_INTERRUPT (V4L2_CID_CG2900_RADIO_PRIVATE_BASE+16) +enum v4l2_cg2900_radio_interrupt { + V4L2_CG2900_RADIO_INTERRUPT_UNKNOWN = 0, + V4L2_CG2900_RADIO_INTERRUPT_SEARCH_COMPLETED = 1, + V4L2_CG2900_RADIO_INTERRUPT_BAND_SCAN_COMPLETED = 2, + V4L2_CG2900_RADIO_INTERRUPT_BLOCK_SCAN_COMPLETED = 3, + V4L2_CG2900_RADIO_INTERRUPT_SCAN_CANCELLED = 4, + V4L2_CG2900_RADIO_INTERRUPT_MONO_STEREO_TRANSITION = 5, + V4L2_CG2900_RADIO_INTERRUPT_DEVICE_RESET = 6, + V4L2_CG2900_RADIO_INTERRUPT_RDS_RECEIVED = 7 +}; + /* Camera class control IDs */ #define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900) #define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1) diff --git a/include/sound/ux500_ab8500.h b/include/sound/ux500_ab8500.h new file mode 100644 index 00000000000..7858bfdb4fa --- /dev/null +++ b/include/sound/ux500_ab8500.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Jarmo K. Kuronen <jarmo.kuronen@symbio.com> + * for ST-Ericsson. + * + * License terms: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef UX500_AB8500_H +#define UX500_AB8500_H + +extern struct snd_soc_ops ux500_ab8500_ops[]; + +struct snd_soc_pcm_runtime; + +int ux500_ab8500_startup(struct snd_pcm_substream *substream); + +void ux500_ab8500_shutdown(struct snd_pcm_substream *substream); + +int ux500_ab8500_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); + +int ux500_ab8500_soc_machine_drv_init(void); + +void ux500_ab8500_soc_machine_drv_cleanup(void); + +int ux500_ab8500_machine_codec_init(struct snd_soc_pcm_runtime *runtime); + +extern void ux500_ab8500_jack_report(int); + +#endif diff --git a/include/sound/ux500_ab8500_ext.h b/include/sound/ux500_ab8500_ext.h new file mode 100644 index 00000000000..1cc9a74585c --- /dev/null +++ b/include/sound/ux500_ab8500_ext.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Ola Lilja <ola.o.lilja@stericsson.com> + * for ST-Ericsson. + * + * License terms: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef UX500_AB8500_EXT_H +#define UX500_AB8500_EXT_H + +#include <linux/mfd/abx500/ab8500-gpadc.h> + +int ux500_ab8500_audio_gpadc_measure(struct ab8500_gpadc *gpadc, + u8 channel, bool mode, int *value); + +#endif diff --git a/include/trace/Kbuild b/include/trace/Kbuild new file mode 100644 index 00000000000..7e8b704d610 --- /dev/null +++ b/include/trace/Kbuild @@ -0,0 +1 @@ +header-y += stm.h diff --git a/include/trace/stm.h b/include/trace/stm.h new file mode 100644 index 00000000000..de3ed1dc381 --- /dev/null +++ b/include/trace/stm.h @@ -0,0 +1,228 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson STM Trace driver + * + * Author: Pierre Peiffer <pierre.peiffer@stericsson.com> for ST-Ericsson. + * Philippe Langlais <philippe.langlais@stericsson.com> for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef STM_H +#define STM_H + +#include <linux/types.h> + +#define STM_DEV_NAME "stm" + +/* One single channel mapping */ +struct stm_channel { + union { + __u8 no_stamp8; + __u16 no_stamp16; + __u32 no_stamp32; + __u64 no_stamp64; + }; + union { + __u8 stamp8; + __u16 stamp16; + __u32 stamp32; + __u64 stamp64; + }; +}; + +/* Possible trace modes */ +#define STM_SW_LOSSLESS 0 /* Software mode: lossless data but intrusive */ +#define STM_HW_LOSSY 1 /* Hardware mode: lossy data but less intrusive */ + +/* Possible clock setting */ +enum clock_div { + STM_CLOCK_DIV2 = 0, + STM_CLOCK_DIV4, + STM_CLOCK_DIV6, + STM_CLOCK_DIV8, + STM_CLOCK_DIV10, + STM_CLOCK_DIV12, + STM_CLOCK_DIV14, + STM_CLOCK_DIV16, +}; + +/* ioctl commands */ +#define STM_CONNECTION _IOW('t', 0, enum stm_connection_type) +#define STM_DISABLE _IO('t', 1) +#define STM_GET_NB_MAX_CHANNELS _IOR('t', 2, int) +#define STM_GET_NB_FREE_CHANNELS _IOR('t', 3, int) +#define STM_GET_CHANNEL_NO _IOR('t', 4, int) +#define STM_SET_CLOCK_DIV _IOW('t', 5, enum clock_div) +#define STM_GET_CTRL_REG _IOR('t', 6, int) +#define STM_ENABLE_SRC _IOWR('t', 7, int) +#define STM_GET_FREE_CHANNEL _IOW('t', 8, int) +#define STM_RELEASE_CHANNEL _IOW('t', 9, int) +#define STM_SET_MODE _IOWR('t', 10, int) +#define STM_GET_MODE _IOR('t', 11, int) + +enum stm_connection_type { + STM_DISCONNECT = 0, + STM_DEFAULT_CONNECTION = 1, + STM_STE_MODEM_ON_MIPI34_NONE_ON_MIPI60 = 2, + STM_STE_APE_ON_MIPI34_NONE_ON_MIPI60 = 3, + STM_STE_MODEM_ON_MIPI34_APE_ON_MIPI60 = 4, + STM_STE_MODEM_ON_MICROSD = 5, + STM_STE_APE_ON_MICROSD = 6, + STM_STE_INVALID_CONNECTION = 0xff +}; + +#ifdef __KERNEL__ + +struct stm_platform_data { + u32 regs_phys_base; + u32 channels_phys_base; + u32 id_mask; + u32 masters_enabled; + const s16 *channels_reserved; + int channels_reserved_sz; + int (*stm_connection)(enum stm_connection_type); +}; + +/* Channels base address */ +extern volatile struct stm_channel __iomem *stm_channels; + +/* Provides stm_trace_XX() and stm_tracet_XX() trace API */ +#define DEFLLTFUN(size) \ +static inline void stm_trace_##size(int channel, __u##size data) \ +{ \ + stm_channels[channel].no_stamp##size = data; \ +} \ +static inline void stm_tracet_##size(int channel, __u##size data) \ +{ \ + stm_channels[channel].stamp##size = data; \ +} \ + +DEFLLTFUN(8); +DEFLLTFUN(16); +DEFLLTFUN(32); +DEFLLTFUN(64); + +/* + * Trace a buffer on a given channel + * with auto time stamping on the last byte(s) only + */ +int stm_trace_buffer_onchannel(int channel, const void *data, size_t length); +/* + * Trace a buffer on a dynamically allocated channel + * with auto time stamping on the last byte(s) only + * Dynamic channel are allocated in the 128 highest channels + */ +int stm_trace_buffer(const void *data, size_t length); + +/* printk equivalent for STM */ +int stm_printk(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); + +#if defined(CONFIG_STM_PRINTK) +#define stm_dup_printk(buf, length) \ + stm_trace_buffer_onchannel(CONFIG_STM_PRINTK_CHANNEL, buf, length) + +#else +static inline int stm_dup_printk(char *buf, size_t size) +{ + return 0; +} +#endif + +#if defined(CONFIG_STM_TRACE_PRINTK) +static inline int stm_trace_printk_buf( + unsigned long ip, const char *buf, size_t size) +{ + stm_trace_32(CONFIG_STM_TRACE_PRINTK_CHANNEL, ip); + return stm_trace_buffer_onchannel(CONFIG_STM_TRACE_PRINTK_CHANNEL, + buf, size); +} + +static inline int stm_trace_bprintk_buf( + unsigned long ip, const char *fmt, const void *buf, size_t size) +{ + stm_trace_64(CONFIG_STM_TRACE_BPRINTK_CHANNEL, ((u64)ip<<32)+(u32)fmt); + return stm_trace_buffer_onchannel(CONFIG_STM_TRACE_PRINTK_CHANNEL, + buf, size); +} +#else +static inline int stm_trace_printk_buf( + unsigned long ip, const char *buf, size_t size) +{ + return 0; +} + +static inline int stm_trace_bprintk_buf( + unsigned long ip, const char *fmt, const void *buf, size_t size) +{ + return 0; +} +#endif + +#if defined(CONFIG_STM_FTRACE) +static inline void stm_ftrace(unsigned long ip, unsigned long parent_ip) +{ + stm_tracet_64(CONFIG_STM_FTRACE_CHANNEL, (((__u64)ip)<<32) + parent_ip); +} +#else +static inline void stm_ftrace(unsigned long ip, unsigned long parent_ip) +{ +} +#endif + +#if defined(CONFIG_STM_CTX_SWITCH) +static inline void stm_sched_switch(u32 prev_pid, u8 prev_prio, u8 prev_state, + u32 next_pid, u8 next_prio, u8 next_state, u32 next_cpu) +{ + stm_trace_64(CONFIG_STM_CTX_SWITCH_CHANNEL, + (((__u64)prev_pid)<<32) + next_pid); + stm_tracet_64(CONFIG_STM_CTX_SWITCH_CHANNEL, (((__u64)next_cpu)<<32) + + (prev_prio<<24) + (prev_state<<16) + + (next_prio<<8) + next_state); +} +#else +static inline void stm_sched_switch(u32 prev_pid, u8 prev_prio, u8 prev_state, + u32 next_pid, u8 next_prio, u8 next_state, u32 next_cpu) +{ +} +#endif + +#if defined(CONFIG_STM_WAKEUP) +static inline void stm_sched_wakeup(u32 prev_pid, u8 prev_prio, u8 prev_state, + u32 next_pid, u8 next_prio, u8 next_state, u32 next_cpu) +{ + stm_trace_64(CONFIG_STM_WAKEUP_CHANNEL, + (((__u64)prev_pid)<<32) + next_pid); + stm_tracet_64(CONFIG_STM_WAKEUP_CHANNEL, (((__u64)next_cpu)<<32) + + (prev_prio<<24) + (prev_state<<16) + + (next_prio<<8) + next_state); +} +#else +static inline void stm_sched_wakeup(u32 prev_pid, u8 prev_prio, u8 prev_state, + u32 next_pid, u8 next_prio, u8 next_state, u32 next_cpu) +{ +} +#endif + +#if defined(CONFIG_STM_STACK_TRACE) +static inline void stm_stack_trace(unsigned long *callers) +{ + while (*(callers + 1) != ULONG_MAX) { + stm_trace_32(CONFIG_STM_STACK_TRACE_CHANNEL, *callers++); + } + /* Time stamp the latest */ + stm_tracet_32(CONFIG_STM_STACK_TRACE_CHANNEL, *callers); +} +#else +static inline void stm_stack_trace(unsigned long *callers) +{ +} +#endif + +/* Alloc/Free STM channel */ +int stm_alloc_channel(int offset); +void stm_free_channel(int channel); + +#endif /* __KERNEL__ */ + +#endif /* STM_H */ diff --git a/include/video/Kbuild b/include/video/Kbuild index ad3e622c533..d73b95df921 100644 --- a/include/video/Kbuild +++ b/include/video/Kbuild @@ -1,3 +1,4 @@ +header-y += b2r2_blt.h header-y += edid.h header-y += sisfb.h header-y += uvesafb.h diff --git a/include/video/av8100.h b/include/video/av8100.h new file mode 100644 index 00000000000..23e96a0b871 --- /dev/null +++ b/include/video/av8100.h @@ -0,0 +1,549 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * AV8100 driver + * + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __AV8100__H__ +#define __AV8100__H__ + +#define AV8100_CEC_MESSAGE_SIZE 16 +#define AV8100_HDCP_SEND_KEY_SIZE 16 +#define AV8100_INFOFRAME_SIZE 28 +#define AV8100_FUSE_KEY_SIZE 16 +#define AV8100_CHIPVER_1 1 +#define AV8100_CHIPVER_2 2 + +struct av8100_platform_data { + unsigned gpio_base; + int irq; + int reset; + const char *inputclk_id; + const char *regulator_pwr_id; + bool alt_powerupseq; + unsigned char mclk_freq; +}; + +enum av8100_command_type { + AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1, + AV8100_COMMAND_AUDIO_INPUT_FORMAT, + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, + AV8100_COMMAND_VIDEO_SCALING_FORMAT, + AV8100_COMMAND_COLORSPACECONVERSION, + AV8100_COMMAND_CEC_MESSAGE_WRITE, + AV8100_COMMAND_CEC_MESSAGE_READ_BACK, + AV8100_COMMAND_DENC, + AV8100_COMMAND_HDMI, + AV8100_COMMAND_HDCP_SENDKEY, + AV8100_COMMAND_HDCP_MANAGEMENT, + AV8100_COMMAND_INFOFRAMES, + AV8100_COMMAND_EDID_SECTION_READBACK, + AV8100_COMMAND_PATTERNGENERATOR, + AV8100_COMMAND_FUSE_AES_KEY, +}; + +enum interface_type { + I2C_INTERFACE = 0x0, + DSI_INTERFACE = 0x1, +}; + +enum av8100_dsi_mode { + AV8100_HDMI_DSI_OFF, + AV8100_HDMI_DSI_COMMAND_MODE, + AV8100_HDMI_DSI_VIDEO_MODE +}; + +enum av8100_pixel_format { + AV8100_INPUT_PIX_RGB565, + AV8100_INPUT_PIX_RGB666, + AV8100_INPUT_PIX_RGB666P, + AV8100_INPUT_PIX_RGB888, + AV8100_INPUT_PIX_YCBCR422 +}; + +enum av8100_video_mode { + AV8100_VIDEO_INTERLACE, + AV8100_VIDEO_PROGRESSIVE +}; + +enum av8100_dsi_nb_data_lane { + AV8100_DATA_LANES_USED_0, + AV8100_DATA_LANES_USED_1, + AV8100_DATA_LANES_USED_2, + AV8100_DATA_LANES_USED_3, + AV8100_DATA_LANES_USED_4 +}; + +enum av8100_te_config { + AV8100_TE_OFF, /* NO TE*/ + AV8100_TE_DSI_LANE, /* TE generated on DSI lane */ + AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */ + AV8100_TE_DSI_IT, /* TE generatedon both DSI lane & IT line*/ + AV8100_TE_GPIO_IT /* TE on GPIO I2S DAT3 & or IT line*/ +}; + +enum av8100_audio_if_format { + AV8100_AUDIO_I2S_MODE, + AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/ + AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/ +}; + +enum av8100_sample_freq { + AV8100_AUDIO_FREQ_32KHZ, + AV8100_AUDIO_FREQ_44_1KHZ, + AV8100_AUDIO_FREQ_48KHZ, + AV8100_AUDIO_FREQ_64KHZ, + AV8100_AUDIO_FREQ_88_2KHZ, + AV8100_AUDIO_FREQ_96KHZ, + AV8100_AUDIO_FREQ_128KHZ, + AV8100_AUDIO_FREQ_176_1KHZ, + AV8100_AUDIO_FREQ_192KHZ +}; + +enum av8100_audio_word_length { + AV8100_AUDIO_16BITS, + AV8100_AUDIO_20BITS, + AV8100_AUDIO_24BITS +}; + +enum av8100_audio_format { + AV8100_AUDIO_LPCM_MODE, + AV8100_AUDIO_COMPRESS_MODE +}; + +enum av8100_audio_if_mode { + AV8100_AUDIO_SLAVE, + AV8100_AUDIO_MASTER +}; + +enum av8100_audio_mute { + AV8100_AUDIO_MUTE_DISABLE, + AV8100_AUDIO_MUTE_ENABLE +}; + +enum av8100_output_CEA_VESA { + AV8100_CUSTOM, + AV8100_CEA1_640X480P_59_94HZ, + AV8100_CEA2_3_720X480P_59_94HZ, + AV8100_CEA4_1280X720P_60HZ, + AV8100_CEA5_1920X1080I_60HZ, + AV8100_CEA6_7_NTSC_60HZ, + AV8100_CEA14_15_480p_60HZ, + AV8100_CEA16_1920X1080P_60HZ, + AV8100_CEA17_18_720X576P_50HZ, + AV8100_CEA19_1280X720P_50HZ, + AV8100_CEA20_1920X1080I_50HZ, + AV8100_CEA21_22_576I_PAL_50HZ, + AV8100_CEA29_30_576P_50HZ, + AV8100_CEA31_1920x1080P_50Hz, + AV8100_CEA32_1920X1080P_24HZ, + AV8100_CEA33_1920X1080P_25HZ, + AV8100_CEA34_1920X1080P_30HZ, + AV8100_CEA60_1280X720P_24HZ, + AV8100_CEA61_1280X720P_25HZ, + AV8100_CEA62_1280X720P_30HZ, + AV8100_VESA9_800X600P_60_32HZ, + AV8100_VESA14_848X480P_60HZ, + AV8100_VESA16_1024X768P_60HZ, + AV8100_VESA22_1280X768P_59_99HZ, + AV8100_VESA23_1280X768P_59_87HZ, + AV8100_VESA27_1280X800P_59_91HZ, + AV8100_VESA28_1280X800P_59_81HZ, + AV8100_VESA39_1360X768P_60_02HZ, + AV8100_VESA81_1366X768P_59_79HZ, + AV8100_VIDEO_OUTPUT_CEA_VESA_MAX +}; + +enum av8100_video_sync_pol { + AV8100_SYNC_POSITIVE, + AV8100_SYNC_NEGATIVE +}; + +enum av8100_hdmi_mode { + AV8100_HDMI_OFF, + AV8100_HDMI_ON, + AV8100_HDMI_AVMUTE +}; + +enum av8100_hdmi_format { + AV8100_HDMI, + AV8100_DVI +}; + +enum av8100_DVI_format { + AV8100_DVI_CTRL_CTL0, + AV8100_DVI_CTRL_CTL1, + AV8100_DVI_CTRL_CTL2 +}; + +enum av8100_pattern_type { + AV8100_PATTERN_OFF, + AV8100_PATTERN_GENERATOR, + AV8100_PRODUCTION_TESTING +}; + +enum av8100_pattern_format { + AV8100_NO_PATTERN, + AV8100_PATTERN_VGA, + AV8100_PATTERN_720P, + AV8100_PATTERN_1080P +}; + +enum av8100_pattern_audio { + AV8100_PATTERN_AUDIO_OFF, + AV8100_PATTERN_AUDIO_ON, + AV8100_PATTERN_AUDIO_I2S_MEM +}; + +struct av8100_video_input_format_cmd { + enum av8100_dsi_mode dsi_input_mode; + enum av8100_pixel_format input_pixel_format; + unsigned short total_horizontal_pixel; + unsigned short total_horizontal_active_pixel; + unsigned short total_vertical_lines; + unsigned short total_vertical_active_lines; + enum av8100_video_mode video_mode; + enum av8100_dsi_nb_data_lane nb_data_lane; + unsigned char nb_virtual_ch_command_mode; + unsigned char nb_virtual_ch_video_mode; + unsigned short TE_line_nb; + enum av8100_te_config TE_config; + unsigned long master_clock_freq; + unsigned char ui_x4; +}; + +struct av8100_audio_input_format_cmd { + enum av8100_audio_if_format audio_input_if_format; + unsigned char i2s_input_nb; + enum av8100_sample_freq sample_audio_freq; + enum av8100_audio_word_length audio_word_lg; + enum av8100_audio_format audio_format; + enum av8100_audio_if_mode audio_if_mode; + enum av8100_audio_mute audio_mute; +}; + +struct av8100_video_output_format_cmd { + enum av8100_output_CEA_VESA video_output_cea_vesa; + enum av8100_video_sync_pol vsync_polarity; + enum av8100_video_sync_pol hsync_polarity; + unsigned short total_horizontal_pixel; + unsigned short total_horizontal_active_pixel; + unsigned short total_vertical_in_half_lines; + unsigned short total_vertical_active_in_half_lines; + unsigned short hsync_start_in_pixel; + unsigned short hsync_length_in_pixel; + unsigned short vsync_start_in_half_line; + unsigned short vsync_length_in_half_line; + unsigned short hor_video_start_pixel; + unsigned short vert_video_start_pixel; + enum av8100_video_mode video_type; + unsigned short pixel_repeat; + unsigned long pixel_clock_freq_Hz; +}; + +struct av8100_video_scaling_format_cmd { + unsigned short h_start_in_pixel; + unsigned short h_stop_in_pixel; + unsigned short v_start_in_line; + unsigned short v_stop_in_line; + unsigned short h_start_out_pixel; + unsigned short h_stop_out_pixel; + unsigned short v_start_out_line; + unsigned short v_stop_out_line; +}; + +enum av8100_color_transform { + AV8100_COLOR_TRANSFORM_INDENTITY, + AV8100_COLOR_TRANSFORM_INDENTITY_CLAMP_YUV, + AV8100_COLOR_TRANSFORM_YUV_TO_RGB, + AV8100_COLOR_TRANSFORM_YUV_TO_DENC, + AV8100_COLOR_TRANSFORM_RGB_TO_DENC, +}; + +struct av8100_cec_message_write_format_cmd { + unsigned char buffer_length; + unsigned char buffer[AV8100_CEC_MESSAGE_SIZE]; +}; + +struct av8100_cec_message_read_back_format_cmd { +}; + +enum av8100_cvbs_video_format { + AV8100_CVBS_625, + AV8100_CVBS_525, +}; + +enum av8100_standard_selection { + AV8100_PAL_BDGHI, + AV8100_PAL_N, + AV8100_NTSC_M, + AV8100_PAL_M +}; + +struct av8100_denc_format_cmd { + enum av8100_cvbs_video_format cvbs_video_format; + enum av8100_standard_selection standard_selection; + unsigned char enable; + unsigned char macrovision_enable; + unsigned char internal_generator; +}; + +struct av8100_hdmi_cmd { + enum av8100_hdmi_mode hdmi_mode; + enum av8100_hdmi_format hdmi_format; + enum av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/ +}; + +struct av8100_hdcp_send_key_format_cmd { + unsigned char key_number; + unsigned char data_len; + unsigned char data[AV8100_HDCP_SEND_KEY_SIZE]; +}; + +enum av8100_hdcp_auth_req_type { + AV8100_HDCP_AUTH_REQ_OFF = 0, + AV8100_HDCP_AUTH_REQ_ON = 1, + AV8100_HDCP_REV_LIST_REQ = 2, + AV8100_HDCP_AUTH_CONT = 3, +}; + +enum av8100_hdcp_encr_use { + AV8100_HDCP_ENCR_USE_OESS = 0, + AV8100_HDCP_ENCR_USE_EESS = 1, +}; + +struct av8100_hdcp_management_format_cmd { + unsigned char req_type; + unsigned char encr_use; +}; + +struct av8100_infoframes_format_cmd { + unsigned char type; + unsigned char version; + unsigned char length; + unsigned char crc; + unsigned char data[AV8100_INFOFRAME_SIZE]; +}; + +struct av8100_edid_section_readback_format_cmd { + unsigned char address; + unsigned char block_number; +}; + +struct av8100_pattern_generator_format_cmd { + enum av8100_pattern_type pattern_type; + enum av8100_pattern_format pattern_video_format; + enum av8100_pattern_audio pattern_audio_mode; +}; + +enum av8100_fuse_operation { + AV8100_FUSE_READ = 0, + AV8100_FUSE_WRITE = 1, +}; + +struct av8100_fuse_aes_key_format_cmd { + unsigned char fuse_operation; + unsigned char key[AV8100_FUSE_KEY_SIZE]; +}; + +union av8100_configuration { + struct av8100_video_input_format_cmd video_input_format; + struct av8100_audio_input_format_cmd audio_input_format; + struct av8100_video_output_format_cmd video_output_format; + struct av8100_video_scaling_format_cmd video_scaling_format; + enum av8100_color_transform color_transform; + struct av8100_cec_message_write_format_cmd + cec_message_write_format; + struct av8100_cec_message_read_back_format_cmd + cec_message_read_back_format; + struct av8100_denc_format_cmd denc_format; + struct av8100_hdmi_cmd hdmi_format; + struct av8100_hdcp_send_key_format_cmd hdcp_send_key_format; + struct av8100_hdcp_management_format_cmd hdcp_management_format; + struct av8100_infoframes_format_cmd infoframes_format; + struct av8100_edid_section_readback_format_cmd + edid_section_readback_format; + struct av8100_pattern_generator_format_cmd pattern_generator_format; + struct av8100_fuse_aes_key_format_cmd fuse_aes_key_format; +}; + +enum av8100_operating_mode { + AV8100_OPMODE_UNDEFINED = 0, + AV8100_OPMODE_SHUTDOWN, + AV8100_OPMODE_STANDBY, + AV8100_OPMODE_SCAN, + AV8100_OPMODE_INIT, + AV8100_OPMODE_IDLE, + AV8100_OPMODE_VIDEO, +}; + +enum av8100_plugin_status { + AV8100_PLUGIN_NONE = 0x0, + AV8100_HDMI_PLUGIN = 0x1, + AV8100_CVBS_PLUGIN = 0x2, +}; + +enum av8100_hdmi_event { + AV8100_HDMI_EVENT_NONE = 0x0, + AV8100_HDMI_EVENT_HDMI_PLUGIN = 0x1, + AV8100_HDMI_EVENT_HDMI_PLUGOUT = 0x2, + AV8100_HDMI_EVENT_CEC = 0x4, + AV8100_HDMI_EVENT_HDCP = 0x8, + AV8100_HDMI_EVENT_CECTXERR = 0x10, + AV8100_HDMI_EVENT_CECTX = 0x20, /* Transm no error */ +}; + +struct av8100_status { + enum av8100_operating_mode av8100_state; + enum av8100_plugin_status av8100_plugin_status; + int hdmi_on; +}; + + +int av8100_init(void); +void av8100_exit(void); +int av8100_powerscan(void); +int av8100_powerup(void); +int av8100_powerdown(void); +int av8100_disable_interrupt(void); +int av8100_enable_interrupt(void); +int av8100_download_firmware(enum interface_type if_type); +int av8100_reg_stby_w( + unsigned char cpd, + unsigned char stby, + unsigned char mclkrng); +int av8100_reg_hdmi_5_volt_time_w( + unsigned char denc_off_time, + unsigned char hdmi_off_time, + unsigned char on_time); +int av8100_reg_stby_int_mask_w( + unsigned char hpdm, + unsigned char cpdm, + unsigned char stbygpiocfg, + unsigned char ipol); +int av8100_reg_stby_pend_int_w( + unsigned char hpdi, + unsigned char cpdi, + unsigned char oni, + unsigned char bpdig); +int av8100_reg_gen_int_mask_w( + unsigned char eocm, + unsigned char vsim, + unsigned char vsom, + unsigned char cecm, + unsigned char hdcpm, + unsigned char uovbm, + unsigned char tem); +int av8100_reg_gen_int_w( + unsigned char eoci, + unsigned char vsii, + unsigned char vsoi, + unsigned char ceci, + unsigned char hdcpi, + unsigned char uovbi); +int av8100_reg_gpio_conf_w( + unsigned char dat3dir, + unsigned char dat3val, + unsigned char dat2dir, + unsigned char dat2val, + unsigned char dat1dir, + unsigned char dat1val, + unsigned char ucdbg); +int av8100_reg_gen_ctrl_w( + unsigned char fdl, + unsigned char hld, + unsigned char wa, + unsigned char ra); +int av8100_reg_fw_dl_entry_w( + unsigned char mbyte_code_entry); +int av8100_reg_w( + unsigned char offset, + unsigned char value); +int av8100_reg_stby_r( + unsigned char *cpd, + unsigned char *stby, + unsigned char *hpds, + unsigned char *cpds, + unsigned char *mclkrng); +int av8100_reg_hdmi_5_volt_time_r( + unsigned char *denc_off_time, + unsigned char *hdmi_off_time, + unsigned char *on_time); +int av8100_reg_stby_int_mask_r( + unsigned char *hpdm, + unsigned char *cpdm, + unsigned char *stbygpiocfg, + unsigned char *ipol); +int av8100_reg_stby_pend_int_r( + unsigned char *hpdi, + unsigned char *cpdi, + unsigned char *oni, + unsigned char *sid); +int av8100_reg_gen_int_mask_r( + unsigned char *eocm, + unsigned char *vsim, + unsigned char *vsom, + unsigned char *cecm, + unsigned char *hdcpm, + unsigned char *uovbm, + unsigned char *tem); +int av8100_reg_gen_int_r( + unsigned char *eoci, + unsigned char *vsii, + unsigned char *vsoi, + unsigned char *ceci, + unsigned char *hdcpi, + unsigned char *uovbi, + unsigned char *tei); +int av8100_reg_gen_status_r( + unsigned char *cectxerr, + unsigned char *cecrec, + unsigned char *cectrx, + unsigned char *uc, + unsigned char *onuvb, + unsigned char *hdcps); +int av8100_reg_gpio_conf_r( + unsigned char *dat3dir, + unsigned char *dat3val, + unsigned char *dat2dir, + unsigned char *dat2val, + unsigned char *dat1dir, + unsigned char *dat1val, + unsigned char *ucdbg); +int av8100_reg_gen_ctrl_r( + unsigned char *fdl, + unsigned char *hld, + unsigned char *wa, + unsigned char *ra); +int av8100_reg_fw_dl_entry_r( + unsigned char *mbyte_code_entry); +int av8100_reg_r( + unsigned char offset, + unsigned char *value); +int av8100_conf_get(enum av8100_command_type command_type, + union av8100_configuration *config); +int av8100_conf_prep(enum av8100_command_type command_type, + union av8100_configuration *config); +int av8100_conf_w(enum av8100_command_type command_type, + unsigned char *return_buffer_length, + unsigned char *return_buffer, enum interface_type if_type); +int av8100_conf_w_raw(enum av8100_command_type command_type, + unsigned char buffer_length, + unsigned char *buffer, + unsigned char *return_buffer_length, + unsigned char *return_buffer); +struct av8100_status av8100_status_get(void); +enum av8100_output_CEA_VESA av8100_video_output_format_get(int xres, + int yres, + int htot, + int vtot, + int pixelclk, + bool interlaced); +void av8100_hdmi_event_cb_set(void (*event_callback)(enum av8100_hdmi_event)); +u8 av8100_ver_get(void); + +#endif /* __AV8100__H__ */ diff --git a/include/video/b2r2_blt.h b/include/video/b2r2_blt.h new file mode 100644 index 00000000000..771d4f60fdb --- /dev/null +++ b/include/video/b2r2_blt.h @@ -0,0 +1,638 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson B2R2 user interface + * + * Author: Robert Fekete <robert.fekete@stericsson.com> + * Author: Paul Wannback + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + + +#ifndef _LINUX_VIDEO_B2R2_BLT_H +#define _LINUX_VIDEO_B2R2_BLT_H + +#include <linux/types.h> + +#if defined(__KERNEL__) +#include <linux/mm_types.h> +#include <linux/bitops.h> +#else +#define BIT(nr) (1UL << (nr)) +#endif + +/** + * struct b2r2_blt_rect - Specifies a B2R2 rectangle + * + * @left: X-coordinate of top left corner + * @top: Y-coordinate of top left corner + * @width: Rectangle width. Must be >= 0. + * @height: Rectangle height. Must be >= 0. + */ +struct b2r2_blt_rect { + __s32 x; + __s32 y; + __s32 width; + __s32 height; +}; + +/** + * enum b2r2_blt_fmt - Defines the available B2R2 buffer formats + * + * Inspired by Khronos OpenMAX, please see + * OpenMAX IL specification for detailed descriptions of the formats + * + * @B2R2_BLT_FMT_UNUSED: Placeholder value when format is unknown, + * or specified using a vendor-specific means. + * @B2R2_BLT_FMT_16_BIT_ARGB4444: 16 bits per pixel ARGB format with colors + * stored as Alpha 15:12, Red 11:8, Green 7:4, and Blue 3:0. + * @B2R2_BLT_FMT_16_BIT_ARGB1555: 16 bits per pixel ARGB format with colors + * stored as Alpha 15, Red 14:10, Green 9:5, and Blue 4:0. + * @B2R2_BLT_FMT_16_BIT_RGB565: 16 bits per pixel RGB format with colors + * stored as Red 15:11, Green 10:5, and Blue 4:0. + * @B2R2_BLT_FMT_24_BIT_RGB888: 24 bits per pixel RGB format with colors + * stored as Red 23:16, Green 15:8, and Blue 7:0. + * @B2R2_BLT_FMT_32_BIT_ARGB8888: 32 bits per pixel ARGB format with colors + * stored as Alpha 31:24, Red 23:16, Green 15:8, and Blue 7:0. + * @B2R2_BLT_FMT_YUV420_PACKED_PLANAR: YUV planar format, organized with + * three separate planes for each color component, namely Y, U, and V. + * U and V pixels are sub-sampled by a factor of two both horizontally and + * vertically. The buffer shall contain a plane of Y, U, and V data in this + * order + * @B2R2_BLT_FMT_YUV422_PACKED_PLANAR: YUV planar format, organized with + * three separate planes for each color component, namely Y, U, and V. + * U and V pixels are subsampled by a factor of two horizontally. + * The buffer shall contain a plane of Y, U, and V data in this order. + * @B2R2_BLT_FMT_Y_CB_Y_CR: 16 bits per pixel YUV interleaved format organized + * as YUYV (i.e., YCbYCr). + * (Corresponds to YUV422 interleaved) + * @B2R2_BLT_FMT_CB_Y_CR_Y: 16 bits per pixel YUV interleaved format organized + * as UYVY (i.e., CbYCrY). + * (Corresponds to YUV422R) + * @B2R2_BLT_FMT_YUV420_PACKED_SEMI_PLANAR: YUV planar format, organized with + * a first plane containing Y pixels, and a second plane containing U and V + * pixels interleaved with the first U value first. U and V pixels are + * sub-sampled by a factor of two both horizontally and vertically. The buffer + * shall contain a plane of Y, U and V data. + * (Same as B2R2 420 Raster 2 buffer - 420 R2B) + * @B2R2_BLT_FMT_YUV422_PACKED_SEMI_PLANAR: YUV planar format, organized with + * a first plane containing Y pixels, and a second plane containing U and V + * pixels interleaved with the first U value first. U and V pixels are + * sub-sampled by a factor of two horizontally. The buffer shall contain a + * plane of Y, U and V data. + * (Same as B2R2 422 Raster 2 buffer - 422 R2B) + * @B2R2_BLT_FMT_32_BIT_ABGR8888: 32 bits per pixel ABGR format with colors + * stored as Alpha 31:24,Blue 23:16, Green 15:8, and Red 7:0. + * @B2R2_BLT_FMT_24_BIT_ARGB8565: 24 bits per pixel ARGB format with colors + * stored as Alpha 23:16, Red 15:11, Green 10:5, and Blue 4:0. + * @B2R2_BLT_FMT_24_BIT_YUV888: 24 bits per pixel YUV format with colors + * stored as Y 23:16, U 15:8, and V 7:0. + * @B2R2_BLT_FMT_32_BIT_AYUV8888: 32 bits per pixel AYUV format with colors + * stored as Alpha 31:24, Y 23:16, U 15:8, and V 7:0. + * @B2R2_BLT_FMT_YUV420_PACKED_SEMIPLANAR_MB_STE: Nomadik YUV 420 macro block + * format, see B2R2 spec for details + * @B2R2_BLT_FMT_YUV422_PACKED_SEMIPLANAR_MB_STE: Nomadik YUV 422 macro block + * format, see B2R2 spec for details + * @B2R2_BLT_FMT_1_BIT_A1: 1 bit per pixel A format, 1 bit alpha + * @B2R2_BLT_FMT_8_BIT_A8: 8 bit per pixel A format, 8 bit alpha + * @B2R2_BLT_FMT_YUV444_PACKED_PLANAR: YUV planar format, organized with + * three separate planes, one for each color component, namely Y, U, and V. + * All planes use full resolution, there is no subsampling. + * The buffer shall contain a plane of Y, U, and V data in this order. + * @B2R2_BLT_FMT_YVU420_PACKED_SEMI_PLANAR: YVU planar format, organized with + * a first plane containing Y pixels, and a second plane containing V and U + * pixels interleaved with the first V value first. V and U pixels are + * sub-sampled by a factor of two both horizontally and vertically. The buffer + * shall contain two planes, one plane with Y, and one with V and U data. + * (Same as B2R2 420 Raster 2 buffer - 420 R2B except that chroma order is + * swapped.) + * @B2R2_BLT_FMT_YVU422_PACKED_SEMI_PLANAR: YVU planar format, organized with + * a first plane containing Y pixels, and a second plane containing V and U + * pixels interleaved with the first V value first. V and U pixels are + * sub-sampled by a factor of two horizontally. The buffer shall contain a + * two planes, one with Y, and one with V and U data. + * (Same as B2R2 422 Raster 2 buffer - 422 R2B except that chroma order is + * swapped.) + * @B2R2_BLT_FMT_YVU420_PACKED_PLANAR: YVU planar format, organized with + * three separate planes for each color component, namely Y, V, and U. + * V and U pixels are sub-sampled by a factor of two both horizontally and + * vertically. The buffer shall contain a plane of Y, V, and U data in this + * order. (Same as B2R2_BLT_FMT_YUV420_PACKED_PLANAR except that chroma + * order is swapped.) + * @B2R2_BLT_FMT_YVU422_PACKED_PLANAR: YVU planar format, organized with + * three separate planes for each color component, namely Y, V, and U. + * V and U pixels are subsampled by a factor of two horizontally. + * The buffer shall contain a plane of Y, V, and U data in this order. + * (Same as B2R2_BLT_FMT_YUV422_PACKED_PLANAR except that chroma + * order is swapped.) + * @B2R2_BLT_FMT_24_BIT_VUY888: 24 bits per pixel VUY format with colors + * stored as V 23:16, U 15:8, and Y 7:0. + * @B2R2_BLT_FMT_32_BIT_VUYA8888: 32 bits per pixel VUYA format with colors + * stored as V 31:24, U 23:16, Y 15:8, and Alpha 7:0. + */ +enum b2r2_blt_fmt { + B2R2_BLT_FMT_UNUSED = 0, + B2R2_BLT_FMT_16_BIT_ARGB4444 = 4, + B2R2_BLT_FMT_16_BIT_ARGB1555 = 5, + B2R2_BLT_FMT_16_BIT_RGB565 = 6, + B2R2_BLT_FMT_24_BIT_RGB888 = 11, + B2R2_BLT_FMT_32_BIT_ARGB8888 = 16, + B2R2_BLT_FMT_YUV420_PACKED_PLANAR = 20, + B2R2_BLT_FMT_YUV422_PACKED_PLANAR = 23, + B2R2_BLT_FMT_Y_CB_Y_CR = 25, + B2R2_BLT_FMT_CB_Y_CR_Y = 27, + B2R2_BLT_FMT_YUV420_PACKED_SEMI_PLANAR = 39, + B2R2_BLT_FMT_YUV422_PACKED_SEMI_PLANAR = 40, + /* Extensions, non OpenMAX formats */ + B2R2_BLT_FMT_32_BIT_ABGR8888 = 0x7F000000, /* OpenMax vendor start */ + B2R2_BLT_FMT_24_BIT_ARGB8565 = 0x7F000001, + B2R2_BLT_FMT_24_BIT_YUV888 = 0x7F000002, + B2R2_BLT_FMT_32_BIT_AYUV8888 = 0x7F000003, + B2R2_BLT_FMT_YUV420_PACKED_SEMIPLANAR_MB_STE = 0x7F000004, + B2R2_BLT_FMT_YUV422_PACKED_SEMIPLANAR_MB_STE = 0x7F000005, + B2R2_BLT_FMT_1_BIT_A1 = 0x7F000006, + B2R2_BLT_FMT_8_BIT_A8 = 0x7F000007, + B2R2_BLT_FMT_YUV444_PACKED_PLANAR = 0x7F000008, + B2R2_BLT_FMT_YVU420_PACKED_SEMI_PLANAR = 0x7F000009, + B2R2_BLT_FMT_YVU422_PACKED_SEMI_PLANAR = 0x7F00000A, + B2R2_BLT_FMT_YVU420_PACKED_PLANAR = 0x7F00000B, + B2R2_BLT_FMT_YVU422_PACKED_PLANAR = 0x7F00000C, + B2R2_BLT_FMT_24_BIT_VUY888 = 0x7F00000D, + B2R2_BLT_FMT_32_BIT_VUYA8888 = 0x7F00000E, +}; + +/** + * enum b2r2_blt_ptr_type - Specifies a B2R2 buffer pointer type + * + * @B2R2_BLT_PTR_NONE: + * No pointer (NULL). E.g. src fill. + * @B2R2_BLT_PTR_VIRTUAL: + * Use offset as a userspace virtual address + * @B2R2_BLT_PTR_PHYSICAL: + * Use offset as a physical address + * @B2R2_BLT_PTR_FD_OFFSET: + * Use fd + offset to determine buffer location. + * @B2R2_BLT_PTR_HWMEM_BUF_NAME: + * Use hwmem_buf_name and offset to determine buffer location. + */ +enum b2r2_blt_ptr_type { + B2R2_BLT_PTR_NONE, + B2R2_BLT_PTR_VIRTUAL, + B2R2_BLT_PTR_PHYSICAL, + B2R2_BLT_PTR_FD_OFFSET, + B2R2_BLT_PTR_HWMEM_BUF_NAME_OFFSET, +}; + +/** + * struct b2r2_blt_buf - Specifies a B2R2 buffer pointer + * + * @type: Buffer pointer type + * @hwmem_global_buf_id: Hwmem buffer name + * @fd: File descriptor (e.g. file handle to pmem or fb device) + * @offset: Offset where buffer can be found or address. + * @len: Size of buffer in bytes + * @bits: Pointer to the bitmap data. This field can be used to specify + * an alternative way to access the buffer. Whenever the 'bits' pointer + * is set to non-NULL, the underlying implementation is free to decide + * whether or not to use it in favor of other ways to locate the buffer. + */ +struct b2r2_blt_buf { + enum b2r2_blt_ptr_type type; + __s32 hwmem_buf_name; + __s32 fd; + __u32 offset; + __u32 len; + void *bits; +}; + + +/** + * struct b2r2_blt_img - Specifies a B2R2 image + * + * @fmt: Pixel format of image + * @buf: Pixel buffer + * @width: Width in pixels + * @height: Height in pixels + * @pitch: Pitch in bytes (from start of one line to start of next) + */ +struct b2r2_blt_img { + enum b2r2_blt_fmt fmt; + struct b2r2_blt_buf buf; + __s32 width; + __s32 height; + __u32 pitch; +}; + + +/** + * enum b2r2_blt_transform- Specifies rotation and flipping, mutually exclusive + * @B2R2_BLT_TRANSFORM_NONE: + * No rotation or flip + * @B2R2_BLT_TRANSFORM_FLIP_H + * Flip horizontally + * @B2R2_BLT_TRANSFORM_FLIP_V + * Flip vertically + * @B2R2_BLT_TRANSFORM_CCW_ROT_90 + * Rotate 90 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_CCW_ROT_180 + * Rotate 180 degrees (same as flip horizontally together with + * flip vertically) + * @B2R2_BLT_TRANSFORM_CCW_ROT_270 + * Rotate 270 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_FLIP_H_CCW_ROT_90 + * Flip horizontally and then rotate 90 degrees counter clockwise + * @B2R2_BLT_TRANSFORM_FLIP_V_CCW_ROT_90 + * Flip vertically and then rotate 90 degrees counter clockwise + */ +enum b2r2_blt_transform { + B2R2_BLT_TRANSFORM_NONE = 0, + B2R2_BLT_TRANSFORM_FLIP_H = 1, + B2R2_BLT_TRANSFORM_FLIP_V = 2, + B2R2_BLT_TRANSFORM_CCW_ROT_90 = 4, + B2R2_BLT_TRANSFORM_CCW_ROT_180 = 3, + B2R2_BLT_TRANSFORM_CCW_ROT_270 = 7, + B2R2_BLT_TRANSFORM_FLIP_H_CCW_ROT_90 = 5, + B2R2_BLT_TRANSFORM_FLIP_V_CCW_ROT_90 = 6, +}; + + +/** + * enum b2r2_blt_flag - Flags that controls the B2R2 request + * + * Can be combined. + * + * @B2R2_BLT_FLAG_ASYNCH: + * Asynchronous request. b2r2_blt will returns when the request + * has been queued. + * @B2R2_BLT_FLAG_DRY_RUN: + * Dry run, just to check if request can be performed. + * @B2R2_BLT_FLAG_PER_PIXEL_ALPHA_BLEND: + * Enable per pixel alpha blend + * @B2R2_BLT_FLAG_GLOBAL_ALPHA_BLEND: + * Enable global alpha blend (alpha value in global_alpha) + * @B2R2_BLT_FLAG_SOURCE_COLOR_KEY: + * Enable source color key (color in src_color). Color should be in raw + * format. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY and B2R2_BLT_FLAG_DEST_COLOR_KEY cannot be + * specified at the same time. + * @B2R2_BLT_FLAG_SOURCE_FILL: + * Enable ARGB/AYUV source fill (color in src_color). Which of ARGB and AYUV + * is determined by the destination format. + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time + * @B2R2_BLT_FLAG_SOURCE_FILL_RAW: + * Enable raw color source fill (color in src_color) + * B2R2_BLT_FLAG_SOURCE_COLOR_KEY, B2R2_BLT_FLAG_SOURCE_FILL and + * B2R2_BLT_FLAG_SOURCE_FILL_RAW cannot be specified at the same time + * @B2R2_BLT_FLAG_DEST_COLOR_KEY: + * Enable dest color key (color in dst_color). Color in raw format. + * @B2R2_BLT_FLAG_SRC_IS_NOT_PREMULT: + * Source color not premultiplied (Valid for alpha formats only). + * @B2R2_BLT_FLAG_DITHER: + * Enable dithering + * @B2R2_BLT_FLAG_BLUR: + * Enable blur + * @B2R2_BLT_FLAG_SOURCE_MASK: + * Enable source mask + * @B2R2_BLT_FLAG_DESTINATION_CLIP: + * Enable destination clip rectangle + * @B2R2_BLT_FLAG_INHERIT_PRIO + * Inherit process priority + * @B2R2_BLT_FLAG_SRC_NO_CACHE_FLUSH + * Skip cache flush of source image buffer + * @B2R2_BLT_FLAG_SRC_MASK_NO_CACHE_FLUSH + * Skip cache flush of source mask buffer + * @B2R2_BLT_FLAG_DST_NO_CACHE_FLUSH + * Skip cache flush of destination image buffer + * @B2R2_BLT_FLAG_BG_BLEND + * Indicate that a background buffer is supplied + * to the blit operation. B2R2_BLT_FLAG_PER_PIXEL_ALPHA_BLEND, + * B2R2_BLT_FLAG_SRC_IS_NOT_PREMULT, and + * B2R2_BLT_FLAG_GLOBAL_ALPHA_BLEND will control the blend operation. + * The destination blending is in this case disabled and the destination + * buffer will be overwritten with the source and background blend result. + * @B2R2_BLT_FLAG_BG_NO_CACHE_FLUSH + * Skip cache flush of background image buffer + * @B2R2_BLT_FLAG_REPORT_WHEN_DONE + * Report through b2r2_blt file when done. A b2r2_blt_report structure is + * read. Use poll() or select() if anything to read. (i.e. to help user space + * to implement callback functionality) + * @B2R2_BLT_FLAG_REPORT_PERFORMANCE + * Include performance data in the report structure + * @B2R2_BLT_FLAG_CLUT_COLOR_CORRECTION + * Use color look-up table for color correction. + * Pointer to the table must be specified in *clut field of + * the b2r2_blt_req structure. + * The table must map all input color values + * for each channel to the desired output values. + * It is an array with the following format: + * R0 G0 B0 A0 R1 G1 B1 A1...R255 G255 B255 A255 + * where R0 is the 8 bit output value for red channel whenever its input + * equals 0. + * Similarly, R1 through R255 are the red channel outputs whenever + * the channel's inputs equal 1 through 255 respectively. + * Gn, Bn, An denote green, blue and alpha channel. + * Whenever the input bitmap format lacks the alpha channel, + * all alpha values in the color correction table should be set to 255. + * Size of the array that specifies the color correction table + * must be 1024 bytes. + * A table that does not change anything has the form: + * 0 0 0 0 1 1 1 1 2 2 2 2 ... 254 254 254 254 255 255 255 255. + * CLUT color correction can be applied to YUV raster buffers as well, + * in which case the RGB color channels are mapped onto YUV-space + * as follows: + * R = red chrominance + * G = luminance + * B = blue chrominance + * A = alpha + * If any of the planar or semi-planar formats is used, luminance cannot + * be changed by the color correction table. + */ +enum b2r2_blt_flag { + B2R2_BLT_FLAG_ASYNCH = BIT(0),/*0x1*/ + B2R2_BLT_FLAG_DRY_RUN = BIT(1),/*0x2*/ + B2R2_BLT_FLAG_PER_PIXEL_ALPHA_BLEND = BIT(2),/*0x4*/ + B2R2_BLT_FLAG_GLOBAL_ALPHA_BLEND = BIT(3),/*0x8*/ + B2R2_BLT_FLAG_SOURCE_COLOR_KEY = BIT(4),/*0x10*/ + B2R2_BLT_FLAG_SOURCE_FILL = BIT(5),/*0x20*/ + B2R2_BLT_FLAG_SOURCE_FILL_RAW = BIT(6),/*0x40*/ + B2R2_BLT_FLAG_DEST_COLOR_KEY = BIT(7),/*0x80*/ + B2R2_BLT_FLAG_SRC_IS_NOT_PREMULT = BIT(8),/*0x100*/ + B2R2_BLT_FLAG_DITHER = BIT(9),/*0x200*/ + B2R2_BLT_FLAG_BLUR = BIT(10),/*0x400*/ + B2R2_BLT_FLAG_SOURCE_MASK = BIT(11),/*0x800*/ + B2R2_BLT_FLAG_DESTINATION_CLIP = BIT(12),/*0x1000*/ + B2R2_BLT_FLAG_INHERIT_PRIO = BIT(13),/*0x2000*/ + B2R2_BLT_FLAG_SRC_NO_CACHE_FLUSH = BIT(14),/*0x4000*/ + B2R2_BLT_FLAG_SRC_MASK_NO_CACHE_FLUSH = BIT(15),/*0x8000*/ + B2R2_BLT_FLAG_DST_NO_CACHE_FLUSH = BIT(16),/*0x10000*/ + B2R2_BLT_FLAG_BG_BLEND = BIT(17),/*0x20000*/ + B2R2_BLT_FLAG_BG_NO_CACHE_FLUSH = BIT(18),/*0x40000*/ + B2R2_BLT_FLAG_REPORT_WHEN_DONE = BIT(29),/*0x20000000*/ + B2R2_BLT_FLAG_REPORT_PERFORMANCE = BIT(30),/*0x40000000*/ + B2R2_BLT_FLAG_CLUT_COLOR_CORRECTION = BIT(31),/*0x80000000*/ +}; + + +/** + * struct b2r2_blt_req - Specifies a request to B2R2 + * + * @size: Size of this structure. Used for versioning. MUST be specified. + * @flags: Flags that control the B2R2 request ORed together + * @tfm: How source should be flipped and rotated when blitting + * @prio: Priority (-20 to 19). Inherits process prio + * if B2R2_BLT_FLAG_INHERIT_PRIO. Given priority is mapped onto B2R2. + * TBD: How? + * @clut: Pointer to the look-up table for color correction. + * @src_img: Source image. Not used if source fill. + * @src_mask: Source mask. Not used if source fill. + * @src_rect: Source area to be blitted. + * @src_color: Source fill color or color key + * @bg_img: Background image. + * @bg_rect: Background area to blend with. + * @dst_img: Destination image. + * @dst_rect: Destination area to be blitted to. + * @dst_color: Destination color key + * @dst_clip_rect: Destination clip rectangle. + * @global_alpha: Global alpha value (0 - 255) + * @report1: Data 1 to report back when request is done. + * See struct b2r2_blt_report. + * @report2: Data 2 to report back when request is done. + * See struct b2r2_blt_report. + * + */ +struct b2r2_blt_req { + __u32 size; + enum b2r2_blt_flag flags; + enum b2r2_blt_transform transform; + __s32 prio; + void *clut; + struct b2r2_blt_img src_img; + struct b2r2_blt_img src_mask; + struct b2r2_blt_rect src_rect; + __u32 src_color; + struct b2r2_blt_img bg_img; + struct b2r2_blt_rect bg_rect; + struct b2r2_blt_img dst_img; + struct b2r2_blt_rect dst_rect; + struct b2r2_blt_rect dst_clip_rect; + __u32 dst_color; + __u8 global_alpha; + __u32 report1; + __u32 report2; +}; + +/** + * enum b2r2_blt_cap - Capabilities that can be queried for. + * + * Capabilities can be queried for a specific format or for formats in + * general. To query for capabilities in general, specify BLT_FMT_UNUSED + * as format. + * + * B2R2_BLT_CAP_UNUSED: Unused/unspecified capability + * B2R2_BLT_CAP_FMT_SOURCE: Is format supported as source? + * B2R2_BLT_CAP_FMT_SOURCE_MASK: Is format supported as source mask? + * B2R2_BLT_CAP_FMT_DEST: Is format supported as dest? + * B2R2_BLT_CAP_PER_PIXEL_ALPHA_BLEND: Is per pixel alpha blending supported + * with format as source + * B2R2_BLT_CAP_GLOBAL_ALPHA_BLEND: Is per global alpha blending supported + * with format as source + * B2R2_BLT_CAP_SOURCE_COLOR_KEY: Is source color key supported with format as + * source + * B2R2_BLT_CAP_SOURCE_FILL: Is source fill supported with format as source + * B2R2_BLT_CAP_SOURCE_FILL_RAW: Is source fill raw supported with format as + * dest + * B2R2_BLT_CAP_DEST_COLOR_KEY: Is dest color key supported with format as dest + * B2R2_BLT_CAP_DITHER: Is dithering supported with format as source + * B2R2_BLT_CAP_BLUR: Is blur supported with format as source + * B2R2_BLT_CAP_MINIFICATION_LIMIT: Minification limit (copybit support) + * B2R2_BLT_CAP_MAGNIFICATION_LIMIT: Magnification limit (copybit support) + * B2R2_BLT_CAP_SCALING_FRAC_BITS: Number of scaling fractional bits (copybit + * support) + * B2R2_BLT_CAP_ROTATION_STEP_DEG: Supported rotation step in degrees (copybit + * support) + */ + +enum b2r2_blt_cap { + B2R2_BLT_CAP_UNUSED = 0, + /** + * @brief Is format supported as source. + */ + B2R2_BLT_CAP_FMT_SOURCE, + /** + * @brief Is format supported as source mask + */ + B2R2_BLT_CAP_FMT_SOURCE_MASK, + /** + * @brief Is format supported as destination + */ + B2R2_BLT_CAP_FMT_DEST, + /** + * @brief Is per pixel alpha blending supported with format as source + */ + B2R2_BLT_CAP_PER_PIXEL_ALPHA_BLEND, + /** + * @brief Is global alpha blending supported with format as source + */ + B2R2_BLT_CAP_GLOBAL_ALPHA_BLEND, + /** + * @brief Is source color key supported with format as source + */ + B2R2_BLT_CAP_SOURCE_COLOR_KEY, + /** + * @brief Is source fill supported with format as source + */ + B2R2_BLT_CAP_SOURCE_FILL, + /** + * @brief Is source fill raw supported with format as dest + */ + B2R2_BLT_CAP_SOURCE_FILL_RAW, + /** + * @brief Is dest color key supported with format as dest + */ + B2R2_BLT_CAP_DEST_COLOR_KEY, + /** + * @brief Is dithering supported with format as source + */ + B2R2_BLT_CAP_DITHER, + /** + * @brief Is blur supported with format as source + */ + B2R2_BLT_CAP_BLUR, + /** + * @brief Minification limit (copybit support) + */ + B2R2_BLT_CAP_MINIFICATION_LIMIT, + /** + * @brief Magnification limit (copybit support) + */ + B2R2_BLT_CAP_MAGNIFICATION_LIMIT, + /** + * @brief Number of scaling fractional bits (copybit support) + */ + B2R2_BLT_CAP_SCALING_FRAC_BITS, + /** + * @brief Supported rotation step in degrees (copybit support) + */ + B2R2_BLT_CAP_ROTATION_STEP_DEG, +}; + +/** + * struct b2r2_blt_query_cap - Query B2R2 capabilities + * + * fmt: Format to query capabilities for or BLT_FMT_UNUSED for all + * cap: Capability to query for + * result: Returned capability. Interpretaion of this variable varies + * with the capability queried + */ +struct b2r2_blt_query_cap { + enum b2r2_blt_fmt fmt; + enum b2r2_blt_cap cap; + __u32 result; +}; + +/** + * struct b2r2_blt_report - Report from B2R2 driver back to user space + * + * This structure can be read from B2R2 driver if B2R2_BLT_FLAG_REPORT_WHEN_DONE + * flag was specified when the request was issued. + * + * @request_id: The id for the request, same as reported from blt_request + * @report1: Client data specified in struct blt_request + * @report2: Client data specified in struct blt_request + * @usec_elapsed: Number of microseconds needed to perform this blit + * if B2R2_BLT_FLAG_REPORT_PERFORMANCE was specified when the + * request was issued. + * + */ +struct b2r2_blt_report { + __u32 request_id; + __u32 report1; + __u32 report2; + __u32 usec_elapsed; +}; + +/** + * B2R2 BLT driver is used in the following way: + * + * Obtain a file descriptor to the driver: + * fd = open("/dev/b2r2_blt", O_RDWR); + * + * Issue requests: + * struct b2r2_blt_request blt_request; + * blt_request.size = sizeof(blt_request); + * ... Fill request with data... + * + * request_id = ioctl(fd, B2R2_BLT_IOC, (__u32) &blt_request); + * + * Wait for a request to finish + * ret = ioctl(fd, B2R2_BLT_SYNCH_IOC, (__u32) request_id); + * + * Wait for all requests from this context to finish + * ret = ioctl(fd, B2R2_BLT_SYNCH_IOC, (__u32) 0); + * + * Wait indefinitely for report data from driver: + * pollfd.fd = fd + * pollfd.events = 0xFFFFFFFF; + * pollfd.revents = 0; + * ret = poll(&pollfd, 1, -1); + * + * Read report data from driver + * struct b2r2_blt_report blt_report; + * + * nread = read(fd, &blt_report, sizeof(blt_report)); + * + * Close the driver + * close(fd); + */ + +/* B2R2 BLT IOCTLS */ + +/** + * B2R2_BLT_IOC_MAGIC is ioctl type group for B2R2 driver + */ +#define B2R2_BLT_IOC_MAGIC 0xb2 + +/** + * The B2R2_BLT_IOC ioctl adds a blit request to B2R2. + * + * The ioctl returns when the blit has been performed if not + * asynchronous execution has been specified. If asynchronous, + * control is returned as soon as the request has been queued. + * + * Supplied parameter shall be a pointer to a struct b2r2_blt_req. + * + * Returns an unique request id if >= 0, else a negative error code. + * This request id can be waited for using B2R2_BLT_SYNC_IOC. + * Return values: -ESOMERROR Description of an error + */ +#define B2R2_BLT_IOC _IOW(B2R2_BLT_IOC_MAGIC, 1, struct b2r2_blt_req) + +/** + * The B2R2_BLT_SYNC_IOC waits for all or a specified request to be finished. + * + * Supplied parameter shall be a request id previously returned by + * B2R2_BLT_IOC or 0 for all requests. + * + * Returns 0 if OK, else a negative error code + * Return value: -ESOMERROR Description of an error + */ +#define B2R2_BLT_SYNCH_IOC _IOW(B2R2_BLT_IOC_MAGIC, 2, int) + +/** + * The BLT_QUERY_CAP_IOC returns capability information for all or + * for a certain format + * + * Supplied parameter shall be a pointer to a struct b2r2_blt_query_cap. + * + * @return Returns 0 if OK, else a negative error code + * @retval -ESOMERROR Description of an error + */ +#define B2R2_BLT_QUERY_CAP_IOC _IOWR(B2R2_BLT_IOC_MAGIC, 3, \ + struct b2r2_blt_query_cap) + +#endif /* #ifdef _LINUX_VIDEO_B2R2_BLT_H */ diff --git a/include/video/hdmi.h b/include/video/hdmi.h new file mode 100644 index 00000000000..55dcd003fcd --- /dev/null +++ b/include/video/hdmi.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * HDMI driver + * + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __HDMI__H__ +#define __HDMI__H__ + +#define HDMI_RESULT_OK 0 +#define HDMI_RESULT_NOT_OK 1 +#define HDMI_AES_NOT_FUSED 2 +#define HDMI_RESULT_CRC_MISMATCH 3 + +#define HDMI_CEC_READ_MAXSIZE 16 +#define HDMI_CEC_WRITE_MAXSIZE 15 +#define HDMI_INFOFRAME_MAX_SIZE 27 +#define HDMI_HDCP_FUSEAES_KEYSIZE 16 +#define HDMI_HDCP_AES_BLOCK_START 128 +#define HDMI_HDCP_KSV_BLOCK 40 +#define HDMI_HDCP_AES_NR_OF_BLOCKS 18 +#define HDMI_HDCP_AES_KEYSIZE 16 +#define HDMI_HDCP_AES_KSVSIZE 5 +#define HDMI_HDCP_AES_KSVZEROESSIZE 3 +#define HDMI_EDID_DATA_SIZE 128 +#define HDMI_CEC_SIZE 15 +#define HDMI_INFOFR_SIZE 27 +#define HDMI_FUSE_KEYSIZE 16 +#define HDMI_AES_KSVSIZE 5 +#define HDMI_AES_KEYSIZE 288 +#define HDMI_CRC32_SIZE 4 +#define HDMI_HDCPAUTHRESP_SIZE 126 + +#define HDMI_STOREASTEXT_TEXT_SIZE 2 +#define HDMI_STOREASTEXT_BIN_SIZE 1 +#define HDMI_PLUGDETEN_TEXT_SIZE 6 +#define HDMI_PLUGDETEN_BIN_SIZE 3 +#define HDMI_EDIDREAD_TEXT_SIZE 4 +#define HDMI_EDIDREAD_BIN_SIZE 2 +#define HDMI_CECEVEN_TEXT_SIZE 2 +#define HDMI_CECEVEN_BIN_SIZE 1 +#define HDMI_CECSEND_TEXT_SIZE_MAX 37 +#define HDMI_CECSEND_TEXT_SIZE_MIN 6 +#define HDMI_CECSEND_BIN_SIZE_MAX 18 +#define HDMI_CECSEND_BIN_SIZE_MIN 3 +#define HDMI_INFOFRSEND_TEXT_SIZE_MIN 8 +#define HDMI_INFOFRSEND_TEXT_SIZE_MAX 63 +#define HDMI_INFOFRSEND_BIN_SIZE_MIN 4 +#define HDMI_INFOFRSEND_BIN_SIZE_MAX 31 +#define HDMI_HDCPEVEN_TEXT_SIZE 2 +#define HDMI_HDCPEVEN_BIN_SIZE 1 +#define HDMI_HDCP_FUSEAES_TEXT_SIZE 34 +#define HDMI_HDCP_FUSEAES_BIN_SIZE 17 +#define HDMI_HDCP_LOADAES_TEXT_SIZE 594 +#define HDMI_HDCP_LOADAES_BIN_SIZE 297 +#define HDMI_HDCPAUTHENCR_TEXT_SIZE 4 +#define HDMI_HDCPAUTHENCR_BIN_SIZE 2 +#define HDMI_EVCLR_TEXT_SIZE 2 +#define HDMI_EVCLR_BIN_SIZE 1 +#define HDMI_AUDIOCFG_TEXT_SIZE 14 +#define HDMI_AUDIOCFG_BIN_SIZE 7 +#define HDMI_POWERONOFF_TEXT_SIZE 2 +#define HDMI_POWERONOFF_BIN_SIZE 1 + +#define HDMI_IOC_MAGIC 0xcc + +/** IOCTL Operations */ +#define IOC_PLUG_DETECT_ENABLE _IOWR(HDMI_IOC_MAGIC, 1, int) +#define IOC_EDID_READ _IOWR(HDMI_IOC_MAGIC, 2, int) +#define IOC_CEC_EVENT_ENABLE _IOWR(HDMI_IOC_MAGIC, 3, int) +#define IOC_CEC_READ _IOWR(HDMI_IOC_MAGIC, 4, int) +#define IOC_CEC_SEND _IOWR(HDMI_IOC_MAGIC, 5, int) +#define IOC_INFOFRAME_SEND _IOWR(HDMI_IOC_MAGIC, 6, int) +#define IOC_HDCP_EVENT_ENABLE _IOWR(HDMI_IOC_MAGIC, 7, int) +#define IOC_HDCP_CHKAESOTP _IOWR(HDMI_IOC_MAGIC, 8, int) +#define IOC_HDCP_FUSEAES _IOWR(HDMI_IOC_MAGIC, 9, int) +#define IOC_HDCP_LOADAES _IOWR(HDMI_IOC_MAGIC, 10, int) +#define IOC_HDCP_AUTHENCR_REQ _IOWR(HDMI_IOC_MAGIC, 11, int) +#define IOC_HDCP_STATE_GET _IOWR(HDMI_IOC_MAGIC, 12, int) +#define IOC_EVENTS_READ _IOWR(HDMI_IOC_MAGIC, 13, int) +#define IOC_EVENTS_CLEAR _IOWR(HDMI_IOC_MAGIC, 14, int) +#define IOC_AUDIO_CFG _IOWR(HDMI_IOC_MAGIC, 15, int) +#define IOC_PLUG_STATUS _IOWR(HDMI_IOC_MAGIC, 16, int) +#define IOC_POWERONOFF _IOWR(HDMI_IOC_MAGIC, 17, int) +#define IOC_EVENT_WAKEUP _IOWR(HDMI_IOC_MAGIC, 18, int) +#define IOC_POWERSTATE _IOWR(HDMI_IOC_MAGIC, 19, int) + + +/* HDMI driver */ +void hdmi_event(enum av8100_hdmi_event); +int hdmi_init(void); +void hdmi_exit(void); + +enum hdmi_event { + HDMI_EVENT_NONE = 0x0, + HDMI_EVENT_HDMI_PLUGIN = 0x1, + HDMI_EVENT_HDMI_PLUGOUT = 0x2, + HDMI_EVENT_CEC = 0x4, + HDMI_EVENT_HDCP = 0x8, + HDMI_EVENT_CECTXERR = 0x10, + HDMI_EVENT_WAKEUP = 0x20, + HDMI_EVENT_CECTX = 0x40, +}; + +enum hdmi_hdcp_auth_type { + HDMI_HDCP_AUTH_OFF = 0, + HDMI_HDCP_AUTH_START = 1, + HDMI_HDCP_AUTH_REV_LIST_REQ = 2, + HDMI_HDCP_AUTH_CONT = 3, +}; + +enum hdmi_hdcp_encr_type { + HDMI_HDCP_ENCR_OESS = 0, + HDMI_HDCP_ENCR_EESS = 1, +}; + +struct plug_detect { + __u8 hdmi_detect_enable; + __u8 on_time; + __u8 hdmi_off_time; +}; + +struct edid_read { + __u8 address; + __u8 block_nr; + __u8 data_length; + __u8 data[HDMI_EDID_DATA_SIZE]; +}; + +struct cec_rw { + __u8 src; + __u8 dest; + __u8 length; + __u8 data[HDMI_CEC_SIZE]; +}; + +struct info_fr { + __u8 type; + __u8 ver; + __u8 crc; + __u8 length; + __u8 data[HDMI_INFOFR_SIZE]; +}; + +struct hdcp_fuseaes { + __u8 key[HDMI_FUSE_KEYSIZE]; + __u8 crc; + __u8 result; +}; + +struct hdcp_loadaesall { + __u8 key[HDMI_AES_KEYSIZE]; + __u8 ksv[HDMI_AES_KSVSIZE]; + __u8 crc32[HDMI_CRC32_SIZE]; + __u8 result; +}; + + +/* hdcp_authencr resp coding + * + * When encr_type is 2 (request revoc list), the response is given by + * resp_size is != 0 and resp containing the folllowing: + * + * __u8[5] Bksv from sink (not belonging to revocation list) + * __u8 Device count + * Additional output if Nrofdevices > 0: + * __u8[5 * Nrofdevices] Bksv per connected equipment + * __u8[20] SHA signature + * + * Device count coding: + * 0 = a simple receiver is connected + * 0x80 = a repeater is connected without downstream equipment + * 0x81 = a repeater is connected with one downstream equipment + * up to 0x94 = (0x80 + 0x14) a repeater is connected with downstream + * equipment (thus up to 20 connected equipments) + * 1 = repeater without sink equipment connected + * >1 = number of connected equipment on the repeater + * Nrofdevices = Device count & 0x7F (max 20) + * + * Max resp_size is 5 + 1 + 5 * 20 + 20 = 126 bytes + * + */ +struct hdcp_authencr { + __u8 auth_type; + __u8 encr_type; + __u8 result; + __u8 resp_size; + __u8 resp[HDMI_HDCPAUTHRESP_SIZE]; +}; + +struct audio_cfg { + __u8 if_format; + __u8 i2s_entries; + __u8 freq; + __u8 word_length; + __u8 format; + __u8 if_mode; + __u8 mute; +}; + +#endif /* __HDMI__H__ */ diff --git a/include/video/mcde.h b/include/video/mcde.h new file mode 100644 index 00000000000..015350f4495 --- /dev/null +++ b/include/video/mcde.h @@ -0,0 +1,391 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE base driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE__H__ +#define __MCDE__H__ + +/* Physical interface types */ +enum mcde_port_type { + MCDE_PORTTYPE_DSI = 0, + MCDE_PORTTYPE_DPI = 1, +}; + +/* Interface mode */ +enum mcde_port_mode { + MCDE_PORTMODE_CMD = 0, + MCDE_PORTMODE_VID = 1, +}; + +/* MCDE fifos */ +enum mcde_fifo { + MCDE_FIFO_A = 0, + MCDE_FIFO_B = 1, + MCDE_FIFO_C0 = 2, + MCDE_FIFO_C1 = 3, +}; + +/* MCDE channels (pixel pipelines) */ +enum mcde_chnl { + MCDE_CHNL_A = 0, + MCDE_CHNL_B = 1, + MCDE_CHNL_C0 = 2, + MCDE_CHNL_C1 = 3, +}; + +/* Update sync mode */ +enum mcde_sync_src { + MCDE_SYNCSRC_OFF = 0, /* No sync */ + MCDE_SYNCSRC_TE0 = 1, /* MCDE ext TE0 */ + MCDE_SYNCSRC_TE1 = 2, /* MCDE ext TE1 */ + MCDE_SYNCSRC_BTA = 3, /* DSI BTA */ + MCDE_SYNCSRC_TE_POLLING = 4, /* DSI TE_POLLING */ + MCDE_SYNCSRC_FORMATTER = 5, /* Sync from formatter */ +}; + +/* Interface pixel formats (output) */ +/* +* REVIEW: Define formats +* Add explanatory comments how the formats are ordered in memory +*/ +enum mcde_port_pix_fmt { + /* MIPI standard formats */ + + MCDE_PORTPIXFMT_DPI_16BPP_C1 = 0x21, + MCDE_PORTPIXFMT_DPI_16BPP_C2 = 0x22, + MCDE_PORTPIXFMT_DPI_16BPP_C3 = 0x23, + MCDE_PORTPIXFMT_DPI_18BPP_C1 = 0x24, + MCDE_PORTPIXFMT_DPI_18BPP_C2 = 0x25, + MCDE_PORTPIXFMT_DPI_24BPP = 0x26, + + MCDE_PORTPIXFMT_DSI_16BPP = 0x31, + MCDE_PORTPIXFMT_DSI_18BPP = 0x32, + MCDE_PORTPIXFMT_DSI_18BPP_PACKED = 0x33, + MCDE_PORTPIXFMT_DSI_24BPP = 0x34, + + /* Custom formats */ + MCDE_PORTPIXFMT_DSI_YCBCR422 = 0x40, +}; + +enum mcde_hdmi_sdtv_switch { + HDMI_SWITCH, + SDTV_SWITCH, + DVI_SWITCH +}; + +enum mcde_col_convert { + MCDE_CONVERT_RGB_2_RGB, + MCDE_CONVERT_RGB_2_YCBCR, + MCDE_CONVERT_YCBCR_2_RGB, + MCDE_CONVERT_YCBCR_2_YCBCR, +}; + +struct mcde_col_transform { + u16 matrix[3][3]; + u16 offset[3]; +}; + +/* DSI video mode */ +enum mcde_dsi_vid_mode { + NON_BURST_MODE_WITH_SYNC_EVENT = 0, + /* enables tvg, test video generator */ + NON_BURST_MODE_WITH_SYNC_EVENT_TVG_ENABLED = 1, + BURST_MODE_WITH_SYNC_EVENT = 2, + BURST_MODE_WITH_SYNC_PULSE = 3, +}; + +#define MCDE_PORT_DPI_NO_CLOCK_DIV 0 + +#define DPI_ACT_HIGH_ALL 0 /* all signals are active high */ +#define DPI_ACT_LOW_HSYNC 1 /* horizontal sync signal is active low */ +#define DPI_ACT_LOW_VSYNC 2 /* vertical sync signal is active low */ +#define DPI_ACT_LOW_DATA_ENABLE 4 /* data enable signal is active low */ +#define DPI_ACT_ON_FALLING_EDGE 8 /* drive data on the falling edge of the + * pixel clock + */ + +struct mcde_port { + enum mcde_port_type type; + enum mcde_port_mode mode; + enum mcde_port_pix_fmt pixel_format; + u8 refresh_rate; /* display refresh rate given in Hz */ + u8 ifc; + u8 link; + enum mcde_sync_src sync_src; + bool update_auto_trig; + enum mcde_hdmi_sdtv_switch hdmi_sdtv_switch; + union { + struct { + u8 virt_id; + u8 num_data_lanes; + u8 ui; + bool clk_cont; + bool host_eot_gen; + + /* DSI video mode operating modes */ + enum mcde_dsi_vid_mode vid_mode; + + /* + * wakeup_time is the time to perform + * LP->HS on D-PHY. Given in clock + * cycles of byte clock frequency. + */ + u32 vid_wakeup_time; + + u32 hs_freq; + u32 lp_freq; + + /* DSI data lanes are swapped if true */ + bool data_lanes_swap; + } dsi; + struct { + u8 bus_width; + bool tv_mode; + u16 clock_div; /* use 0 or 1 for no clock divider */ + u32 polarity; /* see DPI_ACT_LOW_* definitions */ + u32 lcd_freq; + } dpi; + } phy; +}; + +/* Overlay pixel formats (input) *//* REVIEW: Define byte order */ +enum mcde_ovly_pix_fmt { + MCDE_OVLYPIXFMT_RGB565 = 1, + MCDE_OVLYPIXFMT_RGBA5551 = 2, + MCDE_OVLYPIXFMT_RGBA4444 = 3, + MCDE_OVLYPIXFMT_RGB888 = 4, + MCDE_OVLYPIXFMT_RGBX8888 = 5, + MCDE_OVLYPIXFMT_RGBA8888 = 6, + MCDE_OVLYPIXFMT_YCbCr422 = 7, +}; + +/* Display power modes */ +enum mcde_display_power_mode { + MCDE_DISPLAY_PM_OFF = 0, /* Power off */ + MCDE_DISPLAY_PM_STANDBY = 1, /* DCS sleep mode */ + MCDE_DISPLAY_PM_ON = 2, /* DCS normal mode, display on */ +}; + +/* Display rotation */ +enum mcde_display_rotation { + MCDE_DISPLAY_ROT_0 = 0, + MCDE_DISPLAY_ROT_90_CCW = 90, + MCDE_DISPLAY_ROT_180_CCW = 180, + MCDE_DISPLAY_ROT_270_CCW = 270, + MCDE_DISPLAY_ROT_90_CW = MCDE_DISPLAY_ROT_270_CCW, + MCDE_DISPLAY_ROT_180_CW = MCDE_DISPLAY_ROT_180_CCW, + MCDE_DISPLAY_ROT_270_CW = MCDE_DISPLAY_ROT_90_CCW, +}; + +/* REVIEW: Verify */ +#define MCDE_MIN_WIDTH 16 +#define MCDE_MIN_HEIGHT 16 +#define MCDE_MAX_WIDTH 2048 +#define MCDE_MAX_HEIGHT 2048 +#define MCDE_BUF_START_ALIGMENT 8 +#define MCDE_BUF_LINE_ALIGMENT 8 + +/* Tv-out defines */ +#define MCDE_CONFIG_TVOUT_BACKGROUND_LUMINANCE 0x83 +#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CB 0x9C +#define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CR 0x2C + +/* In seconds */ +#define MCDE_AUTO_SYNC_WATCHDOG 5 + +/* DSI modes */ +#define DSI_VIDEO_MODE 0 +#define DSI_CMD_MODE 1 + +/* Video mode descriptor */ +struct mcde_video_mode { + u32 xres; + u32 yres; + u32 pixclock; /* pixel clock in ps (pico seconds) */ + u32 hbp; /* horizontal back porch: left margin (excl. hsync) */ + u32 hfp; /* horizontal front porch: right margin (excl. hsync) */ + u32 hsw; /* horizontal sync width */ + u32 vbp; /* vertical back porch: upper margin (excl. vsync) */ + u32 vfp; /* vertical front porch: lower margin (excl. vsync) */ + u32 vsw; /* vertical sync width*/ + bool interlaced; + bool force_update; /* when switching between hdmi and sdtv */ +}; + +struct mcde_rectangle { + u16 x; + u16 y; + u16 w; + u16 h; +}; + +struct mcde_overlay_info { + u32 paddr; + u32 *vaddr; + u16 stride; /* buffer line len in bytes */ + enum mcde_ovly_pix_fmt fmt; + + u16 src_x; + u16 src_y; + u16 dst_x; + u16 dst_y; + u16 dst_z; + u16 w; + u16 h; + struct mcde_rectangle dirty; +}; + +struct mcde_overlay { + struct kobject kobj; + struct list_head list; /* mcde_display_device.ovlys */ + + struct mcde_display_device *ddev; + struct mcde_overlay_info info; + struct mcde_ovly_state *state; +}; + +/* + * Three functions for mapping 8 bits colour channels on 12 bits colour + * channels. The colour channels (ch0, ch1, ch2) can represent (r, g, b) or + * (Y, Cb, Cr) respectively. + */ +struct mcde_palette_table { + u16 (*map_col_ch0)(u8); + u16 (*map_col_ch1)(u8); + u16 (*map_col_ch2)(u8); +}; + +struct mcde_chnl_state; + +struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id, + enum mcde_fifo fifo, const struct mcde_port *port); +int mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl, + enum mcde_port_pix_fmt pix_fmt); +int mcde_chnl_set_palette(struct mcde_chnl_state *chnl, + struct mcde_palette_table *palette); +void mcde_chnl_set_col_convert(struct mcde_chnl_state *chnl, + struct mcde_col_transform *transform, + enum mcde_col_convert convert); +int mcde_chnl_set_video_mode(struct mcde_chnl_state *chnl, + struct mcde_video_mode *vmode); +/* TODO: Remove rotbuf* parameters when ESRAM allocator is implemented*/ +int mcde_chnl_set_rotation(struct mcde_chnl_state *chnl, + enum mcde_display_rotation rotation, u32 rotbuf1, u32 rotbuf2); +int mcde_chnl_enable_synchronized_update(struct mcde_chnl_state *chnl, + bool enable); +int mcde_chnl_set_power_mode(struct mcde_chnl_state *chnl, + enum mcde_display_power_mode power_mode); + +int mcde_chnl_apply(struct mcde_chnl_state *chnl); +int mcde_chnl_update(struct mcde_chnl_state *chnl, + struct mcde_rectangle *update_area, + bool tripple_buffer); +void mcde_chnl_put(struct mcde_chnl_state *chnl); + +void mcde_chnl_stop_flow(struct mcde_chnl_state *chnl); + +void mcde_chnl_enable(struct mcde_chnl_state *chnl); +void mcde_chnl_disable(struct mcde_chnl_state *chnl); + +/* MCDE overlay */ +struct mcde_ovly_state; + +struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl); +void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly, + u32 paddr); +void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly, + u32 stride, enum mcde_ovly_pix_fmt pix_fmt); +void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly, + u16 x, u16 y, u16 w, u16 h); +void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly, + u16 x, u16 y, u8 z); +void mcde_ovly_apply(struct mcde_ovly_state *ovly); +void mcde_ovly_put(struct mcde_ovly_state *ovly); + +/* MCDE dsi */ + +#define DCS_CMD_ENTER_IDLE_MODE 0x39 +#define DCS_CMD_ENTER_INVERT_MODE 0x21 +#define DCS_CMD_ENTER_NORMAL_MODE 0x13 +#define DCS_CMD_ENTER_PARTIAL_MODE 0x12 +#define DCS_CMD_ENTER_SLEEP_MODE 0x10 +#define DCS_CMD_EXIT_IDLE_MODE 0x38 +#define DCS_CMD_EXIT_INVERT_MODE 0x20 +#define DCS_CMD_EXIT_SLEEP_MODE 0x11 +#define DCS_CMD_GET_ADDRESS_MODE 0x0B +#define DCS_CMD_GET_BLUE_CHANNEL 0x08 +#define DCS_CMD_GET_DIAGNOSTIC_RESULT 0x0F +#define DCS_CMD_GET_DISPLAY_MODE 0x0D +#define DCS_CMD_GET_GREEN_CHANNEL 0x07 +#define DCS_CMD_GET_PIXEL_FORMAT 0x0C +#define DCS_CMD_GET_POWER_MODE 0x0A +#define DCS_CMD_GET_RED_CHANNEL 0x06 +#define DCS_CMD_GET_SCANLINE 0x45 +#define DCS_CMD_GET_SIGNAL_MODE 0x0E +#define DCS_CMD_NOP 0x00 +#define DCS_CMD_READ_DDB_CONTINUE 0xA8 +#define DCS_CMD_READ_DDB_START 0xA1 +#define DCS_CMD_READ_MEMORY_CONTINE 0x3E +#define DCS_CMD_READ_MEMORY_START 0x2E +#define DCS_CMD_SET_ADDRESS_MODE 0x36 +#define DCS_CMD_SET_COLUMN_ADDRESS 0x2A +#define DCS_CMD_SET_DISPLAY_OFF 0x28 +#define DCS_CMD_SET_DISPLAY_ON 0x29 +#define DCS_CMD_SET_GAMMA_CURVE 0x26 +#define DCS_CMD_SET_PAGE_ADDRESS 0x2B +#define DCS_CMD_SET_PARTIAL_AREA 0x30 +#define DCS_CMD_SET_PIXEL_FORMAT 0x3A +#define DCS_CMD_SET_SCROLL_AREA 0x33 +#define DCS_CMD_SET_SCROLL_START 0x37 +#define DCS_CMD_SET_TEAR_OFF 0x34 +#define DCS_CMD_SET_TEAR_ON 0x35 +#define DCS_CMD_SET_TEAR_SCANLINE 0x44 +#define DCS_CMD_SOFT_RESET 0x01 +#define DCS_CMD_WRITE_LUT 0x2D +#define DCS_CMD_WRITE_CONTINUE 0x3C +#define DCS_CMD_WRITE_START 0x2C + +#define MCDE_MAX_DCS_READ 4 +#define MCDE_MAX_DSI_DIRECT_CMD_WRITE 15 + +int mcde_dsi_generic_write(struct mcde_chnl_state *chnl, u8* para, int len); +int mcde_dsi_dcs_write(struct mcde_chnl_state *chnl, + u8 cmd, u8 *data, int len); +int mcde_dsi_dcs_read(struct mcde_chnl_state *chnl, + u8 cmd, u32 *data, int *len); +int mcde_dsi_set_max_pkt_size(struct mcde_chnl_state *chnl); + +/* MCDE */ + +/* Driver data */ +#define MCDE_IRQ "MCDE IRQ" +#define MCDE_IO_AREA "MCDE I/O Area" + +struct mcde_platform_data { + /* DPI */ + u8 outmux[5]; /* MCDE_CONF0.OUTMUXx */ + u8 syncmux; /* MCDE_CONF0.SYNCMUXx */ + + const char *regulator_vana_id; + const char *regulator_mcde_epod_id; + const char *regulator_esram_epod_id; + const char *clock_dsi_id; + const char *clock_dsi_lp_id; + const char *clock_dpi_id; + const char *clock_mcde_id; + + int (*platform_set_clocks)(void); + int (*platform_enable_dsipll)(void); + int (*platform_disable_dsipll)(void); +}; + +int mcde_init(void); +void mcde_exit(void); + +#endif /* __MCDE__H__ */ diff --git a/include/video/mcde_display-ab8500.h b/include/video/mcde_display-ab8500.h new file mode 100644 index 00000000000..ffebe62af92 --- /dev/null +++ b/include/video/mcde_display-ab8500.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * AB8500 tvout driver interface + * + * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __DISPLAY_AB8500__H__ +#define __DISPLAY_AB8500__H__ + +#include <video/mcde.h> + +struct ab8500_display_platform_data { + /* Platform info */ + struct mcde_col_transform *rgb_2_yCbCr_transform; + int nr_regulators; + const char *regulator_id[]; +}; + +#endif /* __DISPLAY_AB8500__H__*/ + diff --git a/include/video/mcde_display-av8100.h b/include/video/mcde_display-av8100.h new file mode 100644 index 00000000000..7c13b49e58f --- /dev/null +++ b/include/video/mcde_display-av8100.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE HDMI display driver + * + * Author: Per Persson <per-xb-persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __DISPLAY_AV8100__H__ +#define __DISPLAY_AV8100__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +#define GPIO_AV8100_RSTN 196 +#define NATIVE_XRES_HDMI 1280 +#define NATIVE_YRES_HDMI 720 +#define NATIVE_XRES_SDTV 720 +#define NATIVE_YRES_SDTV 576 +#define DISPONOFF_SIZE 6 +#define TIMING_SIZE 2 +#define STAYALIVE_SIZE 1 + +struct mcde_display_hdmi_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + const char *cvbs_regulator_id; + int reset_delay; /* ms */ + u32 ddb_id; + struct mcde_col_transform *rgb_2_yCbCr_transform; + + /* Driver data */ /* TODO: move to driver data instead */ + bool hdmi_platform_enable; + struct regulator *regulator; +}; + +struct display_driver_data { + struct regulator *cvbs_regulator; + bool cvbs_regulator_enabled; + bool update_port_pixel_format; + const char *fbdevname; + struct mcde_video_mode *video_mode; +}; + +void hdmi_fb_onoff(struct mcde_display_device *ddev, bool enable, + u8 cea, u8 vesa_cea_nr); + +#endif /* __DISPLAY_AV8100__H__ */ diff --git a/include/video/mcde_display-generic_dsi.h b/include/video/mcde_display-generic_dsi.h new file mode 100644 index 00000000000..87ef6baf67a --- /dev/null +++ b/include/video/mcde_display-generic_dsi.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE generic DCS display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY_GENERIC__H__ +#define __MCDE_DISPLAY_GENERIC__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +struct mcde_display_generic_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + int reset_delay; /* ms */ + int sleep_out_delay; /* ms */ + u32 ddb_id; + + /* Driver data */ + bool generic_platform_enable; + struct regulator *regulator; + int max_supply_voltage; + int min_supply_voltage; +}; + +#endif /* __MCDE_DISPLAY_GENERIC__H__ */ + diff --git a/include/video/mcde_display-sony_acx424akp_dsi.h b/include/video/mcde_display-sony_acx424akp_dsi.h new file mode 100644 index 00000000000..29fb14a3fdb --- /dev/null +++ b/include/video/mcde_display-sony_acx424akp_dsi.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE Sony acx424akp DCS display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY_SONY_ACX424AKP__H__ +#define __MCDE_DISPLAY_SONY_ACX424AKP__H__ + +enum display_panel_type { + DISPLAY_NONE = 0, + DISPLAY_SONY_ACX424AKP = 0x1b81, + DISPLAY_SONY_ACX424AKP_ID2 = 0x1a81, +}; + +struct mcde_display_sony_acx424akp_platform_data { + /* Platform info */ + int reset_gpio; + enum display_panel_type disp_panel; /* display panel types */ +}; + +#endif /* __MCDE_DISPLAY_SONY_ACX424AKP__H__ */ + diff --git a/include/video/mcde_display-vuib500-dpi.h b/include/video/mcde_display-vuib500-dpi.h new file mode 100644 index 00000000000..94bad83bf97 --- /dev/null +++ b/include/video/mcde_display-vuib500-dpi.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE DPI display driver + * + * Author: Torbjorn Svensson <torbjorn.x.svensson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __MCDE_DISPLAY_DPI__H__ +#define __MCDE_DISPLAY_DPI__H__ + +#include <linux/regulator/consumer.h> + +#include "mcde_display.h" + +struct mcde_display_dpi_platform_data { + /* Platform info */ + int reset_gpio; + bool reset_high; + const char *regulator_id; + int reset_delay; + + /* Driver data */ + struct regulator *regulator; + int max_supply_voltage; + int min_supply_voltage; +}; +#endif /* __MCDE_DISPLAY_DPI__H__ */ diff --git a/include/video/mcde_display.h b/include/video/mcde_display.h new file mode 100644 index 00000000000..97326cbc28c --- /dev/null +++ b/include/video/mcde_display.h @@ -0,0 +1,149 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DISPLAY__H__ +#define __MCDE_DISPLAY__H__ + +#include <linux/device.h> +#include <linux/pm.h> + +#include <video/mcde.h> + +#define UPDATE_FLAG_PIXEL_FORMAT 0x1 +#define UPDATE_FLAG_VIDEO_MODE 0x2 +#define UPDATE_FLAG_ROTATION 0x4 + +struct mcde_display_dsi_platform_data { + int reset_gpio; + int link; +}; + +#define to_mcde_display_device(__dev) \ + container_of((__dev), struct mcde_display_device, dev) + +struct mcde_display_device { + /* MCDE driver static */ + struct device dev; + const char *name; + int id; + struct mcde_port *port; + struct fb_info *fbi; + bool fictive; + + /* MCDE dss driver internal */ + bool initialized; + enum mcde_chnl chnl_id; + enum mcde_fifo fifo; + bool first_update; + struct mutex display_lock; + + bool enabled; + struct mcde_chnl_state *chnl_state; + struct list_head ovlys; + struct mcde_rectangle update_area; + /* TODO: Remove once ESRAM allocator is done */ + u32 rotbuf1; + u32 rotbuf2; + + /* Display driver internal */ + u16 native_x_res; + u16 native_y_res; + u16 physical_width; + u16 physical_height; + enum mcde_display_power_mode power_mode; + enum mcde_ovly_pix_fmt default_pixel_format; + enum mcde_ovly_pix_fmt pixel_format; + enum mcde_display_rotation rotation; + bool synchronized_update; + struct mcde_video_mode video_mode; + int update_flags; + bool stay_alive; + int check_transparency; + + /* Driver API */ + void (*get_native_resolution)(struct mcde_display_device *dev, + u16 *x_res, u16 *y_res); + enum mcde_ovly_pix_fmt (*get_default_pixel_format)( + struct mcde_display_device *dev); + void (*get_physical_size)(struct mcde_display_device *dev, + u16 *x_size, u16 *y_size); + + int (*set_power_mode)(struct mcde_display_device *dev, + enum mcde_display_power_mode power_mode); + enum mcde_display_power_mode (*get_power_mode)( + struct mcde_display_device *dev); + + int (*try_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + int (*set_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + void (*get_video_mode)(struct mcde_display_device *dev, + struct mcde_video_mode *video_mode); + int (*set_pixel_format)(struct mcde_display_device *dev, + enum mcde_ovly_pix_fmt pix_fmt); + enum mcde_ovly_pix_fmt (*get_pixel_format)( + struct mcde_display_device *dev); + enum mcde_port_pix_fmt (*get_port_pixel_format)( + struct mcde_display_device *dev); + + int (*set_rotation)(struct mcde_display_device *dev, + enum mcde_display_rotation rotation); + enum mcde_display_rotation (*get_rotation)( + struct mcde_display_device *dev); + + int (*set_synchronized_update)(struct mcde_display_device *dev, + bool enable); + bool (*get_synchronized_update)(struct mcde_display_device *dev); + + int (*apply_config)(struct mcde_display_device *dev); + int (*invalidate_area)(struct mcde_display_device *dev, + struct mcde_rectangle *area); + int (*update)(struct mcde_display_device *dev, bool tripple_buffer); + int (*on_first_update)(struct mcde_display_device *dev); + int (*platform_enable)(struct mcde_display_device *dev); + int (*platform_disable)(struct mcde_display_device *dev); + int (*ceanr_convert)(struct mcde_display_device *ddev, + u8 cea, u8 vesa_cea_nr, int buffering, + u16 *w, u16 *h, u16 *vw, u16 *vh); +}; + +struct mcde_display_driver { + int (*probe)(struct mcde_display_device *dev); + int (*remove)(struct mcde_display_device *dev); + void (*shutdown)(struct mcde_display_device *dev); + int (*suspend)(struct mcde_display_device *dev, + pm_message_t state); + int (*resume)(struct mcde_display_device *dev); + + struct device_driver driver; +}; + +/* MCDE dsi (Used by MCDE display drivers) */ + +int mcde_display_dsi_dcs_write(struct mcde_display_device *dev, + u8 cmd, u8 *data, int len); +int mcde_display_dsi_dcs_read(struct mcde_display_device *dev, + u8 cmd, u8 *data, int *len); +int mcde_display_dsi_bta_sync(struct mcde_display_device *dev); + +/* MCDE display bus */ + +int mcde_display_driver_register(struct mcde_display_driver *drv); +void mcde_display_driver_unregister(struct mcde_display_driver *drv); +int mcde_display_device_register(struct mcde_display_device *dev); +void mcde_display_device_unregister(struct mcde_display_device *dev); + +void mcde_display_init_device(struct mcde_display_device *dev); + +int mcde_display_init(void); +void mcde_display_exit(void); + +#endif /* __MCDE_DISPLAY__H__ */ + diff --git a/include/video/mcde_dss.h b/include/video/mcde_dss.h new file mode 100644 index 00000000000..efed79ad023 --- /dev/null +++ b/include/video/mcde_dss.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display sub system driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_DSS__H__ +#define __MCDE_DSS__H__ + +#include <linux/kobject.h> +#include <linux/notifier.h> + +#include "mcde.h" +#include "mcde_display.h" + +/* Public MCDE dss (Used by MCDE fb ioctl & MCDE display sysfs) */ +int mcde_dss_open_channel(struct mcde_display_device *ddev); +void mcde_dss_close_channel(struct mcde_display_device *ddev); +int mcde_dss_enable_display(struct mcde_display_device *ddev); +void mcde_dss_disable_display(struct mcde_display_device *ddev); +int mcde_dss_apply_channel(struct mcde_display_device *ddev); +struct mcde_overlay *mcde_dss_create_overlay(struct mcde_display_device *ddev, + struct mcde_overlay_info *info); +void mcde_dss_destroy_overlay(struct mcde_overlay *ovl); +int mcde_dss_enable_overlay(struct mcde_overlay *ovl); +void mcde_dss_disable_overlay(struct mcde_overlay *ovl); +int mcde_dss_apply_overlay(struct mcde_overlay *ovl, + struct mcde_overlay_info *info); +void mcde_dss_get_overlay_info(struct mcde_overlay *ovly, + struct mcde_overlay_info *info); +int mcde_dss_update_overlay(struct mcde_overlay *ovl, bool tripple_buffer); + +void mcde_dss_get_native_resolution(struct mcde_display_device *ddev, + u16 *x_res, u16 *y_res); +enum mcde_ovl_pix_fmt mcde_dss_get_default_color_format( + struct mcde_display_device *ddev); +void mcde_dss_get_physical_size(struct mcde_display_device *ddev, + u16 *x_size, u16 *y_size); /* mm */ + +int mcde_dss_try_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +int mcde_dss_set_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +void mcde_dss_get_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); + +int mcde_dss_set_pixel_format(struct mcde_display_device *ddev, + enum mcde_ovly_pix_fmt pix_fmt); +int mcde_dss_get_pixel_format(struct mcde_display_device *ddev); + +int mcde_dss_set_rotation(struct mcde_display_device *ddev, + enum mcde_display_rotation rotation); +enum mcde_display_rotation mcde_dss_get_rotation( + struct mcde_display_device *ddev); + +int mcde_dss_set_synchronized_update(struct mcde_display_device *ddev, + bool enable); +bool mcde_dss_get_synchronized_update(struct mcde_display_device *ddev); + +/* MCDE dss events */ + +/* A display device and driver has been loaded, probed and bound */ +#define MCDE_DSS_EVENT_DISPLAY_REGISTERED 1 +/* A display device has been removed */ +#define MCDE_DSS_EVENT_DISPLAY_UNREGISTERED 2 + +/* Note! Notifier callback will be called holding the dev sem */ +int mcde_dss_register_notifier(struct notifier_block *nb); +int mcde_dss_unregister_notifier(struct notifier_block *nb); + +/* MCDE dss driver */ + +int mcde_dss_init(void); +void mcde_dss_exit(void); + +#endif /* __MCDE_DSS__H__ */ + diff --git a/include/video/mcde_fb.h b/include/video/mcde_fb.h new file mode 100644 index 00000000000..17556414aa0 --- /dev/null +++ b/include/video/mcde_fb.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display sub system frame buffer driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ +#ifndef __MCDE_FB__H__ +#define __MCDE_FB__H__ + +#include <linux/fb.h> +#include <linux/ioctl.h> +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#else +#include <linux/types.h> +#include <linux/hwmem.h> +#endif + +#ifdef __KERNEL__ +#include "mcde_dss.h" +#ifdef CONFIG_HAS_EARLYSUSPEND +#include <linux/earlysuspend.h> +#endif +#endif + +#define MCDE_GET_BUFFER_NAME_IOC _IO('M', 1) + +#ifdef __KERNEL__ +#define to_mcde_fb(x) ((struct mcde_fb *)(x)->par) + +#define MCDE_FB_MAX_NUM_OVERLAYS 3 + +struct mcde_fb { + int num_ovlys; + struct mcde_overlay *ovlys[MCDE_FB_MAX_NUM_OVERLAYS]; + u32 pseudo_palette[17]; + enum mcde_ovly_pix_fmt pix_fmt; + int id; + struct hwmem_alloc *alloc; + int alloc_name; +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; +#endif +}; + +/* MCDE fbdev API */ +struct fb_info *mcde_fb_create(struct mcde_display_device *ddev, + uint16_t w, uint16_t h, uint16_t vw, uint16_t vh, + enum mcde_ovly_pix_fmt pix_fmt, uint32_t rotate); + +int mcde_fb_attach_overlay(struct fb_info *fb_info, + struct mcde_overlay *ovl); +void mcde_fb_destroy(struct mcde_display_device *ddev); + +/* MCDE fb driver */ +int mcde_fb_init(void); +void mcde_fb_exit(void); +#endif + +#endif /* __MCDE_FB__H__ */ + |