diff options
Diffstat (limited to 'sound')
68 files changed, 43014 insertions, 1352 deletions
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c index 64449cb8f87..c80d36ffd6b 100644 --- a/sound/core/pcm_lib.c +++ b/sound/core/pcm_lib.c @@ -1933,6 +1933,9 @@ static int pcm_sanity_check(struct snd_pcm_substream *substream) struct snd_pcm_runtime *runtime; if (PCM_RUNTIME_CHECK(substream)) return -ENXIO; + /* TODO: consider and -EINVAL here */ + if (substream->hw_no_buffer) + snd_printd("%s: warning this PCM is host less\n", __func__); runtime = substream->runtime; if (snd_BUG_ON(!substream->ops->copy && !runtime->dma_area)) return -EINVAL; diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 6848dd9c70a..c5a97a8958d 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -842,6 +842,7 @@ static int snd_pcm_pre_start(struct snd_pcm_substream *substream, int state) if (runtime->status->state != SNDRV_PCM_STATE_PREPARED) return -EBADFD; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && + !substream->hw_no_buffer && !snd_pcm_playback_data(substream)) return -EPIPE; runtime->trigger_master = substream; @@ -2028,6 +2029,12 @@ int snd_pcm_open_substream(struct snd_pcm *pcm, int stream, goto error; } + if (substream->ops == NULL) { + snd_printd("cannot open back end PCMs directly\n"); + err = -ENODEV; + goto error; + } + if ((err = substream->ops->open(substream)) < 0) goto error; diff --git a/sound/soc/atmel/atmel-pcm.c b/sound/soc/atmel/atmel-pcm.c index d0e75323ec1..912558cf732 100644 --- a/sound/soc/atmel/atmel-pcm.c +++ b/sound/soc/atmel/atmel-pcm.c @@ -364,9 +364,10 @@ static struct snd_pcm_ops atmel_pcm_ops = { \*--------------------------------------------------------------------------*/ static u64 atmel_pcm_dmamask = 0xffffffff; -static int atmel_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, struct snd_pcm *pcm) +static int atmel_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) diff --git a/sound/soc/au1x/dbdma2.c b/sound/soc/au1x/dbdma2.c index 10fdd2854e5..c675ac8bbcc 100644 --- a/sound/soc/au1x/dbdma2.c +++ b/sound/soc/au1x/dbdma2.c @@ -319,10 +319,10 @@ static void au1xpsc_pcm_free_dma_buffers(struct snd_pcm *pcm) snd_pcm_lib_preallocate_free_for_all(pcm); } -static int au1xpsc_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int au1xpsc_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, card->dev, AU1XPSC_BUFFER_MIN_BYTES, (4096 * 1024) - 1); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index c48b23c1d4f..7a8e90d4c53 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -203,6 +203,7 @@ config SND_SOC_TWL4030 tristate config SND_SOC_TWL6040 + select TWL6040_CODEC tristate config SND_SOC_UDA134X diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c index 4bbf1b15a49..34fcfd46295 100644 --- a/sound/soc/codecs/twl6040.c +++ b/sound/soc/codecs/twl6040.c @@ -29,6 +29,7 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/i2c/twl.h> +#include <linux/mfd/twl6040-codec.h> #include <sound/core.h> #include <sound/pcm.h> @@ -77,14 +78,18 @@ struct twl6040_jack_data { /* codec private data */ struct twl6040_data { - int audpwron; - int naudint; int codec_powered; int pll; int non_lp; + int power_mode_forced; + int headset_mode; + unsigned int clk_in; unsigned int sysclk; + u16 left_step_hs; + u16 right_step_hs; + u16 left_step_hf; + u16 right_step_hf; struct snd_pcm_hw_constraint_list *sysclk_constraints; - struct completion ready; struct twl6040_jack_data hs_jack; struct snd_soc_codec *codec; struct workqueue_struct *workqueue; @@ -239,12 +244,13 @@ static inline void twl6040_write_reg_cache(struct snd_soc_codec *codec, static int twl6040_read_reg_volatile(struct snd_soc_codec *codec, unsigned int reg) { + struct twl6040 *twl6040 = codec->control_data; u8 value; if (reg >= TWL6040_CACHEREGNUM) return -EIO; - twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg); + value = twl6040_reg_read(twl6040, reg); twl6040_write_reg_cache(codec, reg, value); return value; @@ -256,11 +262,13 @@ static int twl6040_read_reg_volatile(struct snd_soc_codec *codec, static int twl6040_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) { + struct twl6040 *twl6040 = codec->control_data; + if (reg >= TWL6040_CACHEREGNUM) return -EIO; twl6040_write_reg_cache(codec, reg, value); - return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg); + return twl6040_reg_write(twl6040, reg, value); } static void twl6040_init_vio_regs(struct snd_soc_codec *codec) @@ -268,15 +276,21 @@ static void twl6040_init_vio_regs(struct snd_soc_codec *codec) u8 *cache = codec->reg_cache; int reg, i; - /* allow registers to be accessed by i2c */ - twl6040_write(codec, TWL6040_REG_ACCCTL, cache[TWL6040_REG_ACCCTL]); - for (i = 0; i < TWL6040_VIOREGNUM; i++) { reg = twl6040_vio_reg[i]; - /* skip read-only registers (ASICID, ASICREV, STATUS) */ + /* + * skip read-only registers (ASICID, ASICREV, STATUS) + * and registers shared among MFD children + */ switch (reg) { case TWL6040_REG_ASICID: case TWL6040_REG_ASICREV: + case TWL6040_REG_INTID: + case TWL6040_REG_INTMR: + case TWL6040_REG_NCPCTL: + case TWL6040_REG_LDOCTL: + case TWL6040_REG_GPOCTL: + case TWL6040_REG_ACCCTL: case TWL6040_REG_STATUS: continue; default: @@ -293,6 +307,19 @@ static void twl6040_init_vdd_regs(struct snd_soc_codec *codec) for (i = 0; i < TWL6040_VDDREGNUM; i++) { reg = twl6040_vdd_reg[i]; + /* skip vibra and pll registers */ + switch (reg) { + case TWL6040_REG_VIBCTLL: + case TWL6040_REG_VIBDATL: + case TWL6040_REG_VIBCTLR: + case TWL6040_REG_VIBDATR: + case TWL6040_REG_HPPLLCTL: + case TWL6040_REG_LPPLLCTL: + case TWL6040_REG_LPPLLDIV: + continue; + default: + break; + } twl6040_write(codec, reg, cache[reg]); } } @@ -317,7 +344,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec, if (headset->ramp == TWL6040_RAMP_UP) { /* ramp step up */ if (val < headset->left_vol) { - val += left_step; + if (val + left_step > headset->left_vol) + val = headset->left_vol; + else + val += left_step; + reg &= ~TWL6040_HSL_VOL_MASK; twl6040_write(codec, TWL6040_REG_HSGAIN, (reg | (~val & TWL6040_HSL_VOL_MASK))); @@ -327,7 +358,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec, } else if (headset->ramp == TWL6040_RAMP_DOWN) { /* ramp step down */ if (val > 0x0) { - val -= left_step; + if ((int)val - (int)left_step < 0) + val = 0; + else + val -= left_step; + reg &= ~TWL6040_HSL_VOL_MASK; twl6040_write(codec, TWL6040_REG_HSGAIN, reg | (~val & TWL6040_HSL_VOL_MASK)); @@ -344,7 +379,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec, if (headset->ramp == TWL6040_RAMP_UP) { /* ramp step up */ if (val < headset->right_vol) { - val += right_step; + if (val + right_step > headset->right_vol) + val = headset->right_vol; + else + val += right_step; + reg &= ~TWL6040_HSR_VOL_MASK; twl6040_write(codec, TWL6040_REG_HSGAIN, (reg | (~val << TWL6040_HSR_VOL_SHIFT))); @@ -354,7 +393,11 @@ static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec, } else if (headset->ramp == TWL6040_RAMP_DOWN) { /* ramp step down */ if (val > 0x0) { - val -= right_step; + if ((int)val - (int)right_step < 0) + val = 0; + else + val -= right_step; + reg &= ~TWL6040_HSR_VOL_MASK; twl6040_write(codec, TWL6040_REG_HSGAIN, reg | (~val << TWL6040_HSR_VOL_SHIFT)); @@ -385,7 +428,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec, if (handsfree->ramp == TWL6040_RAMP_UP) { /* ramp step up */ if (val < handsfree->left_vol) { - val += left_step; + if (val + left_step > handsfree->left_vol) + val = handsfree->left_vol; + else + val += left_step; + reg &= ~TWL6040_HF_VOL_MASK; twl6040_write(codec, TWL6040_REG_HFLGAIN, reg | (0x1D - val)); @@ -395,7 +442,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec, } else if (handsfree->ramp == TWL6040_RAMP_DOWN) { /* ramp step down */ if (val > 0) { - val -= left_step; + if ((int)val - (int)left_step < 0) + val = 0; + else + val -= left_step; + reg &= ~TWL6040_HF_VOL_MASK; twl6040_write(codec, TWL6040_REG_HFLGAIN, reg | (0x1D - val)); @@ -412,7 +463,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec, if (handsfree->ramp == TWL6040_RAMP_UP) { /* ramp step up */ if (val < handsfree->right_vol) { - val += right_step; + if (val + right_step > handsfree->right_vol) + val = handsfree->right_vol; + else + val += right_step; + reg &= ~TWL6040_HF_VOL_MASK; twl6040_write(codec, TWL6040_REG_HFRGAIN, reg | (0x1D - val)); @@ -422,7 +477,11 @@ static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec, } else if (handsfree->ramp == TWL6040_RAMP_DOWN) { /* ramp step down */ if (val > 0) { - val -= right_step; + if ((int)val - (int)right_step < 0) + val = 0; + else + val -= right_step; + reg &= ~TWL6040_HF_VOL_MASK; twl6040_write(codec, TWL6040_REG_HFRGAIN, reg | (0x1D - val)); @@ -451,11 +510,9 @@ static void twl6040_pga_hs_work(struct work_struct *work) /* HS PGA volumes have 4 bits of resolution to ramp */ for (i = 0; i <= 16; i++) { - headset_complete = 1; - if (headset->ramp != TWL6040_RAMP_NONE) - headset_complete = twl6040_hs_ramp_step(codec, - headset->left_step, - headset->right_step); + headset_complete = twl6040_hs_ramp_step(codec, + headset->left_step, + headset->right_step); /* ramp finished ? */ if (headset_complete) @@ -496,11 +553,9 @@ static void twl6040_pga_hf_work(struct work_struct *work) /* HF PGA volumes have 5 bits of resolution to ramp */ for (i = 0; i <= 32; i++) { - handsfree_complete = 1; - if (handsfree->ramp != TWL6040_RAMP_NONE) - handsfree_complete = twl6040_hf_ramp_step(codec, - handsfree->left_step, - handsfree->right_step); + handsfree_complete = twl6040_hf_ramp_step(codec, + handsfree->left_step, + handsfree->right_step); /* ramp finished ? */ if (handsfree_complete) @@ -541,12 +596,16 @@ static int pga_event(struct snd_soc_dapm_widget *w, out = &priv->headset; work = &priv->hs_delayed_work; queue = priv->hs_workqueue; + out->left_step = priv->left_step_hs; + out->right_step = priv->right_step_hs; out->step_delay = 5; /* 5 ms between volume ramp steps */ break; case 4: out = &priv->handsfree; work = &priv->hf_delayed_work; queue = priv->hf_workqueue; + out->left_step = priv->left_step_hf; + out->right_step = priv->right_step_hf; out->step_delay = 5; /* 5 ms between volume ramp steps */ if (SND_SOC_DAPM_EVENT_ON(event)) priv->non_lp++; @@ -579,8 +638,6 @@ static int pga_event(struct snd_soc_dapm_widget *w, if (!delayed_work_pending(work)) { /* use volume ramp for power-down */ - out->left_step = 1; - out->right_step = 1; out->ramp = TWL6040_RAMP_DOWN; INIT_COMPLETION(out->ramp_done); @@ -596,88 +653,6 @@ static int pga_event(struct snd_soc_dapm_widget *w, return 0; } -/* twl6040 codec manual power-up sequence */ -static void twl6040_power_up(struct snd_soc_codec *codec) -{ - u8 ncpctl, ldoctl, lppllctl, accctl; - - ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); - ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); - lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); - accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); - - /* enable reference system */ - ldoctl |= TWL6040_REFENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - msleep(10); - /* enable internal oscillator */ - ldoctl |= TWL6040_OSCENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(10); - /* enable high-side ldo */ - ldoctl |= TWL6040_HSLDOENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(244); - /* enable negative charge pump */ - ncpctl |= TWL6040_NCPENA | TWL6040_NCPOPEN; - twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); - udelay(488); - /* enable low-side ldo */ - ldoctl |= TWL6040_LSLDOENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(244); - /* enable low-power pll */ - lppllctl |= TWL6040_LPLLENA; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); - /* reset state machine */ - accctl |= TWL6040_RESETSPLIT; - twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); - mdelay(5); - accctl &= ~TWL6040_RESETSPLIT; - twl6040_write(codec, TWL6040_REG_ACCCTL, accctl); - /* disable internal oscillator */ - ldoctl &= ~TWL6040_OSCENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); -} - -/* twl6040 codec manual power-down sequence */ -static void twl6040_power_down(struct snd_soc_codec *codec) -{ - u8 ncpctl, ldoctl, lppllctl, accctl; - - ncpctl = twl6040_read_reg_cache(codec, TWL6040_REG_NCPCTL); - ldoctl = twl6040_read_reg_cache(codec, TWL6040_REG_LDOCTL); - lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); - accctl = twl6040_read_reg_cache(codec, TWL6040_REG_ACCCTL); - - /* enable internal oscillator */ - ldoctl |= TWL6040_OSCENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(10); - /* disable low-power pll */ - lppllctl &= ~TWL6040_LPLLENA; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); - /* disable low-side ldo */ - ldoctl &= ~TWL6040_LSLDOENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(244); - /* disable negative charge pump */ - ncpctl &= ~(TWL6040_NCPENA | TWL6040_NCPOPEN); - twl6040_write(codec, TWL6040_REG_NCPCTL, ncpctl); - udelay(488); - /* disable high-side ldo */ - ldoctl &= ~TWL6040_HSLDOENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - udelay(244); - /* disable internal oscillator */ - ldoctl &= ~TWL6040_OSCENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - /* disable reference system */ - ldoctl &= ~TWL6040_REFENA; - twl6040_write(codec, TWL6040_REG_LDOCTL, ldoctl); - msleep(10); -} - /* set headset dac and driver power mode */ static int headset_power_mode(struct snd_soc_codec *codec, int high_perf) { @@ -713,15 +688,26 @@ static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w, { struct snd_soc_codec *codec = w->codec; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + int ret = 0; - if (SND_SOC_DAPM_EVENT_ON(event)) + if (SND_SOC_DAPM_EVENT_ON(event)) { priv->non_lp++; - else + if (!strcmp(w->name, "Earphone Driver")) { + /* Earphone doesn't support low power mode */ + priv->power_mode_forced = 1; + ret = headset_power_mode(codec, 1); + } + } else { priv->non_lp--; + if (!strcmp(w->name, "Earphone Driver")) { + priv->power_mode_forced = 0; + ret = headset_power_mode(codec, priv->headset_mode); + } + } msleep(1); - return 0; + return ret; } void twl6040_hs_jack_report(struct snd_soc_codec *codec, @@ -766,32 +752,18 @@ static void twl6040_accessory_work(struct work_struct *work) } /* audio interrupt handler */ -static irqreturn_t twl6040_naudint_handler(int irq, void *data) +static irqreturn_t twl6040_audio_handler(int irq, void *data) { struct snd_soc_codec *codec = data; + struct twl6040 *twl6040 = codec->control_data; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); u8 intid; - twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); - - if (intid & TWL6040_THINT) - dev_alert(codec->dev, "die temp over-limit detection\n"); + intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID); if ((intid & TWL6040_PLUGINT) || (intid & TWL6040_UNPLUGINT)) queue_delayed_work(priv->workqueue, &priv->delayed_work, - msecs_to_jiffies(200)); - - if (intid & TWL6040_HOOKINT) - dev_info(codec->dev, "hook detection\n"); - - if (intid & TWL6040_HFINT) - dev_alert(codec->dev, "hf drivers over current detection\n"); - - if (intid & TWL6040_VIBINT) - dev_alert(codec->dev, "vib drivers over current detection\n"); - - if (intid & TWL6040_READYINT) - complete(&priv->ready); + msecs_to_jiffies(200)); return IRQ_HANDLED; } @@ -960,9 +932,9 @@ static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -600, 600, 0); /* * AFMGAIN volume control: - * from 18 to 24 dB in 6 dB steps + * from -18 to 24 dB in 6 dB steps */ -static DECLARE_TLV_DB_SCALE(afm_amp_tlv, 1800, 600, 0); +static DECLARE_TLV_DB_SCALE(afm_amp_tlv, -1800, 600, 0); /* * HSGAIN volume control: @@ -1040,6 +1012,58 @@ static const struct snd_kcontrol_new hfr_mux_controls = static const struct snd_kcontrol_new ep_driver_switch_controls = SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0); +/* AVADC clock priority */ +static const char *twl6040_dmic_volt_texts[] = { + "1.80V", "1.85V" +}; + +static const struct soc_enum twl6040_dmic_volt_enum[] = { + SOC_ENUM_SINGLE(TWL6040_REG_DMICBCTL, 2, + ARRAY_SIZE(twl6040_dmic_volt_texts), + twl6040_dmic_volt_texts), + SOC_ENUM_SINGLE(TWL6040_REG_DMICBCTL, 6, + ARRAY_SIZE(twl6040_dmic_volt_texts), + twl6040_dmic_volt_texts), +}; + +/* Headset power mode */ +static const char *twl6040_headset_power_texts[] = { + "Low-Power", "High-Perfomance", +}; + +static const struct soc_enum twl6040_headset_power_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(twl6040_headset_power_texts), + twl6040_headset_power_texts); + +static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = priv->headset_mode; + + return 0; +} + +static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); + int high_perf = ucontrol->value.enumerated.item[0]; + int ret; + + if (priv->power_mode_forced) + return -EPERM; + + ret = headset_power_mode(codec, high_perf); + if (!ret) + priv->headset_mode = high_perf; + + return ret; +} + static const struct snd_kcontrol_new twl6040_snd_controls[] = { /* Capture gains */ SOC_DOUBLE_TLV("Capture Preamplifier Volume", @@ -1049,7 +1073,7 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = { /* AFM gains */ SOC_DOUBLE_TLV("Aux FM Volume", - TWL6040_REG_LINEGAIN, 0, 4, 0xF, 0, afm_amp_tlv), + TWL6040_REG_LINEGAIN, 0, 3, 7, 0, afm_amp_tlv), /* Playback gains */ SOC_TWL6040_DOUBLE_TLV("Headset Playback Volume", @@ -1058,6 +1082,13 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = { TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv), SOC_SINGLE_TLV("Earphone Playback Volume", TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv), + + SOC_ENUM("Digital Mic Bias 1 Voltage", twl6040_dmic_volt_enum[0]), + SOC_ENUM("Digital Mic Bias 2 Voltage", twl6040_dmic_volt_enum[1]), + + SOC_ENUM_EXT("Headset Power Mode", twl6040_headset_power_enum, + twl6040_headset_power_get_enum, + twl6040_headset_power_put_enum), }; static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = { @@ -1231,37 +1262,11 @@ static int twl6040_add_widgets(struct snd_soc_codec *codec) return 0; } -static int twl6040_power_up_completion(struct snd_soc_codec *codec, - int naudint) -{ - struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - int time_left; - u8 intid; - - time_left = wait_for_completion_timeout(&priv->ready, - msecs_to_jiffies(144)); - - if (!time_left) { - twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, - TWL6040_REG_INTID); - if (!(intid & TWL6040_READYINT)) { - dev_err(codec->dev, "timeout waiting for READYINT\n"); - return -ETIMEDOUT; - } - } - - priv->codec_powered = 1; - - return 0; -} - static int twl6040_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { + struct twl6040 *twl6040 = codec->control_data; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - int audpwron = priv->audpwron; - int naudint = priv->naudint; - int ret; switch (level) { case SND_SOC_BIAS_ON: @@ -1272,24 +1277,8 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec, if (priv->codec_powered) break; - if (gpio_is_valid(audpwron)) { - /* use AUDPWRON line */ - gpio_set_value(audpwron, 1); - - /* wait for power-up completion */ - ret = twl6040_power_up_completion(codec, naudint); - if (ret) - return ret; - - /* sync registers updated during power-up sequence */ - twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); - twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); - twl6040_read_reg_volatile(codec, TWL6040_REG_LPPLLCTL); - } else { - /* use manual power-up sequence */ - twl6040_power_up(codec); - priv->codec_powered = 1; - } + twl6040_enable(twl6040); + priv->codec_powered = 1; /* initialize vdd/vss registers with reg_cache */ twl6040_init_vdd_regs(codec); @@ -1307,28 +1296,15 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec, if (!priv->codec_powered) break; - if (gpio_is_valid(audpwron)) { - /* use AUDPWRON line */ - gpio_set_value(audpwron, 0); - - /* power-down sequence latency */ - udelay(500); - - /* sync registers updated during power-down sequence */ - twl6040_read_reg_volatile(codec, TWL6040_REG_NCPCTL); - twl6040_read_reg_volatile(codec, TWL6040_REG_LDOCTL); - twl6040_write_reg_cache(codec, TWL6040_REG_LPPLLCTL, - 0x00); - } else { - /* use manual power-down sequence */ - twl6040_power_down(codec); - } - + twl6040_disable(twl6040); priv->codec_powered = 0; break; } codec->dapm.bias_level = level; + /* get pll and sysclk after power transition */ + priv->pll = twl6040_get_pll(twl6040); + priv->sysclk = twl6040_get_sysclk(twl6040); return 0; } @@ -1357,13 +1333,17 @@ static struct snd_pcm_hw_constraint_list hp_constraints = { static int twl6040_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { + /* TODO: Add constraint for backends */ +#if 0 struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; + struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, priv->sysclk_constraints); +#endif return 0; } @@ -1374,39 +1354,40 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream, { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; + struct twl6040 *twl6040 = codec->control_data; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - u8 lppllctl; - int rate; + unsigned int sysclk; + int rate, ret; /* nothing to do for high-perf pll, it supports only 48 kHz */ if (priv->pll == TWL6040_HPPLL_ID) return 0; - lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); - rate = params_rate(params); switch (rate) { case 11250: case 22500: case 44100: case 88200: - lppllctl |= TWL6040_LPLLFIN; - priv->sysclk = 17640000; + sysclk = 17640000; break; case 8000: case 16000: case 32000: case 48000: case 96000: - lppllctl &= ~TWL6040_LPLLFIN; - priv->sysclk = 19200000; + sysclk = 19200000; break; default: dev_err(codec->dev, "unsupported rate %d\n", rate); return -EINVAL; } - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + ret = twl6040_set_pll(twl6040, TWL6040_LPPLL_ID, priv->clk_in, sysclk); + if (ret) + return ret; + + priv->sysclk = twl6040_get_sysclk(twl6040); return 0; } @@ -1449,99 +1430,25 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; + struct twl6040 *twl6040 = codec->control_data; struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - u8 hppllctl, lppllctl; - - hppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_HPPLLCTL); - lppllctl = twl6040_read_reg_cache(codec, TWL6040_REG_LPPLLCTL); + int ret; switch (clk_id) { case TWL6040_SYSCLK_SEL_LPPLL: - switch (freq) { - case 32768: - /* headset dac and driver must be in low-power mode */ - headset_power_mode(codec, 0); - - /* clk32k input requires low-power pll */ - lppllctl |= TWL6040_LPLLENA; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); - mdelay(5); - lppllctl &= ~TWL6040_HPLLSEL; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); - hppllctl &= ~TWL6040_HPLLENA; - twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); - break; - default: - dev_err(codec->dev, "unknown mclk freq %d\n", freq); - return -EINVAL; - } - - /* lppll divider */ - switch (priv->sysclk) { - case 17640000: - lppllctl |= TWL6040_LPLLFIN; - break; - case 19200000: - lppllctl &= ~TWL6040_LPLLFIN; - break; - default: - /* sysclk not yet configured */ - lppllctl &= ~TWL6040_LPLLFIN; - priv->sysclk = 19200000; - break; - } - - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + ret = twl6040_set_pll(twl6040, TWL6040_LPPLL_ID, + freq, priv->sysclk); + if (ret) + return ret; - priv->pll = TWL6040_LPPLL_ID; priv->sysclk_constraints = &lp_constraints; break; case TWL6040_SYSCLK_SEL_HPPLL: - hppllctl &= ~TWL6040_MCLK_MSK; - - switch (freq) { - case 12000000: - /* mclk input, pll enabled */ - hppllctl |= TWL6040_MCLK_12000KHZ | - TWL6040_HPLLSQRBP | - TWL6040_HPLLENA; - break; - case 19200000: - /* mclk input, pll disabled */ - hppllctl |= TWL6040_MCLK_19200KHZ | - TWL6040_HPLLSQRENA | - TWL6040_HPLLBP; - break; - case 26000000: - /* mclk input, pll enabled */ - hppllctl |= TWL6040_MCLK_26000KHZ | - TWL6040_HPLLSQRBP | - TWL6040_HPLLENA; - break; - case 38400000: - /* clk slicer, pll disabled */ - hppllctl |= TWL6040_MCLK_38400KHZ | - TWL6040_HPLLSQRENA | - TWL6040_HPLLBP; - break; - default: - dev_err(codec->dev, "unknown mclk freq %d\n", freq); - return -EINVAL; - } - - /* headset dac and driver must be in high-performance mode */ - headset_power_mode(codec, 1); - - twl6040_write(codec, TWL6040_REG_HPPLLCTL, hppllctl); - udelay(500); - lppllctl |= TWL6040_HPLLSEL; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); - lppllctl &= ~TWL6040_LPLLENA; - twl6040_write(codec, TWL6040_REG_LPPLLCTL, lppllctl); + ret = twl6040_set_pll(twl6040, TWL6040_HPPLL_ID, freq, + priv->sysclk); + if (ret) + return ret; - /* high-performance pll can provide only 19.2 MHz */ - priv->pll = TWL6040_HPPLL_ID; - priv->sysclk = 19200000; priv->sysclk_constraints = &hp_constraints; break; default: @@ -1549,6 +1456,10 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai, return -EINVAL; } + priv->pll = twl6040_get_pll(twl6040); + priv->clk_in = freq; + priv->sysclk = twl6040_get_sysclk(twl6040); + return 0; } @@ -1559,23 +1470,51 @@ static struct snd_soc_dai_ops twl6040_dai_ops = { .set_sysclk = twl6040_set_dai_sysclk, }; -static struct snd_soc_dai_driver twl6040_dai = { - .name = "twl6040-hifi", +static struct snd_soc_dai_driver twl6040_dai[] = { +{ + .name = "twl6040-ul", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = TWL6040_RATES, + .formats = TWL6040_FORMATS, + }, + .ops = &twl6040_dai_ops, +}, +{ + .name = "twl6040-dl1", .playback = { - .stream_name = "Playback", + .stream_name = "Headset Playback", .channels_min = 1, - .channels_max = 4, + .channels_max = 2, .rates = TWL6040_RATES, .formats = TWL6040_FORMATS, }, - .capture = { - .stream_name = "Capture", + .ops = &twl6040_dai_ops, +}, +{ + .name = "twl6040-dl2", + .playback = { + .stream_name = "Handsfree Playback", .channels_min = 1, .channels_max = 2, .rates = TWL6040_RATES, .formats = TWL6040_FORMATS, }, .ops = &twl6040_dai_ops, +}, +{ + .name = "twl6040-vib", + .playback = { + .stream_name = "Vibra Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .formats = TWL6040_FORMATS, + }, + .ops = &twl6040_dai_ops, +}, }; #ifdef CONFIG_PM @@ -1600,11 +1539,9 @@ static int twl6040_resume(struct snd_soc_codec *codec) static int twl6040_probe(struct snd_soc_codec *codec) { - struct twl4030_codec_data *twl_codec = codec->dev->platform_data; struct twl6040_data *priv; - int audpwron, naudint; + struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev); int ret = 0; - u8 icrev, intmr = TWL6040_ALLINT_MSK; priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); if (priv == NULL) @@ -1612,23 +1549,28 @@ static int twl6040_probe(struct snd_soc_codec *codec) snd_soc_codec_set_drvdata(codec, priv); priv->codec = codec; + codec->control_data = dev_get_drvdata(codec->dev->parent); - twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &icrev, TWL6040_REG_ASICREV); - - if (twl_codec && (icrev > 0)) - audpwron = twl_codec->audpwron_gpio; - else - audpwron = -EINVAL; + if (pdata && pdata->left_step_hs && pdata->right_step_hs) { + priv->left_step_hs = pdata->left_step_hs; + priv->right_step_hs = pdata->right_step_hs; + } else { + priv->left_step_hs = 1; + priv->right_step_hs = 1; + } - if (twl_codec) - naudint = twl_codec->naudint_irq; - else - naudint = 0; + if (pdata && pdata->left_step_hf && pdata->right_step_hf) { + priv->left_step_hf = pdata->left_step_hf; + priv->right_step_hf = pdata->right_step_hf; + } else { + priv->left_step_hf = 1; + priv->right_step_hf = 1; + } - priv->audpwron = audpwron; - priv->naudint = naudint; + /* default is high-performance mode */ + priv->headset_mode = 1; + priv->sysclk_constraints = &lp_constraints; priv->workqueue = create_singlethread_workqueue("twl6040-codec"); - if (!priv->workqueue) goto work_err; @@ -1636,56 +1578,34 @@ static int twl6040_probe(struct snd_soc_codec *codec) mutex_init(&priv->mutex); - init_completion(&priv->ready); init_completion(&priv->headset.ramp_done); init_completion(&priv->handsfree.ramp_done); - if (gpio_is_valid(audpwron)) { - ret = gpio_request(audpwron, "audpwron"); - if (ret) - goto gpio1_err; - - ret = gpio_direction_output(audpwron, 0); - if (ret) - goto gpio2_err; - - priv->codec_powered = 0; - - /* enable only codec ready interrupt */ - intmr &= ~(TWL6040_READYMSK | TWL6040_PLUGMSK); - - /* reset interrupt status to allow correct power up sequence */ - twl6040_read_reg_volatile(codec, TWL6040_REG_INTID); - } - twl6040_write(codec, TWL6040_REG_INTMR, intmr); - - if (naudint) { - /* audio interrupt */ - ret = request_threaded_irq(naudint, NULL, - twl6040_naudint_handler, - IRQF_TRIGGER_LOW | IRQF_ONESHOT, - "twl6040_codec", codec); - if (ret) - goto gpio2_err; - } - - /* init vio registers */ - twl6040_init_vio_regs(codec); - priv->hf_workqueue = create_singlethread_workqueue("twl6040-hf"); if (priv->hf_workqueue == NULL) { ret = -ENOMEM; - goto irq_err; + goto hfwork_err; } priv->hs_workqueue = create_singlethread_workqueue("twl6040-hs"); if (priv->hs_workqueue == NULL) { ret = -ENOMEM; - goto wq_err; + goto hswork_err; } INIT_DELAYED_WORK(&priv->hs_delayed_work, twl6040_pga_hs_work); INIT_DELAYED_WORK(&priv->hf_delayed_work, twl6040_pga_hf_work); + ret = twl6040_request_irq(codec->control_data, TWL6040_IRQ_PLUG, + twl6040_audio_handler, "twl6040_irq_plug", + codec); + if (ret) { + dev_err(codec->dev, "PLUG IRQ request failed: %d\n", ret); + goto irq_err; + } + + /* init vio registers */ + twl6040_init_vio_regs(codec); + /* power on device */ ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); if (ret) @@ -1698,16 +1618,12 @@ static int twl6040_probe(struct snd_soc_codec *codec) return 0; bias_err: + twl6040_free_irq(codec->control_data, TWL6040_IRQ_PLUG, codec); +irq_err: destroy_workqueue(priv->hs_workqueue); -wq_err: +hswork_err: destroy_workqueue(priv->hf_workqueue); -irq_err: - if (naudint) - free_irq(naudint, codec); -gpio2_err: - if (gpio_is_valid(audpwron)) - gpio_free(audpwron); -gpio1_err: +hfwork_err: destroy_workqueue(priv->workqueue); work_err: kfree(priv); @@ -1717,17 +1633,9 @@ work_err: static int twl6040_remove(struct snd_soc_codec *codec) { struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); - int audpwron = priv->audpwron; - int naudint = priv->naudint; twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); - - if (gpio_is_valid(audpwron)) - gpio_free(audpwron); - - if (naudint) - free_irq(naudint, codec); - + twl6040_free_irq(codec->control_data, TWL6040_IRQ_PLUG, codec); destroy_workqueue(priv->workqueue); destroy_workqueue(priv->hf_workqueue); destroy_workqueue(priv->hs_workqueue); @@ -1752,7 +1660,8 @@ static struct snd_soc_codec_driver soc_codec_dev_twl6040 = { static int __devinit twl6040_codec_probe(struct platform_device *pdev) { return snd_soc_register_codec(&pdev->dev, - &soc_codec_dev_twl6040, &twl6040_dai, 1); + &soc_codec_dev_twl6040, twl6040_dai, + ARRAY_SIZE(twl6040_dai)); } static int __devexit twl6040_codec_remove(struct platform_device *pdev) diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h index 23aeed0963e..105a6fde5f9 100644 --- a/sound/soc/codecs/twl6040.h +++ b/sound/soc/codecs/twl6040.h @@ -22,123 +22,7 @@ #ifndef __TWL6040_H__ #define __TWL6040_H__ -#define TWL6040_REG_ASICID 0x01 -#define TWL6040_REG_ASICREV 0x02 -#define TWL6040_REG_INTID 0x03 -#define TWL6040_REG_INTMR 0x04 -#define TWL6040_REG_NCPCTL 0x05 -#define TWL6040_REG_LDOCTL 0x06 -#define TWL6040_REG_HPPLLCTL 0x07 -#define TWL6040_REG_LPPLLCTL 0x08 -#define TWL6040_REG_LPPLLDIV 0x09 -#define TWL6040_REG_AMICBCTL 0x0A -#define TWL6040_REG_DMICBCTL 0x0B -#define TWL6040_REG_MICLCTL 0x0C -#define TWL6040_REG_MICRCTL 0x0D -#define TWL6040_REG_MICGAIN 0x0E -#define TWL6040_REG_LINEGAIN 0x0F -#define TWL6040_REG_HSLCTL 0x10 -#define TWL6040_REG_HSRCTL 0x11 -#define TWL6040_REG_HSGAIN 0x12 -#define TWL6040_REG_EARCTL 0x13 -#define TWL6040_REG_HFLCTL 0x14 -#define TWL6040_REG_HFLGAIN 0x15 -#define TWL6040_REG_HFRCTL 0x16 -#define TWL6040_REG_HFRGAIN 0x17 -#define TWL6040_REG_VIBCTLL 0x18 -#define TWL6040_REG_VIBDATL 0x19 -#define TWL6040_REG_VIBCTLR 0x1A -#define TWL6040_REG_VIBDATR 0x1B -#define TWL6040_REG_HKCTL1 0x1C -#define TWL6040_REG_HKCTL2 0x1D -#define TWL6040_REG_GPOCTL 0x1E -#define TWL6040_REG_ALB 0x1F -#define TWL6040_REG_DLB 0x20 -#define TWL6040_REG_TRIM1 0x28 -#define TWL6040_REG_TRIM2 0x29 -#define TWL6040_REG_TRIM3 0x2A -#define TWL6040_REG_HSOTRIM 0x2B -#define TWL6040_REG_HFOTRIM 0x2C -#define TWL6040_REG_ACCCTL 0x2D -#define TWL6040_REG_STATUS 0x2E - -#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1) - -#define TWL6040_VIOREGNUM 18 -#define TWL6040_VDDREGNUM 21 - -/* INTID (0x03) fields */ - -#define TWL6040_THINT 0x01 -#define TWL6040_PLUGINT 0x02 -#define TWL6040_UNPLUGINT 0x04 -#define TWL6040_HOOKINT 0x08 -#define TWL6040_HFINT 0x10 -#define TWL6040_VIBINT 0x20 -#define TWL6040_READYINT 0x40 - -/* INTMR (0x04) fields */ - -#define TWL6040_PLUGMSK 0x02 -#define TWL6040_READYMSK 0x40 -#define TWL6040_ALLINT_MSK 0x7B - -/* NCPCTL (0x05) fields */ - -#define TWL6040_NCPENA 0x01 -#define TWL6040_NCPOPEN 0x40 - -/* LDOCTL (0x06) fields */ - -#define TWL6040_LSLDOENA 0x01 -#define TWL6040_HSLDOENA 0x04 -#define TWL6040_REFENA 0x40 -#define TWL6040_OSCENA 0x80 - -/* HPPLLCTL (0x07) fields */ - -#define TWL6040_HPLLENA 0x01 -#define TWL6040_HPLLRST 0x02 -#define TWL6040_HPLLBP 0x04 -#define TWL6040_HPLLSQRENA 0x08 -#define TWL6040_HPLLSQRBP 0x10 -#define TWL6040_MCLK_12000KHZ (0 << 5) -#define TWL6040_MCLK_19200KHZ (1 << 5) -#define TWL6040_MCLK_26000KHZ (2 << 5) -#define TWL6040_MCLK_38400KHZ (3 << 5) -#define TWL6040_MCLK_MSK 0x60 - -/* LPPLLCTL (0x08) fields */ - -#define TWL6040_LPLLENA 0x01 -#define TWL6040_LPLLRST 0x02 -#define TWL6040_LPLLSEL 0x04 -#define TWL6040_LPLLFIN 0x08 -#define TWL6040_HPLLSEL 0x10 - -/* HSLCTL (0x10) fields */ - -#define TWL6040_HSDACMODEL 0x02 -#define TWL6040_HSDRVMODEL 0x08 - -/* HSRCTL (0x11) fields */ - -#define TWL6040_HSDACMODER 0x02 -#define TWL6040_HSDRVMODER 0x08 - -/* ACCCTL (0x2D) fields */ - -#define TWL6040_RESETSPLIT 0x04 - -#define TWL6040_SYSCLK_SEL_LPPLL 1 -#define TWL6040_SYSCLK_SEL_HPPLL 2 - -#define TWL6040_HPPLL_ID 1 -#define TWL6040_LPPLL_ID 2 - -/* STATUS (0x2E) fields */ - -#define TWL6040_PLUGCOMP 0x02 +#include <linux/mfd/twl6040-codec.h> void twl6040_hs_jack_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, int report); diff --git a/sound/soc/davinci/davinci-pcm.c b/sound/soc/davinci/davinci-pcm.c index 9d35b8c1a62..7d889d45cb4 100644 --- a/sound/soc/davinci/davinci-pcm.c +++ b/sound/soc/davinci/davinci-pcm.c @@ -811,9 +811,10 @@ static void davinci_pcm_free(struct snd_pcm *pcm) static u64 davinci_pcm_dmamask = 0xffffffff; -static int davinci_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, struct snd_pcm *pcm) +static int davinci_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret; if (!card->dev->dma_mask) diff --git a/sound/soc/ep93xx/ep93xx-pcm.c b/sound/soc/ep93xx/ep93xx-pcm.c index 06670776f64..210e4a72b07 100644 --- a/sound/soc/ep93xx/ep93xx-pcm.c +++ b/sound/soc/ep93xx/ep93xx-pcm.c @@ -266,9 +266,10 @@ static void ep93xx_pcm_free_dma_buffers(struct snd_pcm *pcm) static u64 ep93xx_pcm_dmamask = 0xffffffff; -static int ep93xx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int ep93xx_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/imx/imx-pcm-fiq.c index 413b78da248..58a4c227459 100644 --- a/sound/soc/imx/imx-pcm-fiq.c +++ b/sound/soc/imx/imx-pcm-fiq.c @@ -238,12 +238,13 @@ static struct snd_pcm_ops imx_pcm_ops = { static int ssi_irq = 0; -static int imx_pcm_fiq_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int imx_pcm_fiq_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret; - ret = imx_pcm_new(card, dai, pcm); + ret = imx_pcm_new(rtd); if (ret) return ret; diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c index 30894ea7f33..e74c84cfc88 100644 --- a/sound/soc/imx/imx-ssi.c +++ b/sound/soc/imx/imx-ssi.c @@ -388,10 +388,10 @@ static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) static u64 imx_pcm_dmamask = DMA_BIT_MASK(32); -int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +int imx_pcm_new(struct snd_soc_pcm_runtime *rtd) { - + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h index dc8a87530e3..0a84cec3599 100644 --- a/sound/soc/imx/imx-ssi.h +++ b/sound/soc/imx/imx-ssi.h @@ -225,8 +225,7 @@ struct snd_soc_platform *imx_ssi_dma_mx2_init(struct platform_device *pdev, struct imx_ssi *ssi); int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma); -int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm); +int imx_pcm_new(struct snd_soc_pcm_runtime *rtd); void imx_pcm_free(struct snd_pcm *pcm); /* diff --git a/sound/soc/jz4740/jz4740-pcm.c b/sound/soc/jz4740/jz4740-pcm.c index fb1483f7c96..6d0a9361773 100644 --- a/sound/soc/jz4740/jz4740-pcm.c +++ b/sound/soc/jz4740/jz4740-pcm.c @@ -299,9 +299,10 @@ static void jz4740_pcm_free(struct snd_pcm *pcm) static u64 jz4740_pcm_dmamask = DMA_BIT_MASK(32); -int jz4740_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +int jz4740_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig index a088db6d509..771da39fa9f 100644 --- a/sound/soc/omap/Kconfig +++ b/sound/soc/omap/Kconfig @@ -2,6 +2,9 @@ config SND_OMAP_SOC tristate "SoC Audio for the Texas Instruments OMAP chips" depends on ARCH_OMAP +config SND_OMAP_SOC_ABE_DSP + tristate + config SND_OMAP_SOC_MCBSP tristate select OMAP_MCBSP @@ -9,6 +12,13 @@ config SND_OMAP_SOC_MCBSP config SND_OMAP_SOC_MCPDM tristate +config SND_OMAP_SOC_ABE + select SND_DYNAMIC_MINORS + tristate + +config SND_OMAP_SOC_DMIC + tristate + config SND_OMAP_SOC_N810 tristate "SoC Audio support for Nokia N810" depends on SND_OMAP_SOC && MACH_NOKIA_N810 && I2C @@ -99,13 +109,28 @@ config SND_OMAP_SOC_SDP3430 SDP3430. config SND_OMAP_SOC_SDP4430 - tristate "SoC Audio support for Texas Instruments SDP4430" - depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_4430SDP + tristate "SoC Audio support for Texas Instruments SDP4430 or PandaBoard" + depends on (MACH_OMAP_4430SDP || MACH_OMAP4_PANDA) + depends on TWL4030_CORE && SND_OMAP_SOC + select SND_OMAP_SOC_ABE select SND_OMAP_SOC_MCPDM select SND_SOC_TWL6040 + select SND_OMAP_SOC_MCBSP + select SND_SOC_DMIC + select SND_OMAP_SOC_DMIC + select SND_OMAP_SOC_ABE_DSP help Say Y if you want to add support for SoC audio on Texas Instruments - SDP4430. + SDP4430 or PandaBoard. + +config SND_OMAP_SOC_OMAP4_HDMI + tristate "SoC Audio support for Texas Instruments SDP4430 or Panda HDMI port" + depends on SND_OMAP_SOC && OMAP4_DSS_HDMI && OMAP2_DSS + depends on (MACH_OMAP_4430SDP || MACH_OMAP4_PANDA) + select SND_OMAP_SOC_HDMI + help + Say Y if you want to add support for SoC HDMI audio on Texas Instruments + SDP4430 or Panda config SND_OMAP_SOC_OMAP3_PANDORA tristate "SoC Audio support for OMAP3 Pandora" diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile index ba9fc650db2..0267ec9e43a 100644 --- a/sound/soc/omap/Makefile +++ b/sound/soc/omap/Makefile @@ -1,11 +1,17 @@ # OMAP Platform Support +snd-soc-omap-abe-objs := omap-abe.o snd-soc-omap-objs := omap-pcm.o +snd-soc-omap-dmic-objs := omap-dmic.o snd-soc-omap-mcbsp-objs := omap-mcbsp.o -snd-soc-omap-mcpdm-objs := omap-mcpdm.o mcpdm.o +snd-soc-omap-mcpdm-objs := omap-mcpdm.o +snd-soc-omap-abe-dsp-objs := omap-abe-dsp.o +obj-$(CONFIG_SND_OMAP_SOC_ABE) += snd-soc-omap-abe.o obj-$(CONFIG_SND_OMAP_SOC) += snd-soc-omap.o +obj-$(CONFIG_SND_OMAP_SOC_DMIC) += snd-soc-omap-dmic.o obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o obj-$(CONFIG_SND_OMAP_SOC_MCPDM) += snd-soc-omap-mcpdm.o +obj-$(CONFIG_SND_OMAP_SOC_ABE_DSP) += snd-soc-omap-abe-dsp.o abe/ # OMAP Machine Support snd-soc-n810-objs := n810.o @@ -22,6 +28,7 @@ snd-soc-omap3pandora-objs := omap3pandora.o snd-soc-omap3beagle-objs := omap3beagle.o snd-soc-zoom2-objs := zoom2.o snd-soc-igep0020-objs := igep0020.o +snd-soc-omap4-hdmi-objs := omap-hdmi.o omap4-hdmi-card.o obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o obj-$(CONFIG_SND_OMAP_SOC_RX51) += snd-soc-rx51.o @@ -37,3 +44,4 @@ obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o obj-$(CONFIG_SND_OMAP_SOC_IGEP0020) += snd-soc-igep0020.o +obj-$(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) += snd-soc-omap4-hdmi.o diff --git a/sound/soc/omap/abe/Makefile b/sound/soc/omap/abe/Makefile new file mode 100644 index 00000000000..33005870479 --- /dev/null +++ b/sound/soc/omap/abe/Makefile @@ -0,0 +1,11 @@ +snd-soc-abe-hal-objs += abe_api.o \ + abe_dbg.o \ + abe_dat.o \ + abe_ext.o \ + abe_ini.o \ + abe_irq.o \ + abe_lib.o \ + abe_mem.o \ + abe_seq.o \ + +obj-$(CONFIG_SND_OMAP_SOC_ABE_DSP) += snd-soc-abe-hal.o diff --git a/sound/soc/omap/abe/abe_api.c b/sound/soc/omap/abe/abe_api.c new file mode 100644 index 00000000000..a09ca1e1add --- /dev/null +++ b/sound/soc/omap/abe/abe_api.c @@ -0,0 +1,2040 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +#include "abe_typedef.h" +#include "abe_initxxx_labels.h" +#include "abe_dbg.h" +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/slab.h> + +u32 warm_boot = 0; + +/** + * abe_reset_hal - reset the ABE/HAL + * @rdev: regulator source + * @constraints: constraints to apply + * + * Operations : reset the HAL by reloading the static variables and + * default AESS registers. + * Called after a PRCM cold-start reset of ABE + */ +abehal_status abe_reset_hal(void) +{ + u32 i; + _log(id_reset_hal, 0, 0, 0); + abe_dbg_output = TERMINAL_OUTPUT; + abe_dbg_activity_log_write_pointer = 0; + /* IRQ & DBG circular read pointer in DMEM */ + abe_irq_dbg_read_ptr = 0; + /* PDM_DL enable/disable collisions */ + pdm_dl1_status = 0; + pdm_dl2_status = 0; + pdm_vib_status = 0; + /* default = disable the mixer's adaptive gain control */ + abe_use_compensated_gain(0); + /* reset the default gain values */ + for (i = 0; i < MAX_NBGAIN_CMEM; i++) { + abe_muted_gains_indicator[i] = 0; + abe_desired_gains_decibel[i] = (u32) GAIN_MUTE; + abe_desired_gains_linear[i] = 0; + abe_desired_ramp_delay_ms[i] = 0; + abe_muted_gains_decibel[i] = (u32) GAIN_TOOLOW; + } + /* set debug mask to "enable all traces" */ + abe_dbg_mask = (abe_dbg_t) (0); + abe_hw_configuration(); + return 0; +} +EXPORT_SYMBOL(abe_reset_hal); +/** + * abe_load_fw_param - Load ABE Firmware memories + * @PMEM: Pointer of Program memory data + * @PMEM_SIZE: Size of PMEM data + * @CMEM: Pointer of Coeffients memory data + * @CMEM_SIZE: Size of CMEM data + * @SMEM: Pointer of Sample memory data + * @SMEM_SIZE: Size of SMEM data + * @DMEM: Pointer of Data memory data + * @DMEM_SIZE: Size of DMEM data + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw_param(u32 *ABE_FW) +{ + u32 event_gen; + u32 pmem_size, dmem_size, smem_size, cmem_size; + u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr; + _log(id_load_fw_param, 0, 0, 0); +#if PC_SIMULATION + /* the code is loaded from the Checkers */ +#else +#define ABE_FW_OFFSET 5 + fw_ptr = ABE_FW; + abe_firmware_version_number = *fw_ptr++; + pmem_size = *fw_ptr++; + cmem_size = *fw_ptr++; + dmem_size = *fw_ptr++; + smem_size = *fw_ptr++; + pmem_ptr = fw_ptr; + cmem_ptr = pmem_ptr + (pmem_size >> 2); + dmem_ptr = cmem_ptr + (cmem_size >> 2); + smem_ptr = dmem_ptr + (dmem_size >> 2); + /* do not load PMEM */ + if (warm_boot) { + /* Stop the event Generator */ + event_gen = 0; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_START, &event_gen, 4); + /* Now we are sure the firmware is stalled */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr, + cmem_size); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr, + smem_size); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr, + dmem_size); + /* Restore the event Generator status */ + event_gen = 1; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_START, &event_gen, 4); + } else { + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, pmem_ptr, + pmem_size); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr, + cmem_size); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr, + smem_size); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr, + dmem_size); + } + warm_boot = 1; +#endif + return 0; +} +EXPORT_SYMBOL(abe_load_fw_param); +/** + * abe_load_fw - Load ABE Firmware and initialize memories + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw(void) +{ + _log(id_load_fw, 0, 0, 0); + abe_load_fw_param((u32 *) abe_firmware_array); + abe_reset_all_ports(); + abe_build_scheduler_table(); + abe_reset_all_sequence(); + abe_select_main_port(PDM_DL_PORT); + return 0; +} +EXPORT_SYMBOL(abe_load_fw); +/** + * abe_reload_fw - Reload ABE Firmware after OFF mode + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_reload_fw(void) +{ + warm_boot = 0; + abe_load_fw_param((u32 *) abe_firmware_array); + abe_build_scheduler_table(); + + /* IRQ & DBG circular read pointer in DMEM */ + abe_dbg_activity_log_write_pointer = 0; + abe_irq_dbg_read_ptr = 0; + + /* Restore Gains not managed by the drivers */ + abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + + return 0; +} +EXPORT_SYMBOL(abe_reload_fw); +/** + * abe_read_hardware_configuration - Return default HW periferals configuration + * @u: use-case description list (pointer) + * @o: opp mode (pointer) + * @hw: pointer to the output HW structure + * + * Parameter : + * U : use-case description list (pointer) + * H : pointer to the output structure + * + * Operations : + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + * will be upgraded in FW06 + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + */ +abehal_status abe_read_hardware_configuration(u32 *u, u32 *o, + abe_hw_config_init_t *hw) +{ + _log(id_read_hardware_configuration, (u32) u, + (u32) u >> 8, (u32) u >> 16); + abe_read_use_case_opp(u, o); + /* 0: 96kHz 1:192kHz */ + hw->MCPDM_CTRL__DIV_SEL = 0; + /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */ + hw->MCPDM_CTRL__CMD_INT = 1; + /* 0:MSB aligned 1:LSB aligned */ + hw->MCPDM_CTRL__PDMOUTFORMAT = 0; + hw->MCPDM_CTRL__PDM_DN5_EN = 1; + hw->MCPDM_CTRL__PDM_DN4_EN = 1; + hw->MCPDM_CTRL__PDM_DN3_EN = 1; + hw->MCPDM_CTRL__PDM_DN2_EN = 1; + hw->MCPDM_CTRL__PDM_DN1_EN = 1; + hw->MCPDM_CTRL__PDM_UP3_EN = 0; + hw->MCPDM_CTRL__PDM_UP2_EN = 1; + hw->MCPDM_CTRL__PDM_UP1_EN = 1; + /* All the McPDM_DL FIFOs are enabled simultaneously */ + hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER / 6; + /* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels + are enabled */ + hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER / 2; + /* 0:2.4MHz 1:3.84MHz */ + hw->DMIC_CTRL__DMIC_CLK_DIV = 0; + /* 0:MSB aligned 1:LSB aligned */ + hw->DMIC_CTRL__DMICOUTFORMAT = 0; + hw->DMIC_CTRL__DMIC_UP3_EN = 1; + hw->DMIC_CTRL__DMIC_UP2_EN = 1; + hw->DMIC_CTRL__DMIC_UP1_EN = 1; + /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ + hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER / 6; + /* MCBSP SPECIFICATION + RJUST = 00 Right justify data and zero fill MSBs in DRR[1,2] + RJUST = 01 Right justify data and sign extend it into the MSBs + in DRR[1,2] + RJUST = 10 Left justify data and zero fill LSBs in DRR[1,2] + MCBSPLP_RJUST_MODE_RIGHT_ZERO = 0x0, + MCBSPLP_RJUST_MODE_RIGHT_SIGN = 0x1, + MCBSPLP_RJUST_MODE_LEFT_ZERO = 0x2, + MCBSPLP_RJUST_MODE_MAX = MCBSPLP_RJUST_MODE_LEFT_ZERO + */ + hw->MCBSP_SPCR1_REG__RJUST = 2; + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1; + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1; + /* Slimbus IP FIFO thresholds */ + hw->SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD = 1; + /* 2050 gives about 96kHz */ + hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE = + EVENT_GENERATOR_COUNTER_DEFAULT; + /* 0: DMAreq, 1:Counter */ + hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1; + /* 5bits DMAreq selection */ + hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION = + ABE_ATC_MCPDMDL_DMA_REQ; + /* THE famous EVENT timer ! */ + hw->HAL_EVENT_SELECTION = EVENT_TIMER; + return 0; +} +EXPORT_SYMBOL(abe_read_hardware_configuration); +/** + * abe_irq_processing - Process ABE interrupt + * + * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio + * back-end interrupt. This subroutine will check the ATC Hrdware, the + * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated + * for the delivery of "end of time sequenced tasks" notifications, some are + * originated from the Ping-Pong protocols, some are generated from + * the embedded debugger when the firmware stops on programmable break-points, + * etc + */ +abehal_status abe_irq_processing(void) +{ + u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm; + abe_irq_data_t IRQ_data; +#define IrqFiFoMask ((D_McuIrqFifo_sizeof >> 2) -1) + _log(id_irq_processing, 0, 0, 0); + /* extract the write pointer index from CMEM memory (INITPTR format) */ + /* CMEM address of the write pointer in bytes */ + cmem_src = MCU_IRQ_FIFO_ptr_labelID << 2; + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_CMEM, cmem_src, + &sm_cm, sizeof(abe_irq_dbg_write_ptr)); + /* AESS left-pointer index located on MSBs */ + abe_irq_dbg_write_ptr = sm_cm >> 16; + abe_irq_dbg_write_ptr &= 0xFF; + /* loop on the IRQ FIFO content */ + for (i = 0; i < D_McuIrqFifo_sizeof; i++) { + /* stop when the FIFO is empty */ + if (abe_irq_dbg_write_ptr == abe_irq_dbg_read_ptr) + break; + /* read the IRQ/DBG FIFO */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + (D_McuIrqFifo_ADDR + + (abe_irq_dbg_read_ptr << 2)), + (u32 *) &IRQ_data, sizeof(IRQ_data)); + abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) &IrqFiFoMask; + /* select the source of the interrupt */ + switch (IRQ_data.tag) { + case IRQtag_APS: + _log(id_irq_processing, IRQ_data.data, 0, 1); + abe_irq_aps(IRQ_data.data); + break; + case IRQtag_PP: + _log(id_irq_processing, 0, 0, 2); + abe_irq_ping_pong(); + break; + case IRQtag_COUNT: + _log(id_irq_processing, IRQ_data.data, 0, 3); + abe_irq_check_for_sequences(IRQ_data.data); + break; + default: + break; + } + } + abe_monitoring(); + return 0; +} +EXPORT_SYMBOL(abe_irq_processing); +/** + * abe_clear_irq - clear ABE interrupt + * + * This subroutine is call to clear MCU Irq + */ +abehal_status abe_clear_irq(void) +{ + u32 clear_abe_irq = 1; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS, + &clear_abe_irq, 4); + + return 0; +} +EXPORT_SYMBOL(abe_clear_irq); +/** + * abe_select_main_port - Select stynchronization port for Event generator. + * @id: audio port name + * + * tells the FW which is the reference stream for adjusting + * the processing on 23/24/25 slots + */ +abehal_status abe_select_main_port(u32 id) +{ + u32 selection; + _log(id_select_main_port, id, 0, 0); + /* flow control */ + selection = D_IOdescr_ADDR + id * sizeof(ABE_SIODescriptor) + + flow_counter_; + /* when the main port is a sink port from AESS point of view + the sign the firmware task analysis must be changed */ + selection &= 0xFFFFL; + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) + selection |= 0x80000; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR, + &selection, 4); + return 0; +} +/** + * abe_write_event_generator - Select event generator source + * @e: Event Generation Counter, McPDM, DMIC or default. + * + * load the AESS event generator hardware source. Loads the firmware parameters + * accordingly. Indicates to the FW which data stream is the most important to preserve + * in case all the streams are asynchronous. If the parameter is "default", let the HAL + * decide which Event source is the best appropriate based on the opened ports. + * + * When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed + * with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher + * than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz + * The ratio is (MCLK/96000)+(1<<1) = 2050 + * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%) + */ +abehal_status abe_write_event_generator(u32 e) +{ + u32 event, selection, counter, start; + _log(id_write_event_generator, e, 0, 0); + counter = EVENT_GENERATOR_COUNTER_DEFAULT; + start = EVENT_GENERATOR_ON; + abe_current_event_id = e; + switch (e) { + case EVENT_TIMER: + selection = EVENT_SOURCE_COUNTER; + event = 0; + break; + case EVENT_44100: + selection = EVENT_SOURCE_COUNTER; + event = 0; + counter = EVENT_GENERATOR_COUNTER_44100; + break; + default: + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_BLOCK_COPY_ERR); + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_COUNTER, &counter, 4); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_SOURCE_SELECTION, &selection, 4); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_START, &start, 4); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + AUDIO_ENGINE_SCHEDULER, &event, 4); + return 0; +} +EXPORT_SYMBOL(abe_write_event_generator); +/** + * abe_stop_event_generator - Stop event generator source + * + * Stop the event genrator of AESS. No more event will be send to AESS engine. + * Upper layer needs to wait 1/96kHz to be sure that engine reach IDLE instruction + */ +abehal_status abe_stop_event_generator(void) +{ + u32 event_gen; + /* Stop the event Generator */ + event_gen = 0; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_START, &event_gen, 4); + return 0; +} +EXPORT_SYMBOL(abe_stop_event_generator); +/** + * abe_read_use_case_opp() - description for void abe_read_use_case_opp(). + * + * returns the expected min OPP for a given use_case list + */ +abehal_status abe_read_use_case_opp(u32 *u, u32 *o) +{ + u32 opp, i; + u32 *ptr = u; +#define MAX_READ_USE_CASE_OPP 10 +#define OPP_25 1 +#define OPP_50 2 +#define OPP_100 4 + _log(id_read_use_case_opp, (u32) u, (u32) u >> 8, (u32) u >> 16); + opp = i = 0; + do { + /* check for pointer errors */ + if (i > MAX_READ_USE_CASE_OPP) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_READ_USE_CASE_OPP_ERR); + break; + } + /* check for end_of_list */ + if (*ptr <= 0) + break; + /* OPP selection based on current firmware implementation */ + switch (*ptr) { + case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE: + opp |= OPP_25; + break; + case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER: + opp |= OPP_100; + break; + case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL: + opp |= OPP_100; + break; + case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT: + opp |= OPP_50; + break; + case ABE_MULTIMEDIA_AUDIO_RECORDER: + opp |= OPP_50; + break; + case ABE_VIBRATOR_OR_HAPTICS: + opp |= OPP_100; + break; + case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER: + opp |= OPP_100; + break; + case ABE_RINGER_TONES: + opp |= OPP_100; + break; + case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER: + opp |= OPP_100; + break; + default: + break; + } + i++; + ptr++; + } while (*ptr != 0); + if (opp & OPP_100) + *o = ABE_OPP100; + else if (opp & OPP_50) + *o = ABE_OPP50; + else + *o = ABE_OPP25; + return 0; +} +EXPORT_SYMBOL(abe_read_use_case_opp); +/** + * abe_set_opp_processing - Set OPP mode for ABE Firmware + * @opp: OOPP mode + * + * New processing network and OPP: + * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer) + * 1: OPP 25% (simple multimedia features, including low-power player) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% ( multimedia complex use-cases) + * + * Rearranges the FW task network to the corresponding OPP list of features. + * The corresponding AE ports are supposed to be set/reset accordingly before + * this switch. + * + */ +abehal_status abe_set_opp_processing(u32 opp) +{ + u32 dOppMode32, sio_desc_address; + _lock_enter; + _log(id_set_opp_processing, opp, 0, 0); + switch (opp) { + case ABE_OPP25: + /* OPP25% */ + dOppMode32 = DOPPMODE32_OPP25; + break; + case ABE_OPP50: + /* OPP50% */ + dOppMode32 = DOPPMODE32_OPP50; + break; + default: + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_BLOCK_COPY_ERR); + case ABE_OPP100: + /* OPP100% */ + dOppMode32 = DOPPMODE32_OPP100; + break; + } + /* Write Multiframe inside DMEM */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(u32)); + sio_desc_address = dmem_port_descriptors + (MM_EXT_IN_PORT * + sizeof(ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + if (dOppMode32 == DOPPMODE32_OPP100) { + /* ASRC input buffer, size 40 */ + sio_desc.smem_addr1 = smem_mm_ext_in_opp100; + /* Init MM_EXT_IN ASRC and enable its adaptation */ + abe_init_asrc_mm_ext_in(250); + } else + /* at OPP 50 or without ASRC */ + sio_desc.smem_addr1 = smem_mm_ext_in_opp50; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + sio_desc_address = dmem_port_descriptors + (BT_VX_UL_PORT * + sizeof(ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + if (dOppMode32 == DOPPMODE32_OPP100) { + /* ASRC input buffer, size 40 */ + sio_desc.smem_addr1 = smem_bt_vx_ul_opp100; + /* Init MM_EXT_IN ASRC and enable its adaptation */ + abe_init_asrc_bt_ul(250); + } else + /* at OPP 50 or without ASRC */ + sio_desc.smem_addr1 = smem_bt_vx_ul_opp50; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + sio_desc_address = dmem_port_descriptors + (BT_VX_DL_PORT * + sizeof(ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + if (dOppMode32 == DOPPMODE32_OPP100) { + /* ASRC input buffer, size 40 */ + sio_desc.smem_addr1 = smem_bt_vx_dl_opp100; + /* Init MM_EXT_IN ASRC and enable its adaptation */ + abe_init_asrc_bt_dl(250); + } else + /* at OPP 50 or without ASRC */ + sio_desc.smem_addr1 = smem_bt_vx_dl_opp50; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32 *) &sio_desc, sizeof(sio_desc)); + return 0; +} +EXPORT_SYMBOL(abe_set_opp_processing); +/** + * abe_set_ping_pong_buffer + * @port: ABE port ID + * @n_bytes: Size of Ping/Pong buffer + * + * Updates the next ping-pong buffer with "size" bytes copied from the + * host processor. This API notifies the FW that the data transfer is done. + */ +abehal_status abe_set_ping_pong_buffer(u32 port, u32 n_bytes) +{ + u32 sio_pp_desc_address, struct_offset, n_samples, datasize, + base_and_size, *src; + _log(id_set_ping_pong_buffer, port, n_bytes, n_bytes >> 8); + /* ping_pong is only supported on MM_DL */ + if (port != MM_DL_PORT) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + /* translates the number of bytes in samples */ + /* data size in DMEM words */ + datasize = abe_dma_port_iter_factor(&((abe_port[port]).format)); + /* data size in bytes */ + datasize = datasize << 2; + n_samples = n_bytes / datasize; + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_PingPongDesc_ADDR, + (u32 *) &desc_pp, sizeof(desc_pp)); + /* + * read the port SIO descriptor and extract the current pointer + * address after reading the counter + */ + if ((desc_pp.counter & 0x1) == 0) { + struct_offset = (u32) &(desc_pp.nextbuff0_BaseAddr) - + (u32) &(desc_pp); + base_and_size = desc_pp.nextbuff0_BaseAddr; + } else { + struct_offset = (u32) &(desc_pp.nextbuff1_BaseAddr) - + (u32) &(desc_pp); + base_and_size = desc_pp.nextbuff1_BaseAddr; + } + base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16); + sio_pp_desc_address = D_PingPongDesc_ADDR + struct_offset; + src = &base_and_size; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_pp_desc_address, + (u32 *) &base_and_size, sizeof(u32)); + return 0; +} +EXPORT_SYMBOL(abe_set_ping_pong_buffer); +/** + * abe_read_next_ping_pong_buffer + * @port: ABE portID + * @p: Next buffer address (pointer) + * @n: Next buffer size (pointer) + * + * Tell the next base address of the next ping_pong Buffer and its size + */ +abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n) +{ + u32 sio_pp_desc_address; + _log(id_read_next_ping_pong_buffer, port, 0, 0); + /* ping_pong is only supported on MM_DL */ + if (port != MM_DL_PORT) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + /* read the port SIO descriptor and extract the current pointer + address after reading the counter */ + sio_pp_desc_address = D_PingPongDesc_ADDR; + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, + (u32 *) &desc_pp, sizeof(ABE_SPingPongDescriptor)); + if ((desc_pp.counter & 0x1) == 0) { + _log(id_read_next_ping_pong_buffer, port, 0, 0); + *p = desc_pp.nextbuff0_BaseAddr; + } else { + _log(id_read_next_ping_pong_buffer, port, 1, 0); + *p = desc_pp.nextbuff1_BaseAddr; + } + /* translates the number of samples in bytes */ + *n = abe_size_pingpong; + return 0; +} +EXPORT_SYMBOL(abe_read_next_ping_pong_buffer); +/** + * abe_init_ping_pong_buffer + * @id: ABE port ID + * @size_bytes:size of the ping pong + * @n_buffers:number of buffers (2 = ping/pong) + * @p:returned address of the ping-pong list of base address (byte offset + from DMEM start) + * + * Computes the base address of the ping_pong buffers + */ +abehal_status abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers, + u32 *p) +{ + u32 i, dmem_addr; + _log(id_init_ping_pong_buffer, id, size_bytes, n_buffers); + /* ping_pong is supported in 2 buffers configuration right now but FW + is ready for ping/pong/pung/pang... */ + if (id != MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + for (i = 0; i < n_buffers; i++) { + dmem_addr = dmem_ping_pong_buffer + (i * size_bytes); + /* base addresses of the ping pong buffers in U8 unit */ + abe_base_address_pingpong[i] = dmem_addr; + } + /* global data */ + abe_size_pingpong = size_bytes; + *p = (u32) dmem_ping_pong_buffer; + return 0; +} +EXPORT_SYMBOL(abe_init_ping_pong_buffer); +/** + * abe_read_offset_from_ping_buffer + * @id: ABE port ID + * @n: returned address of the offset from the ping buffer start address expressed in samples + * + * Computes the current firmware ping pong read pointer location, expressed in samples, + * as the offset from the start address of ping buffer. + */ +abehal_status abe_read_offset_from_ping_buffer(u32 id, u32 *n) +{ + u32 sio_pp_desc_address; + /* ping_pong is only supported on MM_DL */ + if (MM_DL_PORT != id) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } else { + /* read the port SIO ping pong descriptor */ + sio_pp_desc_address = D_PingPongDesc_ADDR; + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_pp_desc_address, (u32 *) &desc_pp, + sizeof(ABE_SPingPongDescriptor)); + /* extract the current ping pong buffer read pointer based on + the value of the counter */ + if ((desc_pp.counter & 0x1) == 0) { + /* the next is buffer0, hence the current is buffer1 */ + if (abe_port[MM_DL_PORT].format.samp_format & + (MONO_MSB | MONO_RSHIFTED_16 | STEREO_16_16)) { + *n = abe_size_pingpong / 4 + + desc_pp.nextbuff1_Samples - + desc_pp.workbuff_Samples; + } else if (abe_port[MM_DL_PORT].format.samp_format & + (STEREO_MSB | STEREO_RSHIFTED_16)) { + *n = abe_size_pingpong / 8 + + desc_pp.nextbuff1_Samples - + desc_pp.workbuff_Samples; + } else { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + } else { + /* the next is buffer1, hence the current is buffer0 */ + *n = desc_pp.nextbuff0_Samples - + desc_pp.workbuff_Samples; + } + } + return 0; +} +EXPORT_SYMBOL(abe_read_offset_from_ping_buffer); +/** + * abe_plug_subroutine + * @id: returned sequence index after plugging a new subroutine + * @f: subroutine address to be inserted + * @n: number of parameters of this subroutine + * @params: pointer on parameters + * + * register a list of subroutines for call-back purpose + */ +abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n, + u32 *params) +{ + _log(id_plug_subroutine, (u32) (*id), (u32) f, n); + abe_add_subroutine(id, (abe_subroutine2) f, n, (u32 *) params); + return 0; +} +EXPORT_SYMBOL(abe_plug_subroutine); +/** + * abe_set_sequence_time_accuracy + * @fast: fast counter + * @slow: slow counter + * + */ +abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow) +{ + u32 data; + _log(id_set_sequence_time_accuracy, fast, slow, 0); + data = minimum(MAX_UINT16, fast / FW_SCHED_LOOP_FREQ_DIV1000); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_fastCounter_ADDR, + &data, sizeof(data)); + data = minimum(MAX_UINT16, slow / FW_SCHED_LOOP_FREQ_DIV1000); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_slowCounter_ADDR, + &data, sizeof(data)); + return 0; +} +EXPORT_SYMBOL(abe_set_sequence_time_accuracy); +/** + * abe_reset_port + * @id: ABE port ID + * + * stop the port activity and reload default parameters on the associated + * processing features. + * Clears the internal AE buffers. + */ +abehal_status abe_reset_port(u32 id) +{ + _log(id_reset_port, id, 0, 0); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + return 0; +} +EXPORT_SYMBOL(abe_reset_port); +/** + * abe_read_remaining_data + * @id: ABE port_ID + * @n: size pointer to the remaining number of 32bits words + * + * computes the remaining amount of data in the buffer. + */ +abehal_status abe_read_remaining_data(u32 port, u32 *n) +{ + u32 sio_pp_desc_address; + _log(id_read_remaining_data, port, 0, 0); + /* + * read the port SIO descriptor and extract the + * current pointer address after reading the counter + */ + sio_pp_desc_address = D_PingPongDesc_ADDR; + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, + (u32 *) &desc_pp, sizeof(ABE_SPingPongDescriptor)); + *n = desc_pp.workbuff_Samples; + return 0; +} +EXPORT_SYMBOL(abe_read_remaining_data); +/** + * abe_disable_data_transfer + * @id: ABE port id + * + * disables the ATC descriptor and stop IO/port activities + * disable the IO task (@f = 0) + * clear ATC DMEM buffer, ATC enabled + */ +abehal_status abe_disable_data_transfer(u32 id) +{ + abe_port_protocol_t *protocol; + _log(id_disable_data_transfer, id, 0, 0); + /* there is only one PDM_DL physical port shared + with DL1/DL2/VIB. Here is a check for the need to stop + PDM_DL if some activity is already on */ + if (id == PDM_DL1_PORT) { + pdm_dl1_status = 0; + if (pdm_dl2_status || pdm_vib_status) + return 0; + else + id = PDM_DL_PORT; + } + if (id == PDM_DL2_PORT) { + pdm_dl2_status = 0; + if (pdm_dl1_status || pdm_vib_status) + return 0; + else + id = PDM_DL_PORT; + } + if (id == PDM_VIB_PORT) { + pdm_vib_status = 0; + if (pdm_dl1_status || pdm_dl2_status) + return 0; + else + id = PDM_DL_PORT; + } + /* MM_DL managed in ping-pong */ + if (id == MM_DL_PORT) { + protocol = &(abe_port[MM_DL_PORT].protocol); + if (protocol->protocol_switch == PINGPONG_PORT_PROT) { + abe_disable_pp_io_task(MM_DL_PORT); + } + } + /* local host variable status= "port is running" */ + abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE; + /* disable DMA requests */ + abe_disable_dma_request(id); + /* disable ATC transfers */ + abe_init_atc(id); + abe_clean_temporary_buffers(id); + /* select the main port based on the desactivation of this port */ + abe_decide_main_port(); + return 0; +} +EXPORT_SYMBOL(abe_disable_data_transfer); +/** + * abe_enable_data_transfer + * @ip: ABE port id + * + * enables the ATC descriptor + * reset ATC pointers + * enable the IO task (@f <> 0) + */ +abehal_status abe_enable_data_transfer(u32 id) +{ + abe_port_protocol_t *protocol; + abe_data_format_t format; + _log(id_enable_data_transfer, id, 0, 0); + /* there is only one PDM_DL physical port shared + with DL1/DL2/VIB. Here is a check for the need to enable + PDM_DL when some activity is already on */ + if (id == PDM_DL1_PORT) { + id = PDM_DL_PORT; + if (pdm_dl1_status == 1) + return 0; + else + pdm_dl1_status = 1; + } + if (id == PDM_DL2_PORT) { + id = PDM_DL_PORT; + if (pdm_dl2_status == 1) + return 0; + else + pdm_dl2_status = 1; + } + if (id == PDM_VIB_PORT) { + id = PDM_DL_PORT; + if (pdm_vib_status == 1) + return 0; + else + pdm_vib_status = 1; + } + abe_clean_temporary_buffers(id); + if (id == PDM_UL_PORT) { + /* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */ + protocol = &(abe_port[PDM_UL_PORT].protocol); + format = abe_port[PDM_UL_PORT].format; + abe_init_atc(PDM_UL_PORT); + abe_init_io_tasks(PDM_UL_PORT, &format, protocol); + } + if (id == PDM_DL_PORT) { + /* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */ + protocol = &(abe_port[PDM_DL_PORT].protocol); + format = abe_port[PDM_DL_PORT].format; + abe_init_atc(PDM_DL_PORT); + abe_init_io_tasks(PDM_DL_PORT, &format, protocol); + } + /* MM_DL managed in ping-pong */ + if (id == MM_DL_PORT) { + protocol = &(abe_port[MM_DL_PORT].protocol); + if (protocol->protocol_switch == PINGPONG_PORT_PROT) { + abe_enable_pp_io_task(MM_DL_PORT); + } + } + if (id == DMIC_PORT) { + /* one DMIC port enabled = all DMICs enabled, + * since there is a single DMIC path for all DMICs */ + protocol = &(abe_port[DMIC_PORT].protocol); + format = abe_port[DMIC_PORT].format; + abe_init_atc(DMIC_PORT); + abe_init_io_tasks(DMIC_PORT, &format, protocol); + } + if (id == VX_UL_PORT) { + /* Init VX_UL ASRC and enable its adaptation */ + abe_init_asrc_vx_ul(250); + } + if (id == VX_DL_PORT) { + /* Init VX_DL ASRC and enable its adaptation */ + abe_init_asrc_vx_dl(250); + } + /* local host variable status= "port is running" */ + abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; + /* enable DMA requests */ + abe_enable_dma_request(id); + /* select the main port based on the activation of this new port */ + abe_decide_main_port(); + return 0; +} +EXPORT_SYMBOL(abe_enable_data_transfer); +/** + * abe_connect_cbpr_dmareq_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @a: returned pointer to the base address of the CBPr register and number of + * samples to exchange during a DMA_request. + * + * enables the data echange between a DMA and the ABE through the + * CBPr registers of AESS. + */ +abehal_status abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d, + abe_dma_t *returned_dma_t) +{ + _log(id_connect_cbpr_dmareq_port, id, f->f, f->samp_format); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT; + abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f); + abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW; + abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d); + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the dma_t with physical information from AE memory mapping */ + abe_init_dma_t(id, &((abe_port[id]).protocol)); + /* load the ATC descriptors - disabled */ + abe_init_atc(id); + /* return the dma pointer address */ + abe_read_port_address(id, returned_dma_t); + return 0; +} +EXPORT_SYMBOL(abe_connect_cbpr_dmareq_port); +/** + * abe_connect_dmareq_ping_pong_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @s: half-buffer (ping) size + * @a: returned pointer to the base address of the ping-pong buffer and number + * of samples to exchange during a DMA_request. + * + * enables the data echanges between a DMA and a direct access to + * the DMEM memory of ABE. On each dma_request activation the DMA will exchange + * "s" bytes and switch to the "pong" buffer for a new buffer exchange. + */ +abehal_status abe_connect_dmareq_ping_pong_port(u32 id, abe_data_format_t *f, + u32 d, u32 s, + abe_dma_t *returned_dma_t) +{ + abe_dma_t dma1; + _log(id_connect_dmareq_ping_pong_port, id, f->f, f->samp_format); + /* ping_pong is only supported on MM_DL */ + if (id != MM_DL_PORT) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + /* declare PP buffer and prepare the returned dma_t */ + abe_init_ping_pong_buffer(MM_DL_PORT, s, 2, + (u32 *) &(returned_dma_t->data)); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT; + (abe_port[id]).protocol.p.prot_pingpong.buf_addr = + dmem_ping_pong_buffer; + (abe_port[id]).protocol.p.prot_pingpong.buf_size = s; + (abe_port[id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW; + (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1 << d); + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters DESC_IO_PP */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the dma_t with physical information from AE memory mapping */ + abe_init_dma_t(id, &((abe_port[id]).protocol)); + dma1.data = (u32 *) (abe_port[id].dma.data + ABE_DMEM_BASE_ADDRESS_L3); + dma1.iter = abe_port[id].dma.iter; + *returned_dma_t = dma1; + return 0; +} +EXPORT_SYMBOL(abe_connect_dmareq_ping_pong_port); +/** + * abe_connect_irq_ping_pong_port + * @id: port name + * @f: desired data format + * @I: index of the call-back subroutine to call + * @s: half-buffer (ping) size + * @p: returned base address of the first (ping) buffer) + * + * enables the data echanges between a direct access to the DMEM + * memory of ABE using cache flush. On each IRQ activation a subroutine + * registered with "abe_plug_subroutine" will be called. This subroutine + * will generate an amount of samples, send them to DMEM memory and call + * "abe_set_ping_pong_buffer" to notify the new amount of samples in the + * pong buffer. + */ +abehal_status abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f, + u32 subroutine_id, u32 size, + u32 *sink, u32 dsp_mcu_flag) +{ + _log(id_connect_irq_ping_pong_port, id, f->f, f->samp_format); + /* ping_pong is only supported on MM_DL */ + if (id != MM_DL_PORT) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT; + (abe_port[id]).protocol.p.prot_pingpong.buf_addr = + dmem_ping_pong_buffer; + (abe_port[id]).protocol.p.prot_pingpong.buf_size = size; + (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1); + abe_init_ping_pong_buffer(MM_DL_PORT, size, 2, sink); + if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ) + (abe_port[id]).protocol.p.prot_pingpong.irq_addr = + ABE_MCU_IRQSTATUS_RAW; + if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ) + (abe_port[id]).protocol.p.prot_pingpong.irq_addr = + ABE_DSP_IRQSTATUS_RAW; + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the ATC descriptors - disabled */ + abe_init_atc(id); + *sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr; + return 0; +} +EXPORT_SYMBOL(abe_connect_irq_ping_pong_port); +/** + * abe_connect_serial_port() + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * + * Operations : enables the data echanges between a McBSP and an ATC buffer in + * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz + * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the + * abe_write_port API. + */ +abehal_status abe_connect_serial_port(u32 id, abe_data_format_t *f, + u32 mcbsp_id) +{ + u32 UC_NULL[] = { 0 }; + u32 OPP; + abe_hw_config_init_t CONFIG; + _log(id_connect_serial_port, id, f->samp_format, mcbsp_id); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + (abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT; + /* McBSP peripheral connected to ATC */ + (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE; + /* check the iteration of ATC */ + abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG); + (abe_port[id]).protocol.p.prot_serial.iter = + abe_dma_port_iter_factor(f); + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the ATC descriptors - disabled */ + abe_init_atc(id); + return 0; +} +EXPORT_SYMBOL(abe_connect_serial_port); +/** + * abe_connect_slimbus_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between 1/2 SB and an ATC buffers in + * DMEM. + */ +abehal_status abe_connect_slimbus_port(u32 id, abe_data_format_t *f, + u32 sb_port1, u32 sb_port2) +{ + u32 UC_NULL[] = { + 0 + }; + u32 OPP; + abe_hw_config_init_t CONFIG; + u32 iter; + _log(id_connect_slimbus_port, id, f->samp_format, sb_port2); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + (abe_port[id]).protocol.protocol_switch = SLIMBUS_PORT_PROT; + /* SB1 peripheral connected to ATC */ + (abe_port[id]).protocol.p.prot_slimbus.desc_addr1 = sb_port1*ATC_SIZE; + /* SB2 peripheral connected to ATC */ + (abe_port[id]).protocol.p.prot_slimbus.desc_addr2 = sb_port2*ATC_SIZE; + /* check the iteration of ATC */ + abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG); + iter = CONFIG.SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD; + /* SLIMBUS iter should be 1 */ + (abe_port[id]).protocol.p.prot_serial.iter = iter; + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the ATC descriptors - disabled */ + abe_init_atc(id); + return 0; +} +EXPORT_SYMBOL(abe_connect_slimbus_port); +/** + * abe_connect_tdm_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between TDM McBSP ATC buffers in + * DMEM and 1/2 SMEM buffers + */ +abehal_status abe_connect_tdm_port(u32 id, abe_data_format_t *f, u32 mcbsp_id) +{ + u32 UC_NULL[] = { 0 }; + u32 OPP; + abe_hw_config_init_t CONFIG; + u32 iter; + _log(id_connect_tdm_port, id, f->samp_format, mcbsp_id); + abe_port[id] = ((abe_port_t *) abe_port_init)[id]; + (abe_port[id]).format = (*f); + (abe_port[id]).protocol.protocol_switch = TDM_SERIAL_PORT_PROT; + /* McBSP peripheral connected to ATC */ + (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE; + /* check the iteration of ATC */ + abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG); + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) + iter = CONFIG.MCBSP_THRSH1_REG_REG__RTHRESHOLD; + else + iter = CONFIG.MCBSP_THRSH2_REG_REG__XTHRESHOLD; + /* McBSP iter should be 1 */ + (abe_port[id]).protocol.p.prot_serial.iter = iter; + abe_port[id].status = OMAP_ABE_PORT_INITIALIZED; + /* load the micro-task parameters */ + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); + /* load the ATC descriptors - disabled */ + abe_init_atc(id); + return 0; +} +EXPORT_SYMBOL(abe_connect_tdm_port); +/** + * abe_read_port_address + * @dma: output pointer to the DMA iteration and data destination pointer + * + * This API returns the address of the DMA register used on this audio port. + * Depending on the protocol being used, adds the base address offset L3 + * (DMA) or MPU (ARM) + */ +abehal_status abe_read_port_address(u32 port, abe_dma_t *dma2) +{ + abe_dma_t_offset dma1; + u32 protocol_switch; + _log(id_read_port_address, port, 0, 0); + dma1 = (abe_port[port]).dma; + protocol_switch = abe_port[port].protocol.protocol_switch; + switch (protocol_switch) { + case PINGPONG_PORT_PROT: + /* return the base address of the buffer in L3 and L4 spaces */ + (*dma2).data = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l3_dmem = + (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l4_dmem = + (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L4); + break; + case DMAREQ_PORT_PROT: + /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */ + (*dma2).data = (void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3); + (*dma2).l3_dmem = + (void *)((abe_port[port]).protocol.p.prot_dmareq. + buf_addr + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l4_dmem = + (void *)((abe_port[port]).protocol.p.prot_dmareq. + buf_addr + ABE_DMEM_BASE_ADDRESS_L4); + break; + default: + break; + } + (*dma2).iter = (dma1.iter); + return 0; +} +EXPORT_SYMBOL(abe_read_port_address); +/* + * ABE_SELECT_DATA_SOURCE + * + * Parameter : + * port id where data are exchanged + * data_cource_id among: + * SRC_DL1_MIXER_OUTPUT (DL1_M_labelID) + * SRC_SDT_MIXER_OUTPUT (SDT_M_labelID) + * SRC_DL1_GAIN_OUTPUT (DL1_GAIN_out_labelID) + * SRC_DL1_EQ_OUTPUT (DL1_EQ_labelID) + * SRC_DL2_GAIN_OUTPUT (DL2_GAIN_out_labelID) + * SRC_DL2_EQ_OUTPUT (DL2_EQ_labelID) + * SRC_MM_DL (MM_DL_labelID) + * SRC_TONES_DL (Tones_labelID) + * SRC_VX_DL (VX_DL_labelID) + * SRC_VX_UL (VX_UL_labelID) + * SRC_MM_UL2 (MM_UL2_labelID) + * SRC_MM_UL (MM_UL_labelID) + * + * Operations : + * + * Return value : + * None. + */ +abehal_status abe_select_data_source(u32 port_id, u32 smem_source) +{ + u32 sio_desc_address; + sio_desc_address = dmem_port_descriptors + + (port_id * sizeof(ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_desc_address, (u32 *) &sio_desc, sizeof(sio_desc)); + sio_desc.smem_addr1 = (u16) smem_source; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address, (u32 *) &sio_desc, sizeof(sio_desc)); + return 0; +} +EXPORT_SYMBOL(abe_select_data_source); +/** + * abe_write_equalizer + * @id: name of the equalizer + * @param : equalizer coefficients + * + * Load the coefficients in CMEM. + */ +abehal_status abe_write_equalizer(u32 id, abe_equ_t *param) +{ + u32 eq_offset, length, *src, eq_mem, eq_mem_len; + _log(id_write_equalizer, id, 0, 0); + switch (id) { + default: + case EQ1: + eq_offset = C_DL1_Coefs_ADDR; + eq_mem = S_DL1_M_EQ_data_ADDR; + eq_mem_len = S_DL1_M_EQ_data_sizeof; + break; + case EQ2L: + eq_offset = C_DL2_L_Coefs_ADDR; + eq_mem = S_DL2_M_LR_EQ_data_ADDR; + eq_mem_len = S_DL2_M_LR_EQ_data_sizeof; + break; + case EQ2R: + eq_offset = C_DL2_R_Coefs_ADDR; + eq_mem = S_DL2_M_LR_EQ_data_ADDR; + eq_mem_len = S_DL2_M_LR_EQ_data_sizeof; + break; + case EQSDT: + eq_offset = C_SDT_Coefs_ADDR; + eq_mem = S_SDT_F_data_ADDR; + eq_mem_len = S_SDT_F_data_sizeof; + break; + case EQAMIC: + eq_offset = C_96_48_AMIC_Coefs_ADDR; + eq_mem = S_AMIC_96_48_data_ADDR; + eq_mem_len = S_AMIC_96_48_data_sizeof; + break; + case EQDMIC: + eq_offset = C_96_48_DMIC_Coefs_ADDR; + eq_mem = S_DMIC0_96_48_data_ADDR; + eq_mem_len = S_DMIC0_96_48_data_sizeof; + /* three DMIC are clear at the same time DMIC0 DMIC1 DMIC2 */ + eq_mem_len *= 3; + break; + case APS1: + eq_offset = C_APS_DL1_coeffs1_ADDR; + eq_mem = S_APS_IIRmem1_ADDR; + eq_mem_len = S_APS_IIRmem1_sizeof; + break; + case APS2L: + eq_offset = C_APS_DL2_L_coeffs1_ADDR; + eq_mem = S_APS_M_IIRmem2_ADDR; + eq_mem_len = S_APS_M_IIRmem2_sizeof; + break; + case APS2R: + eq_offset = C_APS_DL2_R_coeffs1_ADDR; + eq_mem = S_APS_M_IIRmem2_ADDR; + eq_mem_len = S_APS_M_IIRmem2_sizeof; + break; + } + length = param->equ_length; + src = (u32 *) ((param->coef).type1); + /* translate in bytes */ + eq_offset <<= 2; + /* reset SMEM buffers before the coefficients are loaded */ + abe_reset_mem(ABE_SMEM, eq_mem << 3, eq_mem_len << 3); + /* translate in bytes */ + length <<= 2; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, src, length); + /* reset SMEM buffers after the coefficients are loaded */ + abe_reset_mem(ABE_SMEM, eq_mem << 3, eq_mem_len << 3); + return 0; +} +EXPORT_SYMBOL(abe_write_equalizer); +/** + * abe_write_asrc + * @id: name of the port + * @param: drift value to compensate [ppm] + * + * Load the drift variables to the FW memory. This API can be called only + * when the corresponding port has been already opened and the ASRC has + * been correctly initialized with API abe_init_asrc_... If this API is + * used such that the drift has been changed from positive to negative drift + * or vice versa, there will be click in the output signal. Loading the drift + * value with zero disables the feature. + */ +abehal_status abe_write_asrc(u32 port, s32 dppm) +{ + s32 dtempvalue, adppm, drift_sign, drift_sign_addr, alpha_params_addr; + s32 alpha_params[3]; + _log(id_write_asrc, port, dppm, dppm >> 8); + /* + * x = ppm + * + * - 1000000/x must be multiple of 16 + * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits. + * then shifted by 2bits + * - minusdeltaalpha + * - oneminusepsilon = 1-deltaalpha/2. + * + * ppm = 250 + * - 1000000/250=4000 + * - deltaalpha = 4194.3 ~ 4195 => 0x00418c + */ + /* examples for -6250 ppm */ + /* atempvalue32[1] = -1; d_driftsign */ + /* atempvalue32[3] = 0x00066668; d_deltaalpha */ + /* atempvalue32[4] = 0xfff99998; d_minusdeltaalpha */ + /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */ + /* example for 100 ppm */ + /* atempvalue32[1] = 1;* d_driftsign */ + /* atempvalue32[3] = 0x00001a38; d_deltaalpha */ + /* atempvalue32[4] = 0xffffe5c8; d_minusdeltaalpha */ + /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */ + /* compute new value for the ppm */ + if (dppm >= 0) { + /* d_driftsign */ + drift_sign = 1; + adppm = dppm; + } else { + /* d_driftsign */ + drift_sign = -1; + adppm = (-1 * dppm); + } + if (dppm == 0) { + /* delta_alpha */ + alpha_params[0] = 0; + /* minusdelta_alpha */ + alpha_params[1] = 0; + /* one_minusepsilon */ + alpha_params[2] = 0x003ffff0; + } else { + dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + /* delta_alpha */ + alpha_params[0] = dtempvalue << 2; + /* minusdelta_alpha */ + alpha_params[1] = (-dtempvalue) << 2; + /* one_minusepsilon */ + alpha_params[2] = (0x00100000 - (dtempvalue / 2)) << 2; + } + switch (port) { + /* asynchronous sample-rate-converter for the uplink voice path */ + case VX_DL_PORT: + drift_sign_addr = D_AsrcVars_DL_VX_ADDR + (1 * sizeof(s32)); + alpha_params_addr = D_AsrcVars_DL_VX_ADDR + (3 * sizeof(s32)); + break; + /* asynchronous sample-rate-converter for the downlink voice path */ + case VX_UL_PORT: + drift_sign_addr = D_AsrcVars_UL_VX_ADDR + (1 * sizeof(s32)); + alpha_params_addr = D_AsrcVars_UL_VX_ADDR + (3 * sizeof(s32)); + break; + /* asynchronous sample-rate-converter for the BT_UL path */ + case BT_VX_UL_PORT: + drift_sign_addr = D_AsrcVars_BT_UL_ADDR + (1 * sizeof(s32)); + alpha_params_addr = D_AsrcVars_BT_UL_ADDR + (3 * sizeof(s32)); + break; + /* asynchronous sample-rate-converter for the BT_DL path */ + case BT_VX_DL_PORT: + drift_sign_addr = D_AsrcVars_BT_DL_ADDR + (1 * sizeof(s32)); + alpha_params_addr = D_AsrcVars_BT_DL_ADDR + (3 * sizeof(s32)); + break; + default: + /* asynchronous sample-rate-converter for the MM_EXT_IN path */ + case MM_EXT_IN_PORT: + drift_sign_addr = D_AsrcVars_MM_EXT_IN_ADDR + (1 * sizeof(s32)); + alpha_params_addr = + D_AsrcVars_MM_EXT_IN_ADDR + (3 * sizeof(s32)); + break; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, drift_sign_addr, + (u32 *) &drift_sign, 4); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, alpha_params_addr, + (u32 *) &alpha_params[0], 12); + return 0; +} +EXPORT_SYMBOL(abe_write_asrc); +/** + * abe_write_aps + * @id: name of the aps filter + * @param: table of filter coefficients + * + * Load the filters and thresholds coefficients in FW memory. This AP + * can be called when the corresponding APS is not activated. After + * reloading the firmware the default coefficients corresponds to "no APS + * activated". + * Loading all the coefficients value with zero disables the feature. + */ +abehal_status abe_write_aps(u32 id, abe_aps_t *param) +{ + _log(id_write_aps, id, 0, 0); + return 0; +} +EXPORT_SYMBOL(abe_write_aps); +/** + * abe_use_compensated_gain + * @on_off: + * + * Selects the automatic Mixer's gain management + * on_off = 1 allows the "abe_write_gain" to adjust the overall + * gains of the mixer to be tuned not to create saturation + */ +abehal_status abe_use_compensated_gain(u32 on_off) +{ + abe_compensated_mixer_gain = on_off; + return 0; +} +EXPORT_SYMBOL(abe_use_compensated_gain); +/** + * abe_disable_gain + * Parameters: + * mixer id + * sub-port id + * + */ +abehal_status abe_disable_gain(u32 id, u32 p) +{ + u32 mixer_offset, f_g, ramp; + abe_gain_offset(id, &mixer_offset); + /* save the input parameters for mute/unmute */ + ramp = abe_desired_ramp_delay_ms[mixer_offset + p]; + f_g = GAIN_MUTE; + if (!(abe_muted_gains_indicator[mixer_offset + p] & 0x02)) { + /* Check if we are in mute */ + if (!(abe_muted_gains_indicator[mixer_offset + p] & 0x01)) { + abe_muted_gains_decibel[mixer_offset + p] = + abe_desired_gains_decibel[mixer_offset + p]; + /* mute the gain */ + abe_write_gain(id, f_g, ramp, p); + } + abe_muted_gains_indicator[mixer_offset + p] |= 0x02; + } + return 0; +} +EXPORT_SYMBOL(abe_disable_gain); +/** + * abe_enable_gain + * Parameters: + * mixer id + * sub-port id + * + */ +abehal_status abe_enable_gain(u32 id, u32 p) +{ + u32 mixer_offset, f_g, ramp; + abe_gain_offset(id, &mixer_offset); + if ((abe_muted_gains_indicator[mixer_offset + p] & 0x02)) { + /* restore the input parameters for mute/unmute */ + f_g = abe_muted_gains_decibel[mixer_offset + p]; + ramp = abe_desired_ramp_delay_ms[mixer_offset + p]; + abe_muted_gains_indicator[mixer_offset + p] &= ~0x02; + /* unmute the gain */ + abe_write_gain(id, f_g, ramp, p); + } + return 0; +} +EXPORT_SYMBOL(abe_enable_gain); +/** + * abe_mute_gain + * Parameters: + * mixer id + * sub-port id + * + */ +abehal_status abe_mute_gain(u32 id, u32 p) +{ + u32 mixer_offset, f_g, ramp; + abe_gain_offset(id, &mixer_offset); + /* save the input parameters for mute/unmute */ + ramp = abe_desired_ramp_delay_ms[mixer_offset + p]; + f_g = GAIN_MUTE; + if (!abe_muted_gains_indicator[mixer_offset + p]) { + abe_muted_gains_decibel[mixer_offset + p] = + abe_desired_gains_decibel[mixer_offset + p]; + /* mute the gain */ + abe_write_gain(id, f_g, ramp, p); + } + abe_muted_gains_indicator[mixer_offset + p] |= 0x01; + return 0; +} +EXPORT_SYMBOL(abe_mute_gain); +/** + * abe_unmute_gain + * Parameters: + * mixer id + * sub-port id + * + */ +abehal_status abe_unmute_gain(u32 id, u32 p) +{ + u32 mixer_offset, f_g, ramp; + abe_gain_offset(id, &mixer_offset); + if ((abe_muted_gains_indicator[mixer_offset + p] & 0x01)) { + /* restore the input parameters for mute/unmute */ + f_g = abe_muted_gains_decibel[mixer_offset + p]; + ramp = abe_desired_ramp_delay_ms[mixer_offset + p]; + abe_muted_gains_indicator[mixer_offset + p] &= ~0x01; + /* unmute the gain */ + abe_write_gain(id, f_g, ramp, p); + } + return 0; +} +EXPORT_SYMBOL(abe_unmute_gain); +/** + * abe_write_mixer + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's gain + * in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p) +{ + u32 lin_g, sum_g, mixer_target, mixer_offset, i, mean_gain, mean_exp; + u32 new_gain_linear[4]; + s32 gain_index; + u32 alpha, beta; + u32 ramp_index; + _log(id_write_gain, id, f_g, p); + gain_index = ((f_g - min_mdb) / 100); + gain_index = maximum(gain_index, 0); + gain_index = minimum(gain_index, sizeof_db2lin_table); + lin_g = abe_db2lin_table[gain_index]; + abe_gain_offset(id, &mixer_offset); + /* save the input parameters for mute/unmute */ + abe_desired_gains_linear[mixer_offset + p] = lin_g; + abe_desired_gains_decibel[mixer_offset + p] = f_g; + abe_desired_ramp_delay_ms[mixer_offset + p] = ramp; + /* SMEM word32 address */ + mixer_target = (S_GTarget1_ADDR << 1); + mixer_target += mixer_offset; + mixer_target += p; + /* translate coef address in Bytes */ + mixer_target <<= 2; + if (abe_compensated_mixer_gain) { + switch (id) { + case MIXDL1: + case MIXDL2: + case MIXVXREC: + case MIXAUDUL: + /* compute the sum of the gain of the mixer */ + for (sum_g = i = 0; i < 4; i++) + sum_g += abe_desired_gains_linear[mixer_offset + + i]; + /* lets avoid a division by 0 */ + if (sum_g == 0) + break; + /* if the sum is OK with less than 1, then + do not weight the gains */ + if (sum_g < 0x00040000) { /* REMOVE HARD CONST */ + /* recompute all gains from original + desired values */ + sum_g = 0x00040000; + } + /* translate it in Q16 format for the later division */ + abe_int_2_float16(sum_g, &mean_gain, &mean_exp); + mean_exp = 10 - mean_exp; + for (i = 0; i < 4; i++) { + /* new gain = desired gain divided by sum of gains */ + new_gain_linear[i] = + (abe_desired_gains_linear + [mixer_offset + i] + << 8) / mean_gain; + new_gain_linear[i] = (mean_exp > 0) ? + new_gain_linear[i] << mean_exp : + new_gain_linear[i] >> mean_exp; + } + /* load the whole adpated S_G_Target SMEM MIXER table */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + mixer_target - (p << 2), + new_gain_linear, (4 * sizeof(lin_g))); + break; + default: + /* load the S_G_Target SMEM table */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + mixer_target, + (u32 *) &lin_g, sizeof(lin_g)); + break; + } + } else { + if (!abe_muted_gains_indicator[mixer_offset + p]) + /* load the S_G_Target SMEM table */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + mixer_target, (u32 *) &lin_g, + sizeof(lin_g)); + else + /* update muted gain with new value */ + abe_muted_gains_decibel[mixer_offset + p] = f_g; + } + ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH); + /* ramp data should be interpolated in the table instead */ + ramp_index = 8; + if ((RAMP_5MS <= ramp) && (ramp < RAMP_50MS)) + ramp_index = 24; + if ((RAMP_50MS <= ramp) && (ramp < RAMP_500MS)) + ramp_index = 36; + if (ramp > RAMP_500MS) + ramp_index = 48; + beta = abe_alpha_iir[ramp_index]; + alpha = abe_1_alpha_iir[ramp_index]; + /* CMEM word32 address */ + mixer_target = C_1_Alpha_ADDR; + /* a pair of gains is updated once in the firmware */ + mixer_target += (p + mixer_offset) >> 1; + /* translate coef address in Bytes */ + mixer_target <<= 2; + /* load the ramp delay data */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target, + (u32 *) &alpha, sizeof(alpha)); + /* CMEM word32 address */ + mixer_target = C_Alpha_ADDR; + /* a pair of gains is updated once in the firmware */ + mixer_target += (p + mixer_offset) >> 1; + /* translate coef address in Bytes */ + mixer_target <<= 2; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target, + (u32 *) &beta, sizeof(beta)); + return 0; +} +EXPORT_SYMBOL(abe_write_gain); +/** + * abe_write_mixer + * @id: name of the mixer + * @param: input gains and delay ramp of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p) +{ + _log(id_write_mixer, id, f_ramp, p); + abe_write_gain(id, f_g, f_ramp, p); + return 0; +} +EXPORT_SYMBOL(abe_write_mixer); +/** + * abe_read_gain + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + */ +abehal_status abe_read_gain(u32 id, u32 *f_g, u32 p) +{ + u32 mixer_target, mixer_offset, i; + _log(id_read_gain, id, (u32) f_g, p); + abe_gain_offset(id, &mixer_offset); + /* SMEM word32 address */ + mixer_target = (S_GTarget1_ADDR << 1); + mixer_target += mixer_offset; + mixer_target += p; + /* translate coef address in Bytes */ + mixer_target <<= 2; + + if (!abe_muted_gains_indicator[mixer_offset + p]) { + /* load the S_G_Target SMEM table */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_SMEM, mixer_target, + (u32 *) f_g, sizeof(*f_g)); + for (i = 0; i < sizeof_db2lin_table; i++) { + if (abe_db2lin_table[i] == *f_g) + goto found; + } + *f_g = 0; + return -1; + found: + *f_g = (i * 100) + min_mdb; + } else { + /* update muted gain with new value */ + *f_g = abe_muted_gains_decibel[mixer_offset + p]; + } + + return 0; +} +EXPORT_SYMBOL(abe_read_gain); +/** + * abe_read_mixer + * @id: name of the mixer + * @param: gains of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_read_mixer(u32 id, u32 *f_g, u32 p) +{ + _log(id_read_mixer, id, 0, p); + abe_read_gain(id, f_g, p); + return 0; +} +EXPORT_SYMBOL(abe_read_mixer); +/** + * abe_set_router_configuration + * @Id: name of the router + * @Conf: id of the configuration + * @param: list of output index of the route + * + * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) + * and PORT1/2 (2 stereo ports). Each sample will be individually stored in + * an intermediate table of 10 elements. + * + * Example of router table parameter for voice uplink with phoenix microphones + * + * indexes 0 .. 9 = MM_UL description (digital MICs and MMEXTIN) + * DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + * MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID, + * ZERO_labelID, ZERO_labelID, + * indexes 10 .. 11 = MM_UL2 description (recording on DMIC3) + * DMIC3_L_labelID, DMIC3_R_labelID, + * indexes 12 .. 13 = VX_UL description (VXUL based on PDMUL data) + * AMIC_L_labelID, AMIC_R_labelID, + * indexes 14 .. 15 = RESERVED (NULL) + * ZERO_labelID, ZERO_labelID, + */ +abehal_status abe_set_router_configuration(u32 id, u32 k, u32 *param) +{ + _log(id_set_router_configuration, id, (u32) param, (u32) param >> 8); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_aUplinkRouting_ADDR, param, D_aUplinkRouting_sizeof); + return 0; +} +EXPORT_SYMBOL(abe_set_router_configuration); +/** + * ABE_READ_DEBUG_TRACE + * + * Parameter : + * data destination pointer + * max number of data read + * + * Operations : + * reads the AE circular data pointer holding pairs of debug data+ + * timestamps, and store the pairs in linear addressing to the parameter + * pointer. Stops the copy when the max parameter is reached or when the + * FIFO is empty. + * + * Return value : + * None. + */ +abehal_status abe_read_debug_trace(u32 *data, u32 *n) +{ + _log(id_select_data_source, 0, 0, 0); + return 0; +} +EXPORT_SYMBOL(abe_read_debug_trace); +/** + * abe_connect_debug_trace + * @dma2:pointer to the DMEM trace buffer + * + * returns the address and size of the real-time debug trace buffer, + * the content of which will vary from one firmware release to an other + */ +abehal_status abe_connect_debug_trace(abe_dma_t *dma2) +{ + _log(id_connect_debug_trace, 0, 0, 0); + /* return the base address of the ping buffer in L3 and L4 spaces */ + (*dma2).data = (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l3_dmem = + (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l4_dmem = + (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L4); + (*dma2).iter = D_DEBUG_FIFO_sizeof; + return 0; +} +EXPORT_SYMBOL(abe_connect_debug_trace); +/** + * abe_set_debug_trace + * @debug: debug ID from a list to be defined + * + * load a mask which filters the debug trace to dedicated types of data + */ +abehal_status abe_set_debug_trace(abe_dbg_t debug) +{ + _log(id_set_debug_trace, 0, 0, 0); + abe_dbg_mask = debug; + return 0; +} +EXPORT_SYMBOL(abe_set_debug_trace); +/** + * abe_remote_debugger_interface + * + * interpretation of the UART stream from the remote debugger commands. + * The commands consist in setting break points, loading parameter + */ +abehal_status abe_remote_debugger_interface(u32 n, u8 *p) +{ + _log(id_remote_debugger_interface, n, 0, 0); + return 0; +} +EXPORT_SYMBOL(abe_remote_debugger_interface); +/** + * abe_enable_test_pattern + * + */ +abehal_status abe_enable_test_pattern(u32 smem_id, u32 on_off) +{ + u16 dbg_on, dbg_off, idx_patch, task_patch, addr_patch; + u32 patch, task32; + _log(id_enable_test_pattern, on_off, smem_id, smem_id >> 8); + switch (smem_id) { + case DBG_PATCH_AMIC: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = AMIC_labelID; + task_patch = C_ABE_FW_TASK_AMIC_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_DMIC1: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = DMIC1_labelID; + task_patch = C_ABE_FW_TASK_DMIC1_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_DMIC2: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = DMIC2_labelID; + task_patch = C_ABE_FW_TASK_DMIC2_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_DMIC3: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = DMIC3_labelID; + task_patch = C_ABE_FW_TASK_DMIC3_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_VX_REC: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = VX_REC_labelID; + task_patch = C_ABE_FW_TASK_VXREC_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_BT_UL: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = BT_UL_labelID; + task_patch = C_ABE_FW_TASK_BT_UL_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_MM_DL: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = MM_DL_labelID; + task_patch = C_ABE_FW_TASK_MM_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_DL2_EQ: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = DL2_EQ_labelID; + task_patch = C_ABE_FW_TASK_DL2_APS_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_VIBRA: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = VIBRA_labelID; + task_patch = C_ABE_FW_TASK_VIBRA_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_MM_EXT_IN: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = MM_EXT_IN_labelID; + task_patch = C_ABE_FW_TASK_MM_EXT_IN_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_MIC4: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = MIC4_labelID; + task_patch = C_ABE_FW_TASK_MIC4_SPLIT; + idx_patch = 1; + break; + case DBG_PATCH_MM_DL_MIXDL1: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = AMIC_labelID; + task_patch = C_ABE_FW_TASK_DL1Mixer; + idx_patch = 1; + break; + case DBG_PATCH_MM_DL_MIXDL2: + dbg_on = DBG_48K_PATTERN_labelID; + dbg_off = AMIC_labelID; + task_patch = C_ABE_FW_TASK_DL2Mixer; + idx_patch = 1; + break; + default: + return 0; + } + patch = (on_off != 0) ? dbg_on : dbg_off; + /* address is on 16bits boundary */ + addr_patch = D_tasksList_ADDR + (16 * task_patch) + (2 * idx_patch); + /* read on 32bits words' boundary */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, addr_patch & (~0x03), + &task32, 4); + if (addr_patch & 0x03) + task32 = (0x0000FFFFL & task32) | (patch << 16); + else + task32 = (0xFFFF0000L & task32) | (0x0000FFFF & patch); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, addr_patch & (~0x03), + &task32, 4); + return 0; +} +EXPORT_SYMBOL(abe_enable_test_pattern); +/** + * abe_wakeup - Wakeup ABE + * + * Wakeup ABE in case of retention + */ +abehal_status abe_wakeup(void) +{ + /* Restart event generator */ + abe_write_event_generator(EVENT_TIMER); + /* reconfigure DMA Req and MCU Irq visibility */ + abe_hw_configuration(); + return 0; +} +EXPORT_SYMBOL(abe_wakeup); +/** + * abe_disable_irq - disable MCU/DSP ABE interrupt + * + * This subroutine is disabling ABE MCU/DSP Irq + */ +abehal_status abe_disable_irq(void) +{ + u32 atc_reg; + /* disables the DMAreq from AESS AESS_DMAENABLE_CLR = 127 + * DMA_Req7 will still be enabled as it is used for ABE trace */ + atc_reg = 0x7F; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x64, &atc_reg, 4); + /* disables the MCU IRQ from AESS to Cortex A9 */ + atc_reg = 0x01; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x40, &atc_reg, 4); + return 0; +} +EXPORT_SYMBOL(abe_disable_irq); +/** + * abe_check_activity - Check if some ABE activity. + * + * Check if any ABE ports are running. + * return 1: still activity on ABE + * return 0: no more activity on ABE. Event generator can be stopped + * + */ +u32 abe_check_activity(void) +{ + u32 i; + u32 ret; + ret = 0; + for (i = 0; i < (LAST_PORT_ID - 1); i++) { + if (abe_port[abe_port_priority[i]].status == + OMAP_ABE_PORT_ACTIVITY_RUNNING) + break; + } + if (i < (LAST_PORT_ID - 1)) + ret = 1; + return ret; +} +EXPORT_SYMBOL(abe_check_activity); +/** + * abe_init_mem - Allocate Kernel space memory map for ABE + * + * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM + */ +void abe_init_mem(void __iomem *_io_base) +{ + io_base = _io_base; +} +EXPORT_SYMBOL(abe_init_mem); diff --git a/sound/soc/omap/abe/abe_api.h b/sound/soc/omap/abe/abe_api.h new file mode 100644 index 00000000000..df3d34a29aa --- /dev/null +++ b/sound/soc/omap/abe/abe_api.h @@ -0,0 +1,516 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_API_H_ +#define _ABE_API_H_ +/** + * abe_reset_hal - reset the ABE/HAL + * @rdev: regulator source + * @constraints: constraints to apply + * + * Operations : reset the HAL by reloading the static variables and + * default AESS registers. + * Called after a PRCM cold-start reset of ABE + */ +abehal_status abe_reset_hal(void); +/** + * abe_load_fw_param - Load ABE Firmware memories + * @PMEM: Pointer of Program memory data + * @PMEM_SIZE: Size of PMEM data + * @CMEM: Pointer of Coeffients memory data + * @CMEM_SIZE: Size of CMEM data + * @SMEM: Pointer of Sample memory data + * @SMEM_SIZE: Size of SMEM data + * @DMEM: Pointer of Data memory data + * @DMEM_SIZE: Size of DMEM data + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw_param(u32 *FW); +/** + * abe_load_fw - Load ABE Firmware and initialize memories + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw(void); +/** + * abe_reload_fw - Reload ABE Firmware after OFF mode + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_reload_fw(void); +/** + * abe_read_hardware_configuration - Return default HW periferals configuration + * @u: use-case description list (pointer) + * @o: opp mode (pointer) + * @hw: pointer to the output HW structure + * + * Parameter : + * U : use-case description list (pointer) + * H : pointer to the output structure + * + * Operations : + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + * will be upgraded in FW06 + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + */ +abehal_status abe_read_hardware_configuration(u32 *u, u32 *o, + abe_hw_config_init_t *hw); +/** + * abe_irq_processing - Process ABE interrupt + * + * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio + * back-end interrupt. This subroutine will check the ATC Hrdware, the + * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated + * for the delivery of "end of time sequenced tasks" notifications, some are + * originated from the Ping-Pong protocols, some are generated from + * the embedded debugger when the firmware stops on programmable break-points, + * etc ... + */ +abehal_status abe_irq_processing(void); +/** + * abe_clear_irq - clear ABE interrupt + * + * This subroutine is call to clear MCU Irq + */ +abehal_status abe_clear_irq(void); +/** + * abe_disable_irq - disable MCU/DSP ABE interrupt + * + * This subroutine is disabling ABE MCU/DSP Irq + */ +abehal_status abe_disable_irq(void); +/* + * abe_check_activity - check all ports are closed + */ +u32 abe_check_activity(void); +/** + * abe_wakeup - Wakeup ABE + * + * Wakeup ABE in case of retention + */ +abehal_status abe_wakeup(void); +/** + * abe_stop_event_generator - Stop event generator source + * + * Stop the event genrator of AESS. No more event will be send to AESS engine. + * Upper layer needs to wait 1/96kHz to be sure that engine reach IDLE instruction + */ +abehal_status abe_stop_event_generator(void); +/** + * abe_select_main_port - Select stynchronization port for Event generator. + * @id: audio port name + * + * tells the FW which is the reference stream for adjusting + * the processing on 23/24/25 slots + */ +abehal_status abe_select_main_port(u32 id); +/** + * abe_write_event_generator - Select event generator source + * @e: Event Generation Counter, McPDM, DMIC or default. + * + * load the AESS event generator hardware source. Loads the firmware parameters + * accordingly. Indicates to the FW which data stream is the most important to preserve + * in case all the streams are asynchronous. If the parameter is "default", let the HAL + * decide which Event source is the best appropriate based on the opened ports. + * + * When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed + * with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher + * than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz + * The ratio is (MCLK/96000)+(1<<1) = 2050 + * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%) + */ +abehal_status abe_write_event_generator(u32 e); +/** + * abe_read_use_case_opp() - description for void abe_read_use_case_opp(). + * + * returns the expected min OPP for a given use_case list + */ +abehal_status abe_read_use_case_opp(u32 *u, u32 *o); +/** + * abe_set_opp_processing - Set OPP mode for ABE Firmware + * @opp: OOPP mode + * + * New processing network and OPP: + * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer) + * 1: OPP 25% (simple multimedia features, including low-power player) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (EANC, multimedia complex use-cases) + * + * Rearranges the FW task network to the corresponding OPP list of features. + * The corresponding AE ports are supposed to be set/reset accordingly before + * this switch. + * + */ +abehal_status abe_set_opp_processing(u32 opp); +/** + * abe_set_ping_pong_buffer + * @port: ABE port ID + * @n_bytes: Size of Ping/Pong buffer + * + * Updates the next ping-pong buffer with "size" bytes copied from the + * host processor. This API notifies the FW that the data transfer is done. + */ +abehal_status abe_set_ping_pong_buffer(u32 port, u32 n_bytes); +/** + * abe_read_next_ping_pong_buffer + * @port: ABE portID + * @p: Next buffer address (pointer) + * @n: Next buffer size (pointer) + * + * Tell the next base address of the next ping_pong Buffer and its size + */ +abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n); +/** + * abe_init_ping_pong_buffer + * @id: ABE port ID + * @size_bytes:size of the ping pong + * @n_buffers:number of buffers (2 = ping/pong) + * @p:returned address of the ping-pong list of base address (byte offset + from DMEM start) + * + * Computes the base address of the ping_pong buffers + */ +abehal_status abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers, + u32 *p); +/** + * abe_read_offset_from_ping_buffer + * @id: ABE port ID + * @n: returned address of the offset from the ping buffer start address expressed in samples + * + * Computes the current firmware ping pong read pointer location, expressed in samples, + * as the offset from the start address of ping buffer. + */ +abehal_status abe_read_offset_from_ping_buffer(u32 id, u32 *n); +/** + * abe_plug_subroutine + * @id: returned sequence index after plugging a new subroutine + * @f: subroutine address to be inserted + * @n: number of parameters of this subroutine + * @params: pointer on parameters + * + * register a list of subroutines for call-back purpose + */ +abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n, + u32 *params); +/** + * abe_set_sequence_time_accuracy + * @fast: fast counter + * @slow: slow counter + * + */ +abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow); +/** + * abe_reset_port + * @id: ABE port ID + * + * stop the port activity and reload default parameters on the associated + * processing features. + * Clears the internal AE buffers. + */ +abehal_status abe_reset_port(u32 id); +/** + * abe_read_remaining_data + * @id: ABE port_ID + * @n: size pointer to the remaining number of 32bits words + * + * computes the remaining amount of data in the buffer. + */ +abehal_status abe_read_remaining_data(u32 port, u32 *n); +/** + * abe_disable_data_transfer + * @id: ABE port id + * + * disables the ATC descriptor and stop IO/port activities + * disable the IO task (@f = 0) + * clear ATC DMEM buffer, ATC enabled + */ +abehal_status abe_disable_data_transfer(u32 id); +/** + * abe_enable_data_transfer + * @ip: ABE port id + * + * enables the ATC descriptor + * reset ATC pointers + * enable the IO task (@f <> 0) + */ +abehal_status abe_enable_data_transfer(u32 id); +/** + * abe_set_dmic_filter + * @d: DMIC decimation ratio : 16/25/32/40 + * + * Loads in CMEM a specific list of coefficients depending on the DMIC sampling + * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator + * roll-off at 20kHz. + * The default table is loaded with the DMIC 2.4MHz recommended configuration. + */ +abehal_status abe_set_dmic_filter(u32 d); +/** + * abe_connect_cbpr_dmareq_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @a: returned pointer to the base address of the CBPr register and number of + * samples to exchange during a DMA_request. + * + * enables the data echange between a DMA and the ABE through the + * CBPr registers of AESS. + */ +abehal_status abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d, + abe_dma_t *returned_dma_t); +/** + * abe_connect_dmareq_ping_pong_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @s: half-buffer (ping) size + * @a: returned pointer to the base address of the ping-pong buffer and number + * of samples to exchange during a DMA_request. + * + * enables the data echanges between a DMA and a direct access to + * the DMEM memory of ABE. On each dma_request activation the DMA will exchange + * "s" bytes and switch to the "pong" buffer for a new buffer exchange. + */ +abehal_status abe_connect_dmareq_ping_pong_port(u32 id, abe_data_format_t *f, + u32 d, u32 s, + abe_dma_t *returned_dma_t); +/** + * abe_connect_irq_ping_pong_port + * @id: port name + * @f: desired data format + * @I: index of the call-back subroutine to call + * @s: half-buffer (ping) size + * @p: returned base address of the first (ping) buffer) + * + * enables the data echanges between a direct access to the DMEM + * memory of ABE using cache flush. On each IRQ activation a subroutine + * registered with "abe_plug_subroutine" will be called. This subroutine + * will generate an amount of samples, send them to DMEM memory and call + * "abe_set_ping_pong_buffer" to notify the new amount of samples in the + * pong buffer. + */ +abehal_status abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f, + u32 subroutine_id, u32 size, + u32 *sink, u32 dsp_mcu_flag); +/** + * abe_connect_serial_port() + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * + * Operations : enables the data echanges between a McBSP and an ATC buffer in + * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz + * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the + * abe_write_port API. + */ +abehal_status abe_connect_serial_port(u32 id, abe_data_format_t *f, + u32 mcbsp_id); +/** + * abe_connect_slimbus_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between 1/2 SB and an ATC buffers in + * DMEM. + */ +abehal_status abe_connect_slimbus_port(u32 id, abe_data_format_t *f, + u32 sb_port1, u32 sb_port2); +/** + * abe_connect_tdm_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between TDM McBSP ATC buffers in + * DMEM and 1/2 SMEM buffers + */ +abehal_status abe_connect_tdm_port(u32 id, abe_data_format_t *f, u32 mcbsp_id); +/** + * abe_read_port_address + * @dma: output pointer to the DMA iteration and data destination pointer + * + * This API returns the address of the DMA register used on this audio port. + * Depending on the protocol being used, adds the base address offset L3 + * (DMA) or MPU (ARM) + */ +abehal_status abe_read_port_address(u32 port, abe_dma_t *dma2); +/** + * abe_write_equalizer + * @id: name of the equalizer + * @param : equalizer coefficients + * + * Load the coefficients in CMEM. + */ +abehal_status abe_write_equalizer(u32 id, abe_equ_t *param); +/** + * abe_write_asrc + * @id: name of the port + * @param: drift value to compensate [ppm] + * + * Load the drift variables to the FW memory. This API can be called only + * when the corresponding port has been already opened and the ASRC has + * been correctly initialized with API abe_init_asrc_... If this API is + * used such that the drift has been changed from positive to negative drift + * or vice versa, there will be click in the output signal. Loading the drift + * value with zero disables the feature. + */ +abehal_status abe_write_asrc(u32 port, s32 dppm); +/** + * abe_write_aps + * @id: name of the aps filter + * @param: table of filter coefficients + * + * Load the filters and thresholds coefficients in FW memory. This AP + * can be called when the corresponding APS is not activated. After + * reloading the firmware the default coefficients corresponds to "no APS + * activated". + * Loading all the coefficients value with zero disables the feature. + */ +abehal_status abe_write_aps(u32 id, abe_aps_t *param); +/** + * abe_write_mixer + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's gain + * in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p); +abehal_status abe_use_compensated_gain(u32 on_off); +abehal_status abe_enable_gain(u32 id, u32 p); +abehal_status abe_disable_gain(u32 id, u32 p); +abehal_status abe_mute_gain(u32 id, u32 p); +abehal_status abe_unmute_gain(u32 id, u32 p); +/** + * abe_write_mixer + * @id: name of the mixer + * @param: input gains and delay ramp of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p); +/** + * abe_read_gain + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + */ +abehal_status abe_read_gain(u32 id, u32 *f_g, u32 p); +/** + * abe_read_mixer + * @id: name of the mixer + * @param: gains of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_read_mixer(u32 id, u32 *f_g, u32 p); +/** + * abe_set_router_configuration + * @Id: name of the router + * @Conf: id of the configuration + * @param: list of output index of the route + * + * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) + * and PORT1/2 (2 stereo ports). Each sample will be individually stored in + * an intermediate table of 10 elements. The intermediate table is used to + * route the samples to three directions : REC1 mixer, 2 EANC DMIC source of + * filtering and MM recording audio path. + */ +abehal_status abe_set_router_configuration(u32 id, u32 k, u32 *param); +/** + * abe_select_data_source + * @@@ + */ +abehal_status abe_select_data_source(u32 port_id, u32 smem_source); +/** + * ABE_READ_DEBUG_TRACE + * + * Parameter : + * data destination pointer + * max number of data read + * + * Operations : + * reads the AE circular data pointer holding pairs of debug data+ + * timestamps, and store the pairs in linear addressing to the parameter + * pointer. Stops the copy when the max parameter is reached or when the + * FIFO is empty. + * + * Return value : + * None. + */ +abehal_status abe_read_debug_trace(u32 *data, u32 *n); +/** + * abe_connect_debug_trace + * @dma2:pointer to the DMEM trace buffer + * + * returns the address and size of the real-time debug trace buffer, + * the content of which will vary from one firmware release to an other + */ +abehal_status abe_connect_debug_trace(abe_dma_t *dma2); +/** + * abe_set_debug_trace + * @debug: debug ID from a list to be defined + * + * load a mask which filters the debug trace to dedicated types of data + */ +abehal_status abe_set_debug_trace(abe_dbg_t debug); +/** + * abe_remote_debugger_interface + * + * interpretation of the UART stream from the remote debugger commands. + * The commands consist in setting break points, loading parameter + */ +abehal_status abe_remote_debugger_interface(u32 n, u8 *p); +/** + * abe_enable_test_pattern + * + */ +abehal_status abe_enable_test_pattern(u32 smem_id, u32 on_off); +/** + * abe_init_mem - Allocate Kernel space memory map for ABE + * + * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM + */ +void abe_init_mem(void __iomem *_io_base); +#endif/* _ABE_API_H_ */ diff --git a/sound/soc/omap/abe/abe_cm_addr.h b/sound/soc/omap/abe/abe_cm_addr.h new file mode 100644 index 00000000000..070c961c6ed --- /dev/null +++ b/sound/soc/omap/abe/abe_cm_addr.h @@ -0,0 +1,284 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_CM_ADDR_H_ +#define _ABE_CM_ADDR_H_ +#define init_CM_ADDR 0 +#define init_CM_ADDR_END 309 +#define init_CM_sizeof 310 +#define C_Data_LSB_2_ADDR 310 +#define C_Data_LSB_2_ADDR_END 310 +#define C_Data_LSB_2_sizeof 1 +#define C_1_Alpha_ADDR 311 +#define C_1_Alpha_ADDR_END 328 +#define C_1_Alpha_sizeof 18 +#define C_Alpha_ADDR 329 +#define C_Alpha_ADDR_END 346 +#define C_Alpha_sizeof 18 +#define C_GainsWRamp_ADDR 347 +#define C_GainsWRamp_ADDR_END 360 +#define C_GainsWRamp_sizeof 14 +#define C_Gains_DL1M_ADDR 361 +#define C_Gains_DL1M_ADDR_END 364 +#define C_Gains_DL1M_sizeof 4 +#define C_Gains_DL2M_ADDR 365 +#define C_Gains_DL2M_ADDR_END 368 +#define C_Gains_DL2M_sizeof 4 +#define C_Gains_EchoM_ADDR 369 +#define C_Gains_EchoM_ADDR_END 370 +#define C_Gains_EchoM_sizeof 2 +#define C_Gains_SDTM_ADDR 371 +#define C_Gains_SDTM_ADDR_END 372 +#define C_Gains_SDTM_sizeof 2 +#define C_Gains_VxRecM_ADDR 373 +#define C_Gains_VxRecM_ADDR_END 376 +#define C_Gains_VxRecM_sizeof 4 +#define C_Gains_ULM_ADDR 377 +#define C_Gains_ULM_ADDR_END 380 +#define C_Gains_ULM_sizeof 4 +#define C_Gains_unused_ADDR 381 +#define C_Gains_unused_ADDR_END 382 +#define C_Gains_unused_sizeof 2 +#define C_SDT_Coefs_ADDR 383 +#define C_SDT_Coefs_ADDR_END 391 +#define C_SDT_Coefs_sizeof 9 +#define C_CoefASRC1_VX_ADDR 392 +#define C_CoefASRC1_VX_ADDR_END 410 +#define C_CoefASRC1_VX_sizeof 19 +#define C_CoefASRC2_VX_ADDR 411 +#define C_CoefASRC2_VX_ADDR_END 429 +#define C_CoefASRC2_VX_sizeof 19 +#define C_CoefASRC3_VX_ADDR 430 +#define C_CoefASRC3_VX_ADDR_END 448 +#define C_CoefASRC3_VX_sizeof 19 +#define C_CoefASRC4_VX_ADDR 449 +#define C_CoefASRC4_VX_ADDR_END 467 +#define C_CoefASRC4_VX_sizeof 19 +#define C_CoefASRC5_VX_ADDR 468 +#define C_CoefASRC5_VX_ADDR_END 486 +#define C_CoefASRC5_VX_sizeof 19 +#define C_CoefASRC6_VX_ADDR 487 +#define C_CoefASRC6_VX_ADDR_END 505 +#define C_CoefASRC6_VX_sizeof 19 +#define C_CoefASRC7_VX_ADDR 506 +#define C_CoefASRC7_VX_ADDR_END 524 +#define C_CoefASRC7_VX_sizeof 19 +#define C_CoefASRC8_VX_ADDR 525 +#define C_CoefASRC8_VX_ADDR_END 543 +#define C_CoefASRC8_VX_sizeof 19 +#define C_CoefASRC9_VX_ADDR 544 +#define C_CoefASRC9_VX_ADDR_END 562 +#define C_CoefASRC9_VX_sizeof 19 +#define C_CoefASRC10_VX_ADDR 563 +#define C_CoefASRC10_VX_ADDR_END 581 +#define C_CoefASRC10_VX_sizeof 19 +#define C_CoefASRC11_VX_ADDR 582 +#define C_CoefASRC11_VX_ADDR_END 600 +#define C_CoefASRC11_VX_sizeof 19 +#define C_CoefASRC12_VX_ADDR 601 +#define C_CoefASRC12_VX_ADDR_END 619 +#define C_CoefASRC12_VX_sizeof 19 +#define C_CoefASRC13_VX_ADDR 620 +#define C_CoefASRC13_VX_ADDR_END 638 +#define C_CoefASRC13_VX_sizeof 19 +#define C_CoefASRC14_VX_ADDR 639 +#define C_CoefASRC14_VX_ADDR_END 657 +#define C_CoefASRC14_VX_sizeof 19 +#define C_CoefASRC15_VX_ADDR 658 +#define C_CoefASRC15_VX_ADDR_END 676 +#define C_CoefASRC15_VX_sizeof 19 +#define C_CoefASRC16_VX_ADDR 677 +#define C_CoefASRC16_VX_ADDR_END 695 +#define C_CoefASRC16_VX_sizeof 19 +#define C_AlphaCurrent_UL_VX_ADDR 696 +#define C_AlphaCurrent_UL_VX_ADDR_END 696 +#define C_AlphaCurrent_UL_VX_sizeof 1 +#define C_BetaCurrent_UL_VX_ADDR 697 +#define C_BetaCurrent_UL_VX_ADDR_END 697 +#define C_BetaCurrent_UL_VX_sizeof 1 +#define C_AlphaCurrent_DL_VX_ADDR 698 +#define C_AlphaCurrent_DL_VX_ADDR_END 698 +#define C_AlphaCurrent_DL_VX_sizeof 1 +#define C_BetaCurrent_DL_VX_ADDR 699 +#define C_BetaCurrent_DL_VX_ADDR_END 699 +#define C_BetaCurrent_DL_VX_sizeof 1 +#define C_CoefASRC1_MM_ADDR 700 +#define C_CoefASRC1_MM_ADDR_END 717 +#define C_CoefASRC1_MM_sizeof 18 +#define C_CoefASRC2_MM_ADDR 718 +#define C_CoefASRC2_MM_ADDR_END 735 +#define C_CoefASRC2_MM_sizeof 18 +#define C_CoefASRC3_MM_ADDR 736 +#define C_CoefASRC3_MM_ADDR_END 753 +#define C_CoefASRC3_MM_sizeof 18 +#define C_CoefASRC4_MM_ADDR 754 +#define C_CoefASRC4_MM_ADDR_END 771 +#define C_CoefASRC4_MM_sizeof 18 +#define C_CoefASRC5_MM_ADDR 772 +#define C_CoefASRC5_MM_ADDR_END 789 +#define C_CoefASRC5_MM_sizeof 18 +#define C_CoefASRC6_MM_ADDR 790 +#define C_CoefASRC6_MM_ADDR_END 807 +#define C_CoefASRC6_MM_sizeof 18 +#define C_CoefASRC7_MM_ADDR 808 +#define C_CoefASRC7_MM_ADDR_END 825 +#define C_CoefASRC7_MM_sizeof 18 +#define C_CoefASRC8_MM_ADDR 826 +#define C_CoefASRC8_MM_ADDR_END 843 +#define C_CoefASRC8_MM_sizeof 18 +#define C_CoefASRC9_MM_ADDR 844 +#define C_CoefASRC9_MM_ADDR_END 861 +#define C_CoefASRC9_MM_sizeof 18 +#define C_CoefASRC10_MM_ADDR 862 +#define C_CoefASRC10_MM_ADDR_END 879 +#define C_CoefASRC10_MM_sizeof 18 +#define C_CoefASRC11_MM_ADDR 880 +#define C_CoefASRC11_MM_ADDR_END 897 +#define C_CoefASRC11_MM_sizeof 18 +#define C_CoefASRC12_MM_ADDR 898 +#define C_CoefASRC12_MM_ADDR_END 915 +#define C_CoefASRC12_MM_sizeof 18 +#define C_CoefASRC13_MM_ADDR 916 +#define C_CoefASRC13_MM_ADDR_END 933 +#define C_CoefASRC13_MM_sizeof 18 +#define C_CoefASRC14_MM_ADDR 934 +#define C_CoefASRC14_MM_ADDR_END 951 +#define C_CoefASRC14_MM_sizeof 18 +#define C_CoefASRC15_MM_ADDR 952 +#define C_CoefASRC15_MM_ADDR_END 969 +#define C_CoefASRC15_MM_sizeof 18 +#define C_CoefASRC16_MM_ADDR 970 +#define C_CoefASRC16_MM_ADDR_END 987 +#define C_CoefASRC16_MM_sizeof 18 +#define C_AlphaCurrent_MM_EXT_IN_ADDR 988 +#define C_AlphaCurrent_MM_EXT_IN_ADDR_END 988 +#define C_AlphaCurrent_MM_EXT_IN_sizeof 1 +#define C_BetaCurrent_MM_EXT_IN_ADDR 989 +#define C_BetaCurrent_MM_EXT_IN_ADDR_END 989 +#define C_BetaCurrent_MM_EXT_IN_sizeof 1 +#define C_DL2_L_Coefs_ADDR 990 +#define C_DL2_L_Coefs_ADDR_END 1014 +#define C_DL2_L_Coefs_sizeof 25 +#define C_DL2_R_Coefs_ADDR 1015 +#define C_DL2_R_Coefs_ADDR_END 1039 +#define C_DL2_R_Coefs_sizeof 25 +#define C_DL1_Coefs_ADDR 1040 +#define C_DL1_Coefs_ADDR_END 1064 +#define C_DL1_Coefs_sizeof 25 +#define C_SRC_3_LP_Coefs_ADDR 1065 +#define C_SRC_3_LP_Coefs_ADDR_END 1075 +#define C_SRC_3_LP_Coefs_sizeof 11 +#define C_SRC_3_LP_GAIN_Coefs_ADDR 1076 +#define C_SRC_3_LP_GAIN_Coefs_ADDR_END 1086 +#define C_SRC_3_LP_GAIN_Coefs_sizeof 11 +#define C_SRC_3_HP_Coefs_ADDR 1087 +#define C_SRC_3_HP_Coefs_ADDR_END 1091 +#define C_SRC_3_HP_Coefs_sizeof 5 +#define C_SRC_6_LP_Coefs_ADDR 1092 +#define C_SRC_6_LP_Coefs_ADDR_END 1102 +#define C_SRC_6_LP_Coefs_sizeof 11 +#define C_SRC_6_LP_GAIN_Coefs_ADDR 1103 +#define C_SRC_6_LP_GAIN_Coefs_ADDR_END 1113 +#define C_SRC_6_LP_GAIN_Coefs_sizeof 11 +#define C_SRC_6_HP_Coefs_ADDR 1114 +#define C_SRC_6_HP_Coefs_ADDR_END 1120 +#define C_SRC_6_HP_Coefs_sizeof 7 +#define C_APS_DL1_coeffs1_ADDR 1121 +#define C_APS_DL1_coeffs1_ADDR_END 1129 +#define C_APS_DL1_coeffs1_sizeof 9 +#define C_APS_DL1_M_coeffs2_ADDR 1130 +#define C_APS_DL1_M_coeffs2_ADDR_END 1132 +#define C_APS_DL1_M_coeffs2_sizeof 3 +#define C_APS_DL1_C_coeffs2_ADDR 1133 +#define C_APS_DL1_C_coeffs2_ADDR_END 1135 +#define C_APS_DL1_C_coeffs2_sizeof 3 +#define C_APS_DL2_L_coeffs1_ADDR 1136 +#define C_APS_DL2_L_coeffs1_ADDR_END 1144 +#define C_APS_DL2_L_coeffs1_sizeof 9 +#define C_APS_DL2_R_coeffs1_ADDR 1145 +#define C_APS_DL2_R_coeffs1_ADDR_END 1153 +#define C_APS_DL2_R_coeffs1_sizeof 9 +#define C_APS_DL2_L_M_coeffs2_ADDR 1154 +#define C_APS_DL2_L_M_coeffs2_ADDR_END 1156 +#define C_APS_DL2_L_M_coeffs2_sizeof 3 +#define C_APS_DL2_R_M_coeffs2_ADDR 1157 +#define C_APS_DL2_R_M_coeffs2_ADDR_END 1159 +#define C_APS_DL2_R_M_coeffs2_sizeof 3 +#define C_APS_DL2_L_C_coeffs2_ADDR 1160 +#define C_APS_DL2_L_C_coeffs2_ADDR_END 1162 +#define C_APS_DL2_L_C_coeffs2_sizeof 3 +#define C_APS_DL2_R_C_coeffs2_ADDR 1163 +#define C_APS_DL2_R_C_coeffs2_ADDR_END 1165 +#define C_APS_DL2_R_C_coeffs2_sizeof 3 +#define C_AlphaCurrent_ECHO_REF_ADDR 1166 +#define C_AlphaCurrent_ECHO_REF_ADDR_END 1166 +#define C_AlphaCurrent_ECHO_REF_sizeof 1 +#define C_BetaCurrent_ECHO_REF_ADDR 1167 +#define C_BetaCurrent_ECHO_REF_ADDR_END 1167 +#define C_BetaCurrent_ECHO_REF_sizeof 1 +#define C_APS_DL1_EQ_ADDR 1168 +#define C_APS_DL1_EQ_ADDR_END 1176 +#define C_APS_DL1_EQ_sizeof 9 +#define C_APS_DL2_L_EQ_ADDR 1177 +#define C_APS_DL2_L_EQ_ADDR_END 1185 +#define C_APS_DL2_L_EQ_sizeof 9 +#define C_APS_DL2_R_EQ_ADDR 1186 +#define C_APS_DL2_R_EQ_ADDR_END 1194 +#define C_APS_DL2_R_EQ_sizeof 9 +#define C_Vibra2_consts_ADDR 1195 +#define C_Vibra2_consts_ADDR_END 1198 +#define C_Vibra2_consts_sizeof 4 +#define C_Vibra1_coeffs_ADDR 1199 +#define C_Vibra1_coeffs_ADDR_END 1209 +#define C_Vibra1_coeffs_sizeof 11 +#define C_48_96_LP_Coefs_ADDR 1210 +#define C_48_96_LP_Coefs_ADDR_END 1224 +#define C_48_96_LP_Coefs_sizeof 15 +#define C_96_48_AMIC_Coefs_ADDR 1225 +#define C_96_48_AMIC_Coefs_ADDR_END 1243 +#define C_96_48_AMIC_Coefs_sizeof 19 +#define C_96_48_DMIC_Coefs_ADDR 1244 +#define C_96_48_DMIC_Coefs_ADDR_END 1262 +#define C_96_48_DMIC_Coefs_sizeof 19 +#define C_INPUT_SCALE_ADDR 1263 +#define C_INPUT_SCALE_ADDR_END 1263 +#define C_INPUT_SCALE_sizeof 1 +#define C_OUTPUT_SCALE_ADDR 1264 +#define C_OUTPUT_SCALE_ADDR_END 1264 +#define C_OUTPUT_SCALE_sizeof 1 +#define C_MUTE_SCALING_ADDR 1265 +#define C_MUTE_SCALING_ADDR_END 1265 +#define C_MUTE_SCALING_sizeof 1 +#define C_GAINS_0DB_ADDR 1266 +#define C_GAINS_0DB_ADDR_END 1267 +#define C_GAINS_0DB_sizeof 2 +#define C_AlphaCurrent_BT_UL_ADDR 1268 +#define C_AlphaCurrent_BT_UL_ADDR_END 1268 +#define C_AlphaCurrent_BT_UL_sizeof 1 +#define C_BetaCurrent_BT_UL_ADDR 1269 +#define C_BetaCurrent_BT_UL_ADDR_END 1269 +#define C_BetaCurrent_BT_UL_sizeof 1 +#define C_AlphaCurrent_BT_DL_ADDR 1270 +#define C_AlphaCurrent_BT_DL_ADDR_END 1270 +#define C_AlphaCurrent_BT_DL_sizeof 1 +#define C_BetaCurrent_BT_DL_ADDR 1271 +#define C_BetaCurrent_BT_DL_ADDR_END 1271 +#define C_BetaCurrent_BT_DL_sizeof 1 +#endif/* _ABECM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_dat.c b/sound/soc/omap/abe/abe_dat.c new file mode 100644 index 00000000000..82129921fcd --- /dev/null +++ b/sound/soc/omap/abe/abe_dat.c @@ -0,0 +1,862 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include <linux/module.h> +#include "abe_main.h" +#ifndef abe_dat_c +#define abe_dat_c +const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE] = { +#include "abe_firmware.c" +}; +u32 abe_firmware_version_number; +/* + * Kernel base + */ +void __iomem *io_base; +/* + * global variable : saves stack area + */ +u16 MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT]; +ABE_SIODescriptor sio_desc; +ABE_SPingPongDescriptor desc_pp; +abe_satcdescriptor_aess atc_desc; +/* + * automatic gain control of input mixer's gains + */ +u32 abe_compensated_mixer_gain; +u8 abe_muted_gains_indicator[MAX_NBGAIN_CMEM]; +u32 abe_desired_gains_decibel[MAX_NBGAIN_CMEM]; +u32 abe_muted_gains_decibel[MAX_NBGAIN_CMEM]; +u32 abe_desired_gains_linear[MAX_NBGAIN_CMEM]; +u32 abe_desired_ramp_delay_ms[MAX_NBGAIN_CMEM]; +/* + * HAL/FW ports status / format / sampling / protocol(call_back) / features + * / gain / name + */ +u32 pdm_dl1_status; +u32 pdm_dl2_status; +u32 pdm_vib_status; +/* + * HAL/FW ports status / format / sampling / protocol(call_back) / features + * / gain / name + */ +abe_port_t abe_port[LAST_PORT_ID]; /* list of ABE ports */ +const abe_port_t abe_port_init[LAST_PORT_ID] = { + /* Status Data Format Drift Call-Back Protocol+selector desc_addr; + buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features + reseted at start Port Name for the debug trace */ + /* DMIC */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB}, + NODRIFT, NOCALLBACK, 0, (DMIC_ITER / 6), + { + SNK_P, DMIC_PORT_PROT, + {{dmem_dmic, dmem_dmic_size, DMIC_ITER} } + }, + {0, 0}, + {EQDMIC, 0}, "DMIC"}, + /* PDM_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_amic, (MCPDM_UL_ITER / 2), + { + SNK_P, MCPDMUL_PORT_PROT, + {{dmem_amic, dmem_amic_size, MCPDM_UL_ITER} } + }, + {0, 0}, + {EQAMIC, 0}, "PDM_UL"}, + /* BT_VX_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_bt_vx_ul_opp50, 1, + { + SNK_P, SERIAL_PORT_PROT, {{ + (MCBSP1_DMA_TX*ATC_SIZE), + dmem_bt_vx_ul, + dmem_bt_vx_ul_size, + (1*SCHED_LOOP_8kHz) + } } + }, + {0, 0}, {0}, "BT_VX_UL"}, + /* MM_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ul, 1, + { + SRC_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX3*ATC_SIZE), + dmem_mm_ul, dmem_mm_ul_size, + (10*SCHED_LOOP_48kHz), + ABE_DMASTATUS_RAW, (1 << 3) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120}, + {UPROUTE, 0}, "MM_UL"}, + /* MM_UL2 */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ul2, 1, + { + SRC_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX4*ATC_SIZE), + dmem_mm_ul2, dmem_mm_ul2_size, + (2*SCHED_LOOP_48kHz), + ABE_DMASTATUS_RAW, (1 << 4) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24}, + {UPROUTE, 0}, "MM_UL2"}, + /* VX_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_vx_ul, 1, + { + SRC_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX2*ATC_SIZE), + dmem_vx_ul, dmem_vx_ul_size, + (1*SCHED_LOOP_8kHz), + ABE_DMASTATUS_RAW, (1 << 2) + } } + }, { + CIRCULAR_BUFFER_PERIPHERAL_R__2, 2}, + {ASRC2, 0}, "VX_UL"}, + /* MM_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_dl, 1, + { + SNK_P, PINGPONG_PORT_PROT, {{ + (CBPr_DMA_RTX0*ATC_SIZE), + dmem_mm_dl, dmem_mm_dl_size, + (2*SCHED_LOOP_48kHz), + ABE_DMASTATUS_RAW, (1 << 0) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24}, + {ASRC3, 0}, "MM_DL"}, + /* VX_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_vx_dl, 1, + { + SNK_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX1*ATC_SIZE), + dmem_vx_dl, dmem_vx_dl_size, + (1*SCHED_LOOP_8kHz), + ABE_DMASTATUS_RAW, (1 << 1) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2}, + {ASRC1, 0}, "VX_DL"}, + /* TONES_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_tones_dl, 1, + { + SNK_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX5*ATC_SIZE), + dmem_tones_dl, + dmem_tones_dl_size, + (2*SCHED_LOOP_48kHz), + ABE_DMASTATUS_RAW, (1 << 5) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24}, + {0}, "TONES_DL"}, + /* VIB_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {24000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_vib, 1, + { + SNK_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX6*ATC_SIZE), + dmem_vib_dl, dmem_vib_dl_size, + (2*SCHED_LOOP_24kHz), + ABE_DMASTATUS_RAW, (1 << 6) + } } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12}, + {0}, "VIB_DL"}, + /* BT_VX_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_bt_vx_dl_opp50, 1, + { + SRC_P, SERIAL_PORT_PROT, {{ + (MCBSP1_DMA_RX*ATC_SIZE), + dmem_bt_vx_dl, + dmem_bt_vx_dl_size, + (1*SCHED_LOOP_8kHz), + } } + }, + {0, 0}, {0}, "BT_VX_DL"}, + /* PDM_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB}, + NODRIFT, NOCALLBACK, 0, (MCPDM_DL_ITER / 6), + {SRC_P, MCPDMDL_PORT_PROT, + {{dmem_mcpdm, dmem_mcpdm_size} } }, + {0, 0}, + {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R, 0}, + "PDM_DL"}, + /* MM_EXT_OUT */ + { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ext_out, 1, + { + SRC_P, SERIAL_PORT_PROT, {{ + (MCBSP1_DMA_TX*ATC_SIZE), + dmem_mm_ext_out, dmem_mm_ext_out_size, + (2*SCHED_LOOP_48kHz) + } } + }, {0, 0}, {0}, "MM_EXT_OUT"}, + /* MM_EXT_IN */ + { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ext_in_opp100, 1, + { + SNK_P, SERIAL_PORT_PROT, {{ + (MCBSP1_DMA_RX*ATC_SIZE), + dmem_mm_ext_in, dmem_mm_ext_in_size, + (2*SCHED_LOOP_48kHz) + } } + }, + {0, 0}, {0}, "MM_EXT_IN"}, + /* PCM3_TX */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, 0, 1, + { + SRC_P, TDM_SERIAL_PORT_PROT, {{ + (MCBSP3_DMA_TX * + ATC_SIZE), + dmem_mm_ext_out, + dmem_mm_ext_out_size, + (2*SCHED_LOOP_48kHz) + } } + }, + {0, 0}, {0}, "TDM_OUT"}, + /* PCM3_RX */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, 0, 1, + { + SRC_P, TDM_SERIAL_PORT_PROT, {{ + (MCBSP3_DMA_RX * + ATC_SIZE), + dmem_mm_ext_in, + dmem_mm_ext_in_size, + (2*SCHED_LOOP_48kHz) + } } + }, + {0, 0}, {0}, "TDM_IN"}, + /* SCHD_DBG_PORT */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, MONO_MSB}, + NODRIFT, NOCALLBACK, 0, 1, + { + SRC_P, DMAREQ_PORT_PROT, {{ + (CBPr_DMA_RTX7 * + ATC_SIZE), + dmem_mm_trace, + dmem_mm_trace_size, + (2*SCHED_LOOP_48kHz), + ABE_DMASTATUS_RAW, + (1 << 4) + } } + }, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24}, + {FEAT_SEQ, FEAT_CTL, FEAT_GAINS, 0}, "SCHD_DBG"}, +}; +/* abe_port_init : smem content for DMIC/PDM must be 0 or Dummy_AM_labelID */ +/* + * Firmware features + */ +abe_feature_t all_feature[MAXNBFEATURE]; +const abe_feature_t all_feature_init[] = { + /* ON_reset OFF READ WRITE STATUS INPUT OUTPUT SLOT/S OPP NAME */ + /* equalizer downlink path headset + earphone */ + /* EQ1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1, + c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ1"}, + /* equalizer downlink path integrated handsfree LEFT */ + /* EQ2L */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2, + c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ2L"}, + /* equalizer downlink path integrated handsfree RIGHT */ + /* EQ2R */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ2R"}, + /* equalizer downlink path side-tone */ + /* EQSDT */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQSDT"}, + /* SRC+equalizer uplink DMIC 1st pair */ + /* EQDMIC1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC1"}, + /* SRC+equalizer uplink DMIC 2nd pair */ + /* EQDMIC2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC2"}, + /* SRC+equalizer uplink DMIC 3rd pair */ + /* EQDMIC3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC3"}, + /* SRC+equalizer uplink AMIC */ + /* EQAMIC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQAMIC"}, + /* Acoustic protection for headset */ + /* APS1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " APS1"}, + /* acoustic protection high-pass filter for handsfree "Left" */ + /* APS2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " APS2"}, + /* acoustic protection high-pass filter for handsfree "Right" */ + /* APS3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " APS3"}, + /* asynchronous sample-rate-converter for the downlink voice path */ + /* ASRC1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXDL"}, + /* asynchronous sample-rate-converter for the uplink voice path */ + /* ASRC2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXUL"}, + /* asynchronous sample-rate-converter for the multimedia player */ + /* ASRC3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " ASRC_MMDL"}, + /* asynchronous sample-rate-converter for the echo reference */ + /* ASRC4 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_ECHO"}, + /* mixer of the headset and earphone path */ + /* MXDL1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " MIX_DL1"}, + /* mixer of the hands-free path */ + /* MXDL2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " MIX_DL2"}, + /* mixer for uplink tone mixer */ + /* MXAUDUL */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXSAUDUL"}, + /* mixer for voice recording */ + /* MXVXREC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXVXREC"}, + /* mixer for side-tone */ + /* MXSDT */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_SDT"}, + /* mixer for echo reference */ + /* MXECHO */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_ECHO"}, + /* router of the uplink path */ + /* UPROUTE */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " DLEQ3"}, + /* all gains */ + /* GAINS */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"}, + /* active noise canceller */ + /* EANC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ3"}, + /* sequencing queue of micro tasks */ + /* SEQ */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"}, + /* Phoenix control queue through McPDM */ + /* CTL */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"}, +}; +/* + * MEMORY MAPPING OF THE DMEM FIFOs + */ +/* DMEM port map */ +u32 abe_map_dmem[LAST_PORT_ID]; +u32 abe_map_dmem_secondary[LAST_PORT_ID]; +/* DMEM port buffer sizes */ +u32 abe_map_dmem_size[LAST_PORT_ID]; +/* + * AESS/ATC destination and source address translation (except McASPs) + * from the original 64bits words address + */ +const u32 abe_atc_dstid[ABE_ATC_DESC_SIZE >> 3] = { + /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */ + 0, 0, 12, 0, 1, 0, 2, 0, + /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */ + 3, 0, 4, 5, 6, 7, 8, 9, + /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */ + 10, 11, 0, 0, 0, 0, 0, 0, + /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */ + 0, 0, 14, 0, 0, 0, 0, 0, + /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */ + 63, 63, 63, 63, 63, 63, 63, 63, + /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 + CBP_T15 48 .. 63 */ + 0, 0, 0, 0, 0, 0, 0, 0, +}; +const u32 abe_atc_srcid[ABE_ATC_DESC_SIZE >> 3] = { + /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */ + 0, 12, 0, 13, 0, 1, 0, 2, + /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */ + 0, 3, 0, 0, 0, 0, 0, 0, + /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */ + 0, 0, 4, 5, 6, 7, 8, 9, + /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */ + 10, 11, 0, 0, 0, 14, 0, 0, + /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */ + 63, 63, 63, 63, 63, 63, 63, 63, + /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 + CBP_T15 48 .. 63 */ + 0, 0, 0, 0, 0, 0, 0, 0, +}; +/* + * preset default routing configurations + * This is given as implementation EXAMPLES + * the programmer uses "abe_set_router_configuration" with its own tables + */ +const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL] = { + /* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */ + { + /* 0 .. 9 = MM_UL */ + DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, AMIC_L_labelID, + AMIC_L_labelID, + ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + AMIC_L_labelID, AMIC_L_labelID, + /* 12 .. 13 = VX_UL */ + AMIC_L_labelID, AMIC_R_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + /* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1 */ + { + /* 0 .. 9 = MM_UL */ + DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID, + DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + DMIC1_L_labelID, DMIC1_R_labelID, + /* 12 .. 13 = VX_UL */ + DMIC1_L_labelID, DMIC1_R_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + /* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */ + { + /* 0 .. 9 = MM_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, + DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + DMIC2_L_labelID, DMIC2_R_labelID, + /* 12 .. 13 = VX_UL */ + DMIC2_L_labelID, DMIC2_R_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */ + { + /* 0 .. 9 = MM_UL */ + AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + DMIC3_L_labelID, DMIC3_R_labelID, + /* 12 .. 13 = VX_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */ + { + /* 0 .. 9 = MM_UL */ + BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, + ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + AMIC_L_labelID, AMIC_R_labelID, + /* 12 .. 13 = VX_UL */ + BT_UL_L_labelID, BT_UL_R_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + /* VOICE UPLINK WITH THE BT - UPROUTE_ECHO_MMUL2 */ + { + /* 0 .. 9 = MM_UL */ + MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, BT_UL_L_labelID, + BT_UL_R_labelID, AMIC_L_labelID, AMIC_R_labelID, + ZERO_labelID, ZERO_labelID, ZERO_labelID, ZERO_labelID, + /* 10 .. 11 = MM_UL2 */ + EchoRef_L_labelID, EchoRef_R_labelID, + /* 12 .. 13 = VX_UL */ + AMIC_L_labelID, AMIC_L_labelID, + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, +}; +/* all default routing configurations */ +abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL]; +/* + * ABE SUBROUTINES AND SEQUENCES + */ +/* +const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] = + {{0, 0, 0, 0}, {-1, 0, 0, 0} }, + {{0, 0, 0, 0}, {-1, 0, 0, 0} }, +const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1, 0, 0, 0, 0, + -1, C_CALLBACK1, 0, 0, 0, 0 }; +const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] = + abe_init_atc, 0, 0, + abe_init_atc, 0, 0, + typedef double (*PtrFun) (double); +PtrFun pFun; +pFun = sin; + y = (* pFun) (x); +*//* mask, { time id param tag1} */ +const abe_sequence_t seq_null = { + NOMASK, {CL_M1, 0, {0, 0, 0, 0}, 0}, {CL_M1, 0, {0, 0, 0, 0}, 0} +}; +/* table of new subroutines called in the sequence */ +abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE]; +/* number of parameters per calls */ +u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE]; +/* index of the subroutine */ +u32 abe_subroutine_id[MAXNBSUBROUTINE]; +/* paramters of the subroutine (if any) */ +u32 *abe_all_subroutine_params[MAXNBSUBROUTINE]; +u32 abe_subroutine_write_pointer; +/* table of all sequences */ +abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; +u32 abe_sequence_write_pointer; +/* current number of pending sequences (avoids to look in the table) */ +u32 abe_nb_pending_sequences; +/* pending sequences due to ressource collision */ +u32 abe_pending_sequences[MAXNBSEQUENCE]; +/* mask of unsharable ressources among other sequences */ +u32 abe_global_sequence_mask; +/* table of active sequences */ +abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS]; +/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */ +u32 abe_irq_pingpong_player_id; +EXPORT_SYMBOL_GPL(abe_irq_pingpong_player_id); + +/* index of the plugged subroutine doing acoustics protection adaptation */ +u32 abe_irq_aps_adaptation_id; +/* base addresses of the ping pong buffers in bytes addresses */ +u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS]; +/* size of each ping/pong buffers */ +u32 abe_size_pingpong; +/* number of ping/pong buffer being used */ +u32 abe_nb_pingpong; +/* current EVENT */ +u32 abe_current_event_id; +/* + * ABE CONST AREA FOR PARAMETERS TRANSLATION + */ +const u32 abe_db2lin_table[sizeof_db2lin_table] = { + 0x00000000, /* SMEM coding of -120 dB */ + 0x00000000, /* SMEM coding of -119 dB */ + 0x00000000, /* SMEM coding of -118 dB */ + 0x00000000, /* SMEM coding of -117 dB */ + 0x00000000, /* SMEM coding of -116 dB */ + 0x00000000, /* SMEM coding of -115 dB */ + 0x00000000, /* SMEM coding of -114 dB */ + 0x00000000, /* SMEM coding of -113 dB */ + 0x00000000, /* SMEM coding of -112 dB */ + 0x00000000, /* SMEM coding of -111 dB */ + 0x00000000, /* SMEM coding of -110 dB */ + 0x00000000, /* SMEM coding of -109 dB */ + 0x00000001, /* SMEM coding of -108 dB */ + 0x00000001, /* SMEM coding of -107 dB */ + 0x00000001, /* SMEM coding of -106 dB */ + 0x00000001, /* SMEM coding of -105 dB */ + 0x00000001, /* SMEM coding of -104 dB */ + 0x00000001, /* SMEM coding of -103 dB */ + 0x00000002, /* SMEM coding of -102 dB */ + 0x00000002, /* SMEM coding of -101 dB */ + 0x00000002, /* SMEM coding of -100 dB */ + 0x00000002, /* SMEM coding of -99 dB */ + 0x00000003, /* SMEM coding of -98 dB */ + 0x00000003, /* SMEM coding of -97 dB */ + 0x00000004, /* SMEM coding of -96 dB */ + 0x00000004, /* SMEM coding of -95 dB */ + 0x00000005, /* SMEM coding of -94 dB */ + 0x00000005, /* SMEM coding of -93 dB */ + 0x00000006, /* SMEM coding of -92 dB */ + 0x00000007, /* SMEM coding of -91 dB */ + 0x00000008, /* SMEM coding of -90 dB */ + 0x00000009, /* SMEM coding of -89 dB */ + 0x0000000A, /* SMEM coding of -88 dB */ + 0x0000000B, /* SMEM coding of -87 dB */ + 0x0000000D, /* SMEM coding of -86 dB */ + 0x0000000E, /* SMEM coding of -85 dB */ + 0x00000010, /* SMEM coding of -84 dB */ + 0x00000012, /* SMEM coding of -83 dB */ + 0x00000014, /* SMEM coding of -82 dB */ + 0x00000017, /* SMEM coding of -81 dB */ + 0x0000001A, /* SMEM coding of -80 dB */ + 0x0000001D, /* SMEM coding of -79 dB */ + 0x00000021, /* SMEM coding of -78 dB */ + 0x00000025, /* SMEM coding of -77 dB */ + 0x00000029, /* SMEM coding of -76 dB */ + 0x0000002E, /* SMEM coding of -75 dB */ + 0x00000034, /* SMEM coding of -74 dB */ + 0x0000003A, /* SMEM coding of -73 dB */ + 0x00000041, /* SMEM coding of -72 dB */ + 0x00000049, /* SMEM coding of -71 dB */ + 0x00000052, /* SMEM coding of -70 dB */ + 0x0000005D, /* SMEM coding of -69 dB */ + 0x00000068, /* SMEM coding of -68 dB */ + 0x00000075, /* SMEM coding of -67 dB */ + 0x00000083, /* SMEM coding of -66 dB */ + 0x00000093, /* SMEM coding of -65 dB */ + 0x000000A5, /* SMEM coding of -64 dB */ + 0x000000B9, /* SMEM coding of -63 dB */ + 0x000000D0, /* SMEM coding of -62 dB */ + 0x000000E9, /* SMEM coding of -61 dB */ + 0x00000106, /* SMEM coding of -60 dB */ + 0x00000126, /* SMEM coding of -59 dB */ + 0x0000014A, /* SMEM coding of -58 dB */ + 0x00000172, /* SMEM coding of -57 dB */ + 0x0000019F, /* SMEM coding of -56 dB */ + 0x000001D2, /* SMEM coding of -55 dB */ + 0x0000020B, /* SMEM coding of -54 dB */ + 0x0000024A, /* SMEM coding of -53 dB */ + 0x00000292, /* SMEM coding of -52 dB */ + 0x000002E2, /* SMEM coding of -51 dB */ + 0x0000033C, /* SMEM coding of -50 dB */ + 0x000003A2, /* SMEM coding of -49 dB */ + 0x00000413, /* SMEM coding of -48 dB */ + 0x00000492, /* SMEM coding of -47 dB */ + 0x00000521, /* SMEM coding of -46 dB */ + 0x000005C2, /* SMEM coding of -45 dB */ + 0x00000676, /* SMEM coding of -44 dB */ + 0x0000073F, /* SMEM coding of -43 dB */ + 0x00000822, /* SMEM coding of -42 dB */ + 0x00000920, /* SMEM coding of -41 dB */ + 0x00000A3D, /* SMEM coding of -40 dB */ + 0x00000B7D, /* SMEM coding of -39 dB */ + 0x00000CE4, /* SMEM coding of -38 dB */ + 0x00000E76, /* SMEM coding of -37 dB */ + 0x0000103A, /* SMEM coding of -36 dB */ + 0x00001235, /* SMEM coding of -35 dB */ + 0x0000146E, /* SMEM coding of -34 dB */ + 0x000016EC, /* SMEM coding of -33 dB */ + 0x000019B8, /* SMEM coding of -32 dB */ + 0x00001CDC, /* SMEM coding of -31 dB */ + 0x00002061, /* SMEM coding of -30 dB */ + 0x00002455, /* SMEM coding of -29 dB */ + 0x000028C4, /* SMEM coding of -28 dB */ + 0x00002DBD, /* SMEM coding of -27 dB */ + 0x00003352, /* SMEM coding of -26 dB */ + 0x00003995, /* SMEM coding of -25 dB */ + 0x0000409C, /* SMEM coding of -24 dB */ + 0x0000487E, /* SMEM coding of -23 dB */ + 0x00005156, /* SMEM coding of -22 dB */ + 0x00005B43, /* SMEM coding of -21 dB */ + 0x00006666, /* SMEM coding of -20 dB */ + 0x000072E5, /* SMEM coding of -19 dB */ + 0x000080E9, /* SMEM coding of -18 dB */ + 0x000090A4, /* SMEM coding of -17 dB */ + 0x0000A24B, /* SMEM coding of -16 dB */ + 0x0000B618, /* SMEM coding of -15 dB */ + 0x0000CC50, /* SMEM coding of -14 dB */ + 0x0000E53E, /* SMEM coding of -13 dB */ + 0x00010137, /* SMEM coding of -12 dB */ + 0x0001209A, /* SMEM coding of -11 dB */ + 0x000143D1, /* SMEM coding of -10 dB */ + 0x00016B54, /* SMEM coding of -9 dB */ + 0x000197A9, /* SMEM coding of -8 dB */ + 0x0001C967, /* SMEM coding of -7 dB */ + 0x00020137, /* SMEM coding of -6 dB */ + 0x00023FD6, /* SMEM coding of -5 dB */ + 0x00028619, /* SMEM coding of -4 dB */ + 0x0002D4EF, /* SMEM coding of -3 dB */ + 0x00032D64, /* SMEM coding of -2 dB */ + 0x000390A4, /* SMEM coding of -1 dB */ + 0x00040000, /* SMEM coding of 0 dB */ + 0x00047CF2, /* SMEM coding of 1 dB */ + 0x00050923, /* SMEM coding of 2 dB */ + 0x0005A670, /* SMEM coding of 3 dB */ + 0x000656EE, /* SMEM coding of 4 dB */ + 0x00071CF5, /* SMEM coding of 5 dB */ + 0x0007FB26, /* SMEM coding of 6 dB */ + 0x0008F473, /* SMEM coding of 7 dB */ + 0x000A0C2B, /* SMEM coding of 8 dB */ + 0x000B4606, /* SMEM coding of 9 dB */ + 0x000CA62C, /* SMEM coding of 10 dB */ + 0x000E314A, /* SMEM coding of 11 dB */ + 0x000FEC9E, /* SMEM coding of 12 dB */ + 0x0011DE0A, /* SMEM coding of 13 dB */ + 0x00140C28, /* SMEM coding of 14 dB */ + 0x00167E60, /* SMEM coding of 15 dB */ + 0x00193D00, /* SMEM coding of 16 dB */ + 0x001C515D, /* SMEM coding of 17 dB */ + 0x001FC5EB, /* SMEM coding of 18 dB */ + 0x0023A668, /* SMEM coding of 19 dB */ + 0x00280000, /* SMEM coding of 20 dB */ + 0x002CE178, /* SMEM coding of 21 dB */ + 0x00325B65, /* SMEM coding of 22 dB */ + 0x00388062, /* SMEM coding of 23 dB */ + 0x003F654E, /* SMEM coding of 24 dB */ + 0x00472194, /* SMEM coding of 25 dB */ + 0x004FCF7C, /* SMEM coding of 26 dB */ + 0x00598C81, /* SMEM coding of 27 dB */ + 0x006479B7, /* SMEM coding of 28 dB */ + 0x0070BC3D, /* SMEM coding of 29 dB */ + 0x007E7DB9, /* SMEM coding of 30 dB */ +}; +const u32 abe_1_alpha_iir[64] = { + 0x040002, 0x040002, 0x040002, 0x040002, /* 0 */ + 0x50E955, 0x48CA65, 0x40E321, 0x72BE78, /* 1 [ms] */ + 0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, /* 2 */ + 0x38A084, 0x308974, 0x297B00, 0x235C7C, /* 4 */ + 0x1E14B0, 0x198AF0, 0x15A800, 0x125660, /* 8 */ + 0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, /* 16 */ + 0x07E054, 0x06A3B8, 0x059844, 0x04B680, /* 32 */ + 0x03F80C, 0x035774, 0x02D018, 0x025E0C, /* 64 */ + 0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, /* 128 */ + 0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, /* 256 */ + 0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, /* 512 */ + 0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, /* 1.024 [s] */ + 0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, /* 2.048 */ + 0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, /* 4.096 */ + 0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, /* 8.192 */ + 0x00FFFF, 0x00D743, 0x00B503, 0x009837, +}; +const u32 abe_alpha_iir[64] = { + 0x000000, 0x000000, 0x000000, 0x000000, /* 0 */ + 0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, /* 1 [ms] */ + 0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, /* 2 */ + 0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, /* 4 */ + 0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, /* 8 */ + 0x783EB1, 0x797251, 0x7A7761, 0x7B549D, /* 16 */ + 0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, /* 32 */ + 0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, /* 64 */ + 0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, /* 128 */ + 0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, /* 256 */ + 0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, /* 512 */ + 0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, /* 1.024 [s] */ + 0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, /* 2.048 */ + 0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, /* 4.096 */ + 0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, /* 8.192 */ + 0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1, +}; +/* + * ABE_DEBUG DATA + */ +/* + * IRQ and trace pointer in DMEM: + * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL + */ +u32 abe_irq_dbg_read_ptr; +/* + * General circular buffer used to trace APIs calls and AE activity. + */ +u32 abe_dbg_activity_log[D_DEBUG_HAL_TASK_sizeof]; +u32 abe_dbg_activity_log_write_pointer; +u32 abe_dbg_mask; +/* + * Global variable holding parameter errors + */ +u32 abe_dbg_param; +/* + * Output of messages selector + */ +u32 abe_dbg_output; +/* + * last parameters + */ +#define SIZE_PARAM 10 +u32 param1[SIZE_PARAM]; +u32 param2[SIZE_PARAM]; +u32 param3[SIZE_PARAM]; +u32 param4[SIZE_PARAM]; +u32 param5[SIZE_PARAM]; +/* + * MAIN PORT SELECTION + */ +const u32 abe_port_priority[LAST_PORT_ID - 1] = { + PDM_DL_PORT, + PDM_UL_PORT, + MM_EXT_OUT_PORT, + MM_EXT_IN_PORT, + TDM_DL_PORT, + TDM_UL_PORT, + DMIC_PORT, + MM_UL_PORT, + MM_UL2_PORT, + MM_DL_PORT, + TONES_DL_PORT, + VX_UL_PORT, + VX_DL_PORT, + BT_VX_DL_PORT, + BT_VX_UL_PORT, + VIB_DL_PORT, +}; +/* + * ABE CONST AREA FOR DMIC DECIMATION FILTERS + */ +/* const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +*/ +#endif/* abe_dat_c */ diff --git a/sound/soc/omap/abe/abe_dbg.c b/sound/soc/omap/abe/abe_dbg.c new file mode 100644 index 00000000000..1c4435d66f0 --- /dev/null +++ b/sound/soc/omap/abe/abe_dbg.c @@ -0,0 +1,197 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +/** + * abe_dbg_log - Log ABE trace inside circular buffer + * @x: data to be logged + * @y: data to be logged + * @z: data to be logged + * @t: data to be logged + * Parameter : + * + * abe_dbg_activity_log : global circular buffer holding the data + * abe_dbg_activity_log_write_pointer : circular write pointer + * + * saves data in the log file + */ +void abe_dbg_log(u32 x, u32 y, u32 z, u32 t) +{ + u32 time_stamp, data; + if (abe_dbg_activity_log_write_pointer >= (D_DEBUG_HAL_TASK_sizeof - 2)) + abe_dbg_activity_log_write_pointer = 0; + /* copy in DMEM trace buffer and CortexA9 local buffer and a small 7 + words circular buffer of the DMA trace ending with 0x55555555 + (tag for last word) */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_loopCounter_ADDR, + (u32 *) &time_stamp, sizeof(time_stamp)); + abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = time_stamp; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + + (abe_dbg_activity_log_write_pointer << 2), + (u32 *) &time_stamp, sizeof(time_stamp)); + abe_dbg_activity_log_write_pointer++; + data = ((x & MAX_UINT8) << 24) | ((y & MAX_UINT8) << 16) | + ((z & MAX_UINT8) << 8) + | (t & MAX_UINT8); + abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = data; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + + (abe_dbg_activity_log_write_pointer << 2), + (u32 *) &data, sizeof(data)); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_DEBUG_FIFO_HAL_ADDR + + ((abe_dbg_activity_log_write_pointer << 2) & + (D_DEBUG_FIFO_HAL_sizeof - 1)), (u32 *) &data, + sizeof(data)); + data = ABE_DBG_MAGIC_NUMBER; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR + + (((abe_dbg_activity_log_write_pointer + + 1) << 2) &(D_DEBUG_FIFO_HAL_sizeof - 1)), + (u32 *) &data, sizeof(data)); + abe_dbg_activity_log_write_pointer++; + if (abe_dbg_activity_log_write_pointer >= D_DEBUG_HAL_TASK_sizeof) + abe_dbg_activity_log_write_pointer = 0; +} +/** + * abe_debug_output_pins + * @x: d + * + * set the debug output pins of AESS + */ +void abe_debug_output_pins(u32 x) +{ +} +/** + * abe_dbg_error_log - Log ABE error + * @x: error to log + * + * log the error codes + */ +void abe_dbg_error_log(u32 x) +{ + abe_dbg_log(x, MAX_UINT8, MAX_UINT8, MAX_UINT8); +} +/** + * abe_debugger + * @x: error to log + * + * log error for debugger + */ +void abe_debugger(u32 x) +{ +} +/** + * abe_load_embeddded_patterns + * + * load test patterns + * + * S = power (2, 31) * 0.25; + * N = 4; B = 2; F=[1/N 1/N]; gen_and_save('dbg_8k_2.txt', B, F, N, S); + * N = 8; B = 2; F=[1/N 2/N]; gen_and_save('dbg_16k_2.txt', B, F, N, S); + * N = 12; B = 2; F=[1/N 2/N]; gen_and_save('dbg_48k_2.txt', B, F, N, S); + * N = 60; B = 2; F=[4/N 8/N]; gen_and_save('dbg_amic.txt', B, F, N, S); + * N = 10; B = 6; F=[1/N 2/N 3/N 1/N 2/N 3/N]; gen_and_save('dbg_dmic.txt', B, F, N, S); +*/ +void abe_load_embeddded_patterns(void) +{ + u32 i; +#define patterns_96k_len 48 + const long patterns_96k[patterns_96k_len] = { + 1620480, 1452800, + 1452800, 838656, + 1186304, 0, + 838656, -838912, + 434176, -1453056, + 0, -1677824, + -434432, -1453056, + -838912, -838912, + -1186560, -256, + -1453056, 838656, + -1620736, 1452800, + -1677824, 1677568, + -1620736, 1452800, + -1453056, 838656, + -1186560, 0, + -838912, -838912, + -434432, -1453056, + -256, -1677824, + 434176, -1453056, + 838656, -838912, + 1186304, -256, + 1452800, 838656, + 1620480, 1452800, + 1677568, 1677568, + }; +#define patterns_48k_len 24 + const long patterns_48k[patterns_48k_len] = { + 1452800, 838656, + 838656, -838912, + 0, -1677824, + -838912, -838912, + -1453056, 838656, + -1677824, 1677568, + -1453056, 838656, + -838912, -838912, + -256, -1677824, + 838656, -838912, + 1452800, 838656, + 1677568, 1677568, + }; +#define patterns_24k_len 12 + const long patterns_24k[patterns_24k_len] = { + 838656, -838912, + -838912, -838912, + -1677824, 1677568, + -838912, -838912, + 838656, -838912, + 1677568, 1677568, + }; +#define patterns_16k_len 8 + const long patterns_16k[patterns_16k_len] = { + 0, 0, + -1677824, -1677824, + -256, -256, + 1677568, 1677568, + }; +#define patterns_8k_len 4 + const long patterns_8k[patterns_8k_len] = { + 1677568, -1677824, + 1677568, 1677568, + }; + for (i = 0; i < patterns_8k_len; i++) + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_8K_PATTERN_ADDR * 8) + (i * 4), + (u32 *) (&(patterns_8k[i])), 4); + for (i = 0; i < patterns_16k_len; i++) + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_16K_PATTERN_ADDR * 8) + (i * 4), + (u32 *) (&(patterns_16k[i])), 4); + for (i = 0; i < patterns_24k_len; i++) + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_24K_PATTERN_ADDR * 8) + (i * 4), + (u32 *) (&(patterns_24k[i])), 4); + for (i = 0; i < patterns_48k_len; i++) + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_48K_PATTERN_ADDR * 8) + (i * 4), + (u32 *) (&(patterns_48k[i])), 4); + for (i = 0; i < patterns_96k_len; i++) + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_96K_PATTERN_ADDR * 8) + (i * 4), + (u32 *) (&(patterns_96k[i])), 4); +} diff --git a/sound/soc/omap/abe/abe_dbg.h b/sound/soc/omap/abe/abe_dbg.h new file mode 100644 index 00000000000..038f29c8a2f --- /dev/null +++ b/sound/soc/omap/abe/abe_dbg.h @@ -0,0 +1,149 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +/* + * DEFINE + */ +#define NO_OUTPUT 0 +#define TERMINAL_OUTPUT 1 +#define LINE_OUTPUT 2 +#define DEBUG_TRACE_OUTPUT 3 +/* + * Debug trace format + * TIME 2 bytes from ABE : 4kHz period of the FW scheduler + * SUBID 1 byte : HAL API index + * From 0 to 16 bytes : parameters of the subroutine + * on every 32 dumps a tag is pushed on the debug trace : 0x55555555 + */ +#define dbg_bitfield_offset 8 +#define dbg_api_calls 0 +#define dbg_mapi (1L << (dbg_api_calls + dbg_bitfield_offset)) +#define dbg_external_data_access 1 +#define dbg_mdata (1L << (dbg_external_data_access + dbg_bitfield_offset)) +#define dbg_err_codes 2 +#define dbg_merr (1L << (dbg_api_calls + dbg_bitfield_offset)) +#define ABE_DBG_MAGIC_NUMBER 0x55555555 +/* + * IDs used for traces + */ +#define id_reset_hal (1 + dbg_mapi) +#define id_load_fw (2 + dbg_mapi) +#define id_default_configuration (3 + dbg_mapi) +#define id_irq_processing (4 + dbg_mapi) +#define id_event_generator_switch (5 + dbg_mapi) +#define id_read_hardware_configuration (6 + dbg_mapi) +#define id_read_lowest_opp (7 + dbg_mapi) +#define id_write_gain (8 + dbg_mapi) +#define id_set_asrc_drift_control (9 + dbg_mapi) +#define id_plug_subroutine (10 + dbg_mapi) +#define id_unplug_subroutine (11 + dbg_mapi) +#define id_plug_sequence (12 + dbg_mapi) +#define id_launch_sequence (13 + dbg_mapi) +#define id_launch_sequence_param (14 + dbg_mapi) +#define id_connect_irq_ping_pong_port (15 + dbg_mapi) +#define id_read_analog_gain_dl (16 + dbg_mapi) +#define id_read_analog_gain_ul (17 + dbg_mapi) +#define id_enable_dyn_ul_gain (18 + dbg_mapi) +#define id_disable_dyn_ul_gain (19 + dbg_mapi) +#define id_enable_dyn_extension (20 + dbg_mapi) +#define id_disable_dyn_extension (21 + dbg_mapi) +#define id_notify_analog_gain_changed (22 + dbg_mapi) +#define id_reset_port (23 + dbg_mapi) +#define id_read_remaining_data (24 + dbg_mapi) +#define id_disable_data_transfer (25 + dbg_mapi) +#define id_enable_data_transfer (26 + dbg_mapi) +#define id_read_global_counter (27 + dbg_mapi) +#define id_set_dmic_filter (28 + dbg_mapi) +#define id_set_opp_processing (29 + dbg_mapi) +#define id_set_ping_pong_buffer (30 + dbg_mapi) +#define id_read_port_address (31 + dbg_mapi) +#define id_load_fw_param (32 + dbg_mapi) +#define id_write_headset_offset (33 + dbg_mapi) +#define id_read_gain_ranges (34 + dbg_mapi) +#define id_write_equalizer (35 + dbg_mapi) +#define id_write_asrc (36 + dbg_mapi) +#define id_write_aps (37 + dbg_mapi) +#define id_write_mixer (38 + dbg_mapi) +#define id_write_eanc (39 + dbg_mapi) +#define id_write_router (40 + dbg_mapi) +#define id_read_port_gain (41 + dbg_mapi) +#define id_read_asrc (42 + dbg_mapi) +#define id_read_aps (43 + dbg_mapi) +#define id_read_aps_energy (44 + dbg_mapi) +#define id_read_mixer (45 + dbg_mapi) +#define id_read_eanc (46 + dbg_mapi) +#define id_read_router (47 + dbg_mapi) +#define id_read_debug_trace (48 + dbg_mapi) +#define id_set_sequence_time_accuracy (49 + dbg_mapi) +#define id_set_debug_pins (50 + dbg_mapi) +#define id_select_main_port (51 + dbg_mapi) +#define id_write_event_generator (52 + dbg_mapi) +#define id_read_use_case_opp (53 + dbg_mapi) +#define id_select_data_source (54 + dbg_mapi) +#define id_read_next_ping_pong_buffer (55 + dbg_mapi) +#define id_init_ping_pong_buffer (56 + dbg_mapi) +#define id_connect_cbpr_dmareq_port (57 + dbg_mapi) +#define id_connect_dmareq_port (58 + dbg_mapi) +#define id_connect_dmareq_ping_pong_port (59 + dbg_mapi) +#define id_connect_serial_port (60 + dbg_mapi) +#define id_connect_slimbus_port (61 + dbg_mapi) +#define id_read_gain (62 + dbg_mapi) +#define id_set_router_configuration (63 + dbg_mapi) +#define id_connect_debug_trace (64 + dbg_mapi) +#define id_set_debug_trace (65 + dbg_mapi) +#define id_remote_debugger_interface (66 + dbg_mapi) +#define id_enable_test_pattern (67 + dbg_mapi) +#define id_connect_tdm_port (68 + dbg_mapi) +/* + * IDs used for error codes + */ +#define NOERR 0 +#define ABE_SET_MEMORY_CONFIG_ERR (1 + dbg_merr) +#define ABE_BLOCK_COPY_ERR (2 + dbg_merr) +#define ABE_SEQTOOLONG (3 + dbg_merr) +#define ABE_BADSAMPFORMAT (4 + dbg_merr) +#define ABE_SET_ATC_MEMORY_CONFIG_ERR (5 + dbg_merr) +#define ABE_PROTOCOL_ERROR (6 + dbg_merr) +#define ABE_PARAMETER_ERROR (7 + dbg_merr) +/* port programmed while still running */ +#define ABE_PORT_REPROGRAMMING (8 + dbg_merr) +#define ABE_READ_USE_CASE_OPP_ERR (9 + dbg_merr) +#define ABE_PARAMETER_OVERFLOW (10 + dbg_merr) +#define ABE_FW_FIFO_WRITE_PTR_ERR (11 + dbg_merr) +/* + * IDs used for error codes + */ +/* error in the LIB.C file */ +#define ERR_LIB (1 << 1) +/* error in the API.C file */ +#define ERR_API (1 << 2) +/* error in the INI.C file */ +#define ERR_INI (1 << 3) +/* error in the SEQ.C file */ +#define ERR_SEQ (1 << 4) +/* error in the DBG.C file */ +#define ERR_DBG (1 << 5) +/* error in the DBG.C file */ +#define ERR_EXT (1 << 6) +/* + * MACROS + */ +#define _log(x, y, z, t) {if (x & abe_dbg_mask) abe_dbg_log(x, y, z, t); } diff --git a/sound/soc/omap/abe/abe_def.h b/sound/soc/omap/abe/abe_def.h new file mode 100644 index 00000000000..af2cbc689f9 --- /dev/null +++ b/sound/soc/omap/abe/abe_def.h @@ -0,0 +1,274 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_DEF_H_ +#define _ABE_DEF_H_ +/* + * HARDWARE AND PERIPHERAL DEFINITIONS + */ +/* MM_DL */ +#define ABE_CBPR0_IDX 0 +/* VX_DL */ +#define ABE_CBPR1_IDX 1 +/* VX_UL */ +#define ABE_CBPR2_IDX 2 +/* MM_UL */ +#define ABE_CBPR3_IDX 3 +/* MM_UL2 */ +#define ABE_CBPR4_IDX 4 +/* TONES */ +#define ABE_CBPR5_IDX 5 +/* VIB */ +#define ABE_CBPR6_IDX 6 +/* DEBUG/CTL */ +#define ABE_CBPR7_IDX 7 +#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4) +#define PING_PONG_WITH_MCU_IRQ 1 +#define PING_PONG_WITH_DSP_IRQ 2 +/* ID used for LIB memory copy subroutines */ +#define COPY_FROM_ABE_TO_HOST 1 +#define COPY_FROM_HOST_TO_ABE 2 +/* + * INTERNAL DEFINITIONS + */ +#define ABE_FIRMWARE_MAX_SIZE 26629 +/* 24 Q6.26 coefficients */ +#define NBEQ1 25 +/* 2x12 Q6.26 coefficients */ +#define NBEQ2 13 +/* TBD APS first set of parameters */ +#define NBAPS1 10 +/* TBD APS second set of parameters */ +#define NBAPS2 10 +/* Mixer used for sending tones to the uplink voice path */ +#define NBMIX_AUDIO_UL 2 +/* Main downlink mixer */ +#define NBMIX_DL1 4 +/* Handsfree downlink mixer */ +#define NBMIX_DL2 4 +/* Side-tone mixer */ +#define NBMIX_SDT 2 +/* Echo reference mixer */ +#define NBMIX_ECHO 2 +/* Voice record mixer */ +#define NBMIX_VXREC 4 +/* unsigned version of (-1) */ +#define CC_M1 0xFF +#define CS_M1 0xFFFF +#define CL_M1 0xFFFFFFFFL +/* + Mixer ID Input port ID Comments + DL1_MIXER 0 MMDL path + 1 MMUL2 path + 2 VXDL path + 3 TONES path + SDT_MIXER 0 Uplink path + 1 Downlink path + ECHO_MIXER 0 DL1_MIXER path + 1 DL2_MIXER path + AUDUL_MIXER 0 TONES_DL path + 1 Uplink path + 2 MM_DL path + VXREC_MIXER 0 TONES_DL path + 1 VX_DL path + 2 MM_DL path + 3 VX_UL path +*/ +#define MIX_VXUL_INPUT_MM_DL 0 +#define MIX_VXUL_INPUT_TONES 1 +#define MIX_VXUL_INPUT_VX_UL 2 +#define MIX_VXUL_INPUT_VX_DL 3 +#define MIX_DL1_INPUT_MM_DL 0 +#define MIX_DL1_INPUT_MM_UL2 1 +#define MIX_DL1_INPUT_VX_DL 2 +#define MIX_DL1_INPUT_TONES 3 +#define MIX_DL2_INPUT_MM_DL 0 +#define MIX_DL2_INPUT_MM_UL2 1 +#define MIX_DL2_INPUT_VX_DL 2 +#define MIX_DL2_INPUT_TONES 3 +#define MIX_SDT_INPUT_UP_MIXER 0 +#define MIX_SDT_INPUT_DL1_MIXER 1 +#define MIX_AUDUL_INPUT_MM_DL 0 +#define MIX_AUDUL_INPUT_TONES 1 +#define MIX_AUDUL_INPUT_UPLINK 2 +#define MIX_AUDUL_INPUT_VX_DL 3 +#define MIX_VXREC_INPUT_MM_DL 0 +#define MIX_VXREC_INPUT_TONES 1 +#define MIX_VXREC_INPUT_VX_UL 2 +#define MIX_VXREC_INPUT_VX_DL 3 +#define MIX_ECHO_DL1 0 +#define MIX_ECHO_DL2 1 +/* nb of samples to route */ +#define NBROUTE_UL 16 +/* 10 routing tables max */ +#define NBROUTE_CONFIG_MAX 10 +/* 5 pre-computed routing tables */ +#define NBROUTE_CONFIG 6 +/* AMIC on VX_UL */ +#define UPROUTE_CONFIG_AMIC 0 +/* DMIC first pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC1 1 +/* DMIC second pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC2 2 +/* DMIC last pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC3 3 +/* BT_UL on VX_UL */ +#define UPROUTE_CONFIG_BT 4 +/* ECHO_REF on MM_UL2 */ +#define UPROUTE_ECHO_MMUL2 5 +/* call-back indexes */ +#define MAXCALLBACK 100 +/* subroutines */ +#define MAXNBSUBROUTINE 100 +/* time controlled sequenced */ +#define MAXNBSEQUENCE 20 +/* maximum simultaneous active sequences */ +#define MAXACTIVESEQUENCE 20 +/* max number of steps in the sequences */ +#define MAXSEQUENCESTEPS 2 +/* max number of feature associated to a port */ +#define MAXFEATUREPORT 12 +#define SUB_0_PARAM 0 +/* number of parameters per sequence calls */ +#define SUB_1_PARAM 1 +#define SUB_2_PARAM 2 +#define SUB_3_PARAM 3 +#define SUB_4_PARAM 4 +/* active sequence mask = 0 means the line is free */ +#define FREE_LINE 0 +/* no ask for collision protection */ +#define NOMASK (1 << 0) +/* do not allow a PDM OFF during the execution of this sequence */ +#define MASK_PDM_OFF (1 << 1) +/* do not allow a PDM ON during the execution of this sequence */ +#define MASK_PDM_ON (1 << 2) +/* explicit name of the feature */ +#define NBCHARFEATURENAME 16 +/* explicit name of the port */ +#define NBCHARPORTNAME 16 +/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */ +#define SNK_P ABE_ATC_DIRECTION_IN +/* source / ouptut port */ +#define SRC_P ABE_ATC_DIRECTION_OUT +/* no ASRC applied */ +#define NODRIFT 0 +/* for abe_set_asrc_drift_control */ +#define FORCED_DRIFT_CONTROL 1 +/* for abe_set_asrc_drift_control */ +#define ADPATIVE_DRIFT_CONTROL 2 +/* number of task/slot depending on the OPP value */ +#define DOPPMODE32_OPP100 (0x00000010) +#define DOPPMODE32_OPP50 (0x0000000C) +#define DOPPMODE32_OPP25 (0x0000004) +/* + * ABE CONST AREA FOR PARAMETERS TRANSLATION + */ +#define min_mdb (-12000) +#define max_mdb ( 3000) +#define sizeof_db2lin_table (1 + ((max_mdb - min_mdb)/100)) +#define sizeof_alpha_iir_table 61 +#define sizeof_beta_iir_table 61 +#define GAIN_MAXIMUM 3000L +#define GAIN_24dB 2400L +#define GAIN_18dB 1800L +#define GAIN_12dB 1200L +#define GAIN_6dB 600L +/* default gain = 1 */ +#define GAIN_0dB 0L +#define GAIN_M6dB -600L +#define GAIN_M12dB -1200L +#define GAIN_M18dB -1800L +#define GAIN_M24dB -2400L +#define GAIN_M30dB -3000L +#define GAIN_M40dB -4000L +#define GAIN_M50dB -5000L +/* muted gain = -120 decibels */ +#define MUTE_GAIN -12000L +#define GAIN_TOOLOW -13000L +#define GAIN_MUTE MUTE_GAIN +#define RAMP_MINLENGTH 3L +/* ramp_t is in milli- seconds */ +#define RAMP_0MS 0L +#define RAMP_1MS 1L +#define RAMP_2MS 2L +#define RAMP_5MS 5L +#define RAMP_10MS 10L +#define RAMP_20MS 20L +#define RAMP_50MS 50L +#define RAMP_100MS 100L +#define RAMP_200MS 200L +#define RAMP_500MS 500L +#define RAMP_1000MS 1000L +#define RAMP_MAXLENGTH 10000L +/* for abe_translate_gain_format */ +#define LINABE_TO_DECIBELS 1 +#define DECIBELS_TO_LINABE 2 +/* for abe_translate_ramp_format */ +#define IIRABE_TO_MICROS 1 +#define MICROS_TO_IIABE 2 +/* + * ABE CONST AREA FOR PERIPHERAL TUNING + */ +/* port idled IDLE_P */ +#define OMAP_ABE_PORT_ACTIVITY_IDLE 1 +/* port initialized, ready to be activated */ +#define OMAP_ABE_PORT_INITIALIZED 3 +/* port activated RUN_P */ +#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2 +#define NOCALLBACK 0 +#define NOPARAMETER 0 +/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */ +#define MCPDM_UL_ITER 4 +/* All the McPDM FIFOs are enabled simultaneously */ +#define MCPDM_DL_ITER 24 +/* All the DMIC FIFOs are enabled simultaneously */ +#define DMIC_ITER 12 +/* TBD later if needed */ +#define MAX_PINGPONG_BUFFERS 2 +/* + * Indexes to the subroutines + */ +#define SUB_WRITE_MIXER 1 +#define SUB_WRITE_PORT_GAIN 2 +/* OLD WAY */ +#define c_feat_init_eq 1 +#define c_feat_read_eq1 2 +#define c_write_eq1 3 +#define c_feat_read_eq2 4 +#define c_write_eq2 5 +#define c_feat_read_eq3 6 +#define c_write_eq3 7 +/* max number of gain to be controlled by HAL */ +#define MAX_NBGAIN_CMEM 34 +/* + * MACROS + */ +#define maximum(a,b) (((a)<(b))?(b):(a)) +#define minimum(a,b) (((a)>(b))?(b):(a)) +#define absolute(a) (((a)>0)?(a):((-1)*(a))) +#define HAL_VERSIONS 9 +#endif/* _ABE_DEF_H_ */ diff --git a/sound/soc/omap/abe/abe_define.h b/sound/soc/omap/abe/abe_define.h new file mode 100644 index 00000000000..ff54cc3490b --- /dev/null +++ b/sound/soc/omap/abe/abe_define.h @@ -0,0 +1,65 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_DEFINE_H_ +#define _ABE_DEFINE_H_ +#define ATC_DESCRIPTOR_NUMBER 64 +#define PROCESSING_SLOTS 25 +#define TASK_POOL_LENGTH 128 +#define MCU_IRQ 0x24 +#define MCU_IRQ_SHIFT2 0x90 +#define DMA_REQ_SHIFT2 0x210 +#define DSP_IRQ 0x4c +#define IRQtag_APS 0x000a +#define IRQtag_COUNT 0x000c +#define IRQtag_PP 0x000d +#define DMAreq_7 0x0080 +#define IRQ_FIFO_LENGTH 16 +#define SDT_EQ_ORDER 4 +#define DL_EQ_ORDER 12 +#define MIC_FILTER_ORDER 4 +#define GAINS_WITH_RAMP1 14 +#define GAINS_WITH_RAMP2 22 +#define GAINS_WITH_RAMP_TOTAL 36 +#define ASRC_MEMLENGTH 40 +#define ASRC_UL_VX_FIR_L 19 +#define ASRC_DL_VX_FIR_L 19 +#define ASRC_MM_EXT_IN_FIR_L 18 +#define ASRC_margin 2 +#define ASRC_N_8k 2 +#define ASRC_N_16k 4 +#define ASRC_N_48k 12 +#define VIBRA_N 5 +#define VIBRA1_IIR_MEMSIZE 11 +#define SAMP_LOOP_96K 24 +#define SAMP_LOOP_48K 12 +#define SAMP_LOOP_16K 4 +#define SAMP_LOOP_8K 2 +#define INPUT_SCALE_SHIFTM2 5052 +#define OUTPUT_SCALE_SHIFTM2 5056 +#define MUTE_SCALING 5060 +#define ABE_PMEM 1 +#define ABE_CMEM 2 +#define ABE_SMEM 3 +#define ABE_DMEM 4 +#define ABE_ATC 5 +#define ASRC_BT_UL_FIR_L 19 +#define ASRC_BT_DL_FIR_L 19 +#endif/* _ABE_DEFINE_H_ */ diff --git a/sound/soc/omap/abe/abe_dm_addr.h b/sound/soc/omap/abe/abe_dm_addr.h new file mode 100644 index 00000000000..a6a6c3df045 --- /dev/null +++ b/sound/soc/omap/abe/abe_dm_addr.h @@ -0,0 +1,326 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_DM_ADDR_H_ +#define _ABE_DM_ADDR_H_ +#define D_atcDescriptors_ADDR 0 +#define D_atcDescriptors_ADDR_END 511 +#define D_atcDescriptors_sizeof 512 +#define stack_ADDR 512 +#define stack_ADDR_END 623 +#define stack_sizeof 112 +#define D_version_ADDR 624 +#define D_version_ADDR_END 627 +#define D_version_sizeof 4 +#define D_BT_DL_FIFO_ADDR 1024 +#define D_BT_DL_FIFO_ADDR_END 1503 +#define D_BT_DL_FIFO_sizeof 480 +#define D_BT_UL_FIFO_ADDR 1536 +#define D_BT_UL_FIFO_ADDR_END 2015 +#define D_BT_UL_FIFO_sizeof 480 +#define D_MM_EXT_OUT_FIFO_ADDR 2048 +#define D_MM_EXT_OUT_FIFO_ADDR_END 2527 +#define D_MM_EXT_OUT_FIFO_sizeof 480 +#define D_MM_EXT_IN_FIFO_ADDR 2560 +#define D_MM_EXT_IN_FIFO_ADDR_END 3039 +#define D_MM_EXT_IN_FIFO_sizeof 480 +#define D_MM_UL2_FIFO_ADDR 3072 +#define D_MM_UL2_FIFO_ADDR_END 3551 +#define D_MM_UL2_FIFO_sizeof 480 +#define D_VX_UL_FIFO_ADDR 3584 +#define D_VX_UL_FIFO_ADDR_END 4063 +#define D_VX_UL_FIFO_sizeof 480 +#define D_VX_DL_FIFO_ADDR 4096 +#define D_VX_DL_FIFO_ADDR_END 4575 +#define D_VX_DL_FIFO_sizeof 480 +#define D_DMIC_UL_FIFO_ADDR 4608 +#define D_DMIC_UL_FIFO_ADDR_END 5087 +#define D_DMIC_UL_FIFO_sizeof 480 +#define D_MM_UL_FIFO_ADDR 5120 +#define D_MM_UL_FIFO_ADDR_END 5599 +#define D_MM_UL_FIFO_sizeof 480 +#define D_MM_DL_FIFO_ADDR 5632 +#define D_MM_DL_FIFO_ADDR_END 6111 +#define D_MM_DL_FIFO_sizeof 480 +#define D_TONES_DL_FIFO_ADDR 6144 +#define D_TONES_DL_FIFO_ADDR_END 6623 +#define D_TONES_DL_FIFO_sizeof 480 +#define D_VIB_DL_FIFO_ADDR 6656 +#define D_VIB_DL_FIFO_ADDR_END 7135 +#define D_VIB_DL_FIFO_sizeof 480 +#define D_McPDM_DL_FIFO_ADDR 7168 +#define D_McPDM_DL_FIFO_ADDR_END 7647 +#define D_McPDM_DL_FIFO_sizeof 480 +#define D_McPDM_UL_FIFO_ADDR 7680 +#define D_McPDM_UL_FIFO_ADDR_END 8159 +#define D_McPDM_UL_FIFO_sizeof 480 +#define D_DEBUG_FIFO_ADDR 8160 +#define D_DEBUG_FIFO_ADDR_END 8255 +#define D_DEBUG_FIFO_sizeof 96 +#define D_DEBUG_FIFO_HAL_ADDR 8256 +#define D_DEBUG_FIFO_HAL_ADDR_END 8287 +#define D_DEBUG_FIFO_HAL_sizeof 32 +#define D_IOdescr_ADDR 8288 +#define D_IOdescr_ADDR_END 8927 +#define D_IOdescr_sizeof 640 +#define d_zero_ADDR 8928 +#define d_zero_ADDR_END 8931 +#define d_zero_sizeof 4 +#define dbg_trace1_ADDR 8932 +#define dbg_trace1_ADDR_END 8932 +#define dbg_trace1_sizeof 1 +#define dbg_trace2_ADDR 8933 +#define dbg_trace2_ADDR_END 8933 +#define dbg_trace2_sizeof 1 +#define dbg_trace3_ADDR 8934 +#define dbg_trace3_ADDR_END 8934 +#define dbg_trace3_sizeof 1 +#define D_multiFrame_ADDR 8936 +#define D_multiFrame_ADDR_END 9335 +#define D_multiFrame_sizeof 400 +#define D_tasksList_ADDR 9336 +#define D_tasksList_ADDR_END 11383 +#define D_tasksList_sizeof 2048 +#define D_idleTask_ADDR 11384 +#define D_idleTask_ADDR_END 11385 +#define D_idleTask_sizeof 2 +#define D_typeLengthCheck_ADDR 11386 +#define D_typeLengthCheck_ADDR_END 11387 +#define D_typeLengthCheck_sizeof 2 +#define D_maxTaskBytesInSlot_ADDR 11388 +#define D_maxTaskBytesInSlot_ADDR_END 11389 +#define D_maxTaskBytesInSlot_sizeof 2 +#define D_rewindTaskBytes_ADDR 11390 +#define D_rewindTaskBytes_ADDR_END 11391 +#define D_rewindTaskBytes_sizeof 2 +#define D_pCurrentTask_ADDR 11392 +#define D_pCurrentTask_ADDR_END 11393 +#define D_pCurrentTask_sizeof 2 +#define D_pFastLoopBack_ADDR 11394 +#define D_pFastLoopBack_ADDR_END 11395 +#define D_pFastLoopBack_sizeof 2 +#define D_pNextFastLoopBack_ADDR 11396 +#define D_pNextFastLoopBack_ADDR_END 11399 +#define D_pNextFastLoopBack_sizeof 4 +#define D_ppCurrentTask_ADDR 11400 +#define D_ppCurrentTask_ADDR_END 11401 +#define D_ppCurrentTask_sizeof 2 +#define D_slotCounter_ADDR 11404 +#define D_slotCounter_ADDR_END 11405 +#define D_slotCounter_sizeof 2 +#define D_loopCounter_ADDR 11408 +#define D_loopCounter_ADDR_END 11411 +#define D_loopCounter_sizeof 4 +#define D_RewindFlag_ADDR 11412 +#define D_RewindFlag_ADDR_END 11413 +#define D_RewindFlag_sizeof 2 +#define D_Slot23_ctrl_ADDR 11416 +#define D_Slot23_ctrl_ADDR_END 11419 +#define D_Slot23_ctrl_sizeof 4 +#define D_McuIrqFifo_ADDR 11420 +#define D_McuIrqFifo_ADDR_END 11483 +#define D_McuIrqFifo_sizeof 64 +#define D_PingPongDesc_ADDR 11484 +#define D_PingPongDesc_ADDR_END 11507 +#define D_PingPongDesc_sizeof 24 +#define D_PP_MCU_IRQ_ADDR 11508 +#define D_PP_MCU_IRQ_ADDR_END 11509 +#define D_PP_MCU_IRQ_sizeof 2 +#define D_ctrlPortFifo_ADDR 11520 +#define D_ctrlPortFifo_ADDR_END 11535 +#define D_ctrlPortFifo_sizeof 16 +#define D_Idle_State_ADDR 11536 +#define D_Idle_State_ADDR_END 11539 +#define D_Idle_State_sizeof 4 +#define D_Stop_Request_ADDR 11540 +#define D_Stop_Request_ADDR_END 11543 +#define D_Stop_Request_sizeof 4 +#define D_Ref0_ADDR 11544 +#define D_Ref0_ADDR_END 11545 +#define D_Ref0_sizeof 2 +#define D_DebugRegister_ADDR 11548 +#define D_DebugRegister_ADDR_END 11687 +#define D_DebugRegister_sizeof 140 +#define D_Gcount_ADDR 11688 +#define D_Gcount_ADDR_END 11689 +#define D_Gcount_sizeof 2 +#define D_DCcounter_ADDR 11692 +#define D_DCcounter_ADDR_END 11695 +#define D_DCcounter_sizeof 4 +#define D_DCsum_ADDR 11696 +#define D_DCsum_ADDR_END 11703 +#define D_DCsum_sizeof 8 +#define D_fastCounter_ADDR 11704 +#define D_fastCounter_ADDR_END 11707 +#define D_fastCounter_sizeof 4 +#define D_slowCounter_ADDR 11708 +#define D_slowCounter_ADDR_END 11711 +#define D_slowCounter_sizeof 4 +#define D_aUplinkRouting_ADDR 11712 +#define D_aUplinkRouting_ADDR_END 11743 +#define D_aUplinkRouting_sizeof 32 +#define D_VirtAudioLoop_ADDR 11744 +#define D_VirtAudioLoop_ADDR_END 11747 +#define D_VirtAudioLoop_sizeof 4 +#define D_AsrcVars_DL_VX_ADDR 11748 +#define D_AsrcVars_DL_VX_ADDR_END 11779 +#define D_AsrcVars_DL_VX_sizeof 32 +#define D_AsrcVars_UL_VX_ADDR 11780 +#define D_AsrcVars_UL_VX_ADDR_END 11811 +#define D_AsrcVars_UL_VX_sizeof 32 +#define D_CoefAddresses_VX_ADDR 11812 +#define D_CoefAddresses_VX_ADDR_END 11843 +#define D_CoefAddresses_VX_sizeof 32 +#define D_AsrcVars_MM_EXT_IN_ADDR 11844 +#define D_AsrcVars_MM_EXT_IN_ADDR_END 11875 +#define D_AsrcVars_MM_EXT_IN_sizeof 32 +#define D_CoefAddresses_MM_ADDR 11876 +#define D_CoefAddresses_MM_ADDR_END 11907 +#define D_CoefAddresses_MM_sizeof 32 +#define D_APS_DL1_M_thresholds_ADDR 11908 +#define D_APS_DL1_M_thresholds_ADDR_END 11915 +#define D_APS_DL1_M_thresholds_sizeof 8 +#define D_APS_DL1_M_IRQ_ADDR 11916 +#define D_APS_DL1_M_IRQ_ADDR_END 11917 +#define D_APS_DL1_M_IRQ_sizeof 2 +#define D_APS_DL1_C_IRQ_ADDR 11918 +#define D_APS_DL1_C_IRQ_ADDR_END 11919 +#define D_APS_DL1_C_IRQ_sizeof 2 +#define D_TraceBufAdr_ADDR 11920 +#define D_TraceBufAdr_ADDR_END 11921 +#define D_TraceBufAdr_sizeof 2 +#define D_TraceBufOffset_ADDR 11922 +#define D_TraceBufOffset_ADDR_END 11923 +#define D_TraceBufOffset_sizeof 2 +#define D_TraceBufLength_ADDR 11924 +#define D_TraceBufLength_ADDR_END 11925 +#define D_TraceBufLength_sizeof 2 +#define D_AsrcVars_ECHO_REF_ADDR 11928 +#define D_AsrcVars_ECHO_REF_ADDR_END 11959 +#define D_AsrcVars_ECHO_REF_sizeof 32 +#define D_Pempty_ADDR 11960 +#define D_Pempty_ADDR_END 11963 +#define D_Pempty_sizeof 4 +#define D_APS_DL2_L_M_IRQ_ADDR 11964 +#define D_APS_DL2_L_M_IRQ_ADDR_END 11965 +#define D_APS_DL2_L_M_IRQ_sizeof 2 +#define D_APS_DL2_L_C_IRQ_ADDR 11966 +#define D_APS_DL2_L_C_IRQ_ADDR_END 11967 +#define D_APS_DL2_L_C_IRQ_sizeof 2 +#define D_APS_DL2_R_M_IRQ_ADDR 11968 +#define D_APS_DL2_R_M_IRQ_ADDR_END 11969 +#define D_APS_DL2_R_M_IRQ_sizeof 2 +#define D_APS_DL2_R_C_IRQ_ADDR 11970 +#define D_APS_DL2_R_C_IRQ_ADDR_END 11971 +#define D_APS_DL2_R_C_IRQ_sizeof 2 +#define D_APS_DL1_C_thresholds_ADDR 11972 +#define D_APS_DL1_C_thresholds_ADDR_END 11979 +#define D_APS_DL1_C_thresholds_sizeof 8 +#define D_APS_DL2_L_M_thresholds_ADDR 11980 +#define D_APS_DL2_L_M_thresholds_ADDR_END 11987 +#define D_APS_DL2_L_M_thresholds_sizeof 8 +#define D_APS_DL2_L_C_thresholds_ADDR 11988 +#define D_APS_DL2_L_C_thresholds_ADDR_END 11995 +#define D_APS_DL2_L_C_thresholds_sizeof 8 +#define D_APS_DL2_R_M_thresholds_ADDR 11996 +#define D_APS_DL2_R_M_thresholds_ADDR_END 12003 +#define D_APS_DL2_R_M_thresholds_sizeof 8 +#define D_APS_DL2_R_C_thresholds_ADDR 12004 +#define D_APS_DL2_R_C_thresholds_ADDR_END 12011 +#define D_APS_DL2_R_C_thresholds_sizeof 8 +#define D_ECHO_REF_48_16_WRAP_ADDR 12012 +#define D_ECHO_REF_48_16_WRAP_ADDR_END 12019 +#define D_ECHO_REF_48_16_WRAP_sizeof 8 +#define D_ECHO_REF_48_8_WRAP_ADDR 12020 +#define D_ECHO_REF_48_8_WRAP_ADDR_END 12027 +#define D_ECHO_REF_48_8_WRAP_sizeof 8 +#define D_BT_UL_16_48_WRAP_ADDR 12028 +#define D_BT_UL_16_48_WRAP_ADDR_END 12035 +#define D_BT_UL_16_48_WRAP_sizeof 8 +#define D_BT_UL_8_48_WRAP_ADDR 12036 +#define D_BT_UL_8_48_WRAP_ADDR_END 12043 +#define D_BT_UL_8_48_WRAP_sizeof 8 +#define D_BT_DL_48_16_WRAP_ADDR 12044 +#define D_BT_DL_48_16_WRAP_ADDR_END 12051 +#define D_BT_DL_48_16_WRAP_sizeof 8 +#define D_BT_DL_48_8_WRAP_ADDR 12052 +#define D_BT_DL_48_8_WRAP_ADDR_END 12059 +#define D_BT_DL_48_8_WRAP_sizeof 8 +#define D_VX_DL_16_48_WRAP_ADDR 12060 +#define D_VX_DL_16_48_WRAP_ADDR_END 12067 +#define D_VX_DL_16_48_WRAP_sizeof 8 +#define D_VX_DL_8_48_WRAP_ADDR 12068 +#define D_VX_DL_8_48_WRAP_ADDR_END 12075 +#define D_VX_DL_8_48_WRAP_sizeof 8 +#define D_VX_UL_48_16_WRAP_ADDR 12076 +#define D_VX_UL_48_16_WRAP_ADDR_END 12083 +#define D_VX_UL_48_16_WRAP_sizeof 8 +#define D_VX_UL_48_8_WRAP_ADDR 12084 +#define D_VX_UL_48_8_WRAP_ADDR_END 12091 +#define D_VX_UL_48_8_WRAP_sizeof 8 +#define D_APS_DL1_IRQs_WRAP_ADDR 12092 +#define D_APS_DL1_IRQs_WRAP_ADDR_END 12099 +#define D_APS_DL1_IRQs_WRAP_sizeof 8 +#define D_APS_DL2_L_IRQs_WRAP_ADDR 12100 +#define D_APS_DL2_L_IRQs_WRAP_ADDR_END 12107 +#define D_APS_DL2_L_IRQs_WRAP_sizeof 8 +#define D_APS_DL2_R_IRQs_WRAP_ADDR 12108 +#define D_APS_DL2_R_IRQs_WRAP_ADDR_END 12115 +#define D_APS_DL2_R_IRQs_WRAP_sizeof 8 +#define D_nextMultiFrame_ADDR 12116 +#define D_nextMultiFrame_ADDR_END 12123 +#define D_nextMultiFrame_sizeof 8 +#define D_HW_TEST_ADDR 12124 +#define D_HW_TEST_ADDR_END 12131 +#define D_HW_TEST_sizeof 8 +#define D_TraceBufAdr_HAL_ADDR 12132 +#define D_TraceBufAdr_HAL_ADDR_END 12135 +#define D_TraceBufAdr_HAL_sizeof 4 +#define D_DEBUG_HAL_TASK_ADDR 12288 +#define D_DEBUG_HAL_TASK_ADDR_END 14335 +#define D_DEBUG_HAL_TASK_sizeof 2048 +#define D_DEBUG_FW_TASK_ADDR 14336 +#define D_DEBUG_FW_TASK_ADDR_END 14591 +#define D_DEBUG_FW_TASK_sizeof 256 +#define D_FwMemInit_ADDR 14592 +#define D_FwMemInit_ADDR_END 15551 +#define D_FwMemInit_sizeof 960 +#define D_FwMemInitDescr_ADDR 15552 +#define D_FwMemInitDescr_ADDR_END 15567 +#define D_FwMemInitDescr_sizeof 16 +#define D_AsrcVars_BT_UL_ADDR 15568 +#define D_AsrcVars_BT_UL_ADDR_END 15599 +#define D_AsrcVars_BT_UL_sizeof 32 +#define D_AsrcVars_BT_DL_ADDR 15600 +#define D_AsrcVars_BT_DL_ADDR_END 15631 +#define D_AsrcVars_BT_DL_sizeof 32 +#define D_BT_DL_48_8_OPP100_WRAP_ADDR 15632 +#define D_BT_DL_48_8_OPP100_WRAP_ADDR_END 15639 +#define D_BT_DL_48_8_OPP100_WRAP_sizeof 8 +#define D_BT_DL_48_16_OPP100_WRAP_ADDR 15640 +#define D_BT_DL_48_16_OPP100_WRAP_ADDR_END 15647 +#define D_BT_DL_48_16_OPP100_WRAP_sizeof 8 +#define D_PING_ADDR 16384 +#define D_PING_ADDR_END 40959 +#define D_PING_sizeof 24576 +#define D_PONG_ADDR 40960 +#define D_PONG_ADDR_END 65535 +#define D_PONG_sizeof 24576 +#endif/* _ABEDM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_ext.c b/sound/soc/omap/abe/abe_ext.c new file mode 100644 index 00000000000..21f05d6c4fa --- /dev/null +++ b/sound/soc/omap/abe/abe_ext.c @@ -0,0 +1,228 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +#define ENABLE_DEFAULT_PLAYERS 0 +/** + * abe_default_irq_pingpong_player + * + * generates data for the cache-flush buffer MODE 16+16 + */ +void abe_default_irq_pingpong_player(void) +{ +#if ENABLE_DEFAULT_PLAYERS +#define N_SAMPLES_MAX ((int)(1024)) /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp[N_SAMPLES_MAX], audio_sample; +#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ + const s32 audio_pattern[DATA_SIZE] = { + 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630, + 5063, 0, -5063, -9630, -13254, -15581, -16383, -15581, + -13254, -9630, -5063 + }; +#if 0 +#define DATA_SIZE 8 + const s32 audio_pattern[DATA_SIZE] = { + 0, 11585, 16384, 11585, 0, -11586, -16384, -11586 + }; +#define DATA_SIZE 12 + const s32 audio_pattern[DATA_SIZE] = { + 0, 8191, 14188, 16383, 14188, 8191, 0, + -8192, -14188, -16383, -14188, -8192 + }; + const s32 audio_pattern[8] = { + 16383, 16383, 16383, 16383, -16384, -16384, -16384, -16384 + }; +#endif + /* read the address of the Pong buffer */ + abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + /* each stereo sample weights 4 bytes (format 16|16) */ + n_samples = n_bytes / 4; + /* generate a test pattern */ + for (i = 0; i < n_samples; i++) { + audio_sample = audio_pattern[idx]; + idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1); + /* format 16|16 */ + temp[i] = ((audio_sample << 16) + audio_sample); + } + /* copy the pattern (flush it) to DMEM pointer update + * not necessary here because the buffer size do not + * change from one ping to the other pong + */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, + (u32 *) &(temp[0]), n_bytes); + abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); +#endif +} +/** + * abe_default_irq_pingpong_player_32bits + * + * generates data for the cache-flush buffer MODE 32 BITS + * Return value: + * None. + */ +void abe_default_irq_pingpong_player_32bits(void) +{ +#if ENABLE_DEFAULT_PLAYERS + /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp[N_SAMPLES_MAX], audio_sample; +#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ + const s32 audio_pattern[DATA_SIZE] = { + 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, + 9630, 5063, 0, -5063, -9630, -13254, -15581, -16383, + -15581, -13254, -9630, -5063 + }; + /* read the address of the Pong buffer */ + abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + /* each stereo sample weights 8 bytes (format 32|32) */ + n_samples = n_bytes / 8; + /* generate a test pattern */ + for (i = 0; i < n_samples; i++) { + /* circular addressing */ + audio_sample = audio_pattern[idx]; + idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1); + temp[i * 2 + 0] = (audio_sample << 16); + temp[i * 2 + 1] = (audio_sample << 16); + } + abe_set_ping_pong_buffer(MM_DL_PORT, 0); + /* copy the pattern (flush it) to DMEM pointer update + * not necessary here because the buffer size do not + * change from one ping to the other pong + */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, + (u32 *) &(temp[0]), n_bytes); + abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); +#endif +} +/** + * abe_rshifted16_irq_pingpong_player_32bits + * + * generates data for the cache-flush buffer MODE 32 BITS + * Return value: + * None. + */ +void abe_rshifted16_irq_pingpong_player_32bits(void) +{ +#if ENABLE_DEFAULT_PLAYERS + /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp[N_SAMPLES_MAX], audio_sample; +#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ + const s32 audio_pattern[DATA_SIZE] = { + 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, + 9630, 5063, 0, -5063, -9630, -13254, -15581, -16383, + -15581, -13254, -9630, -5063 + }; + /* read the address of the Pong buffer */ + abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + /* each stereo sample weights 8 bytes (format 32|32) */ + n_samples = n_bytes / 8; + /* generate a test pattern */ + for (i = 0; i < n_samples; i++) { + /* circular addressing */ + audio_sample = audio_pattern[idx]; + idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1); + temp[i * 2 + 0] = audio_sample; + temp[i * 2 + 1] = audio_sample; + } + abe_set_ping_pong_buffer(MM_DL_PORT, 0); + /* copy the pattern (flush it) to DMEM pointer update + * not necessary here because the buffer size do not + * change from one ping to the other pong + */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, + (u32 *) &(temp[0]), n_bytes); + abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); +#endif +} +/** + * abe_1616_irq_pingpong_player_1616bits + * + * generates data for the cache-flush buffer MODE 16+16 BITS + * Return value: + * None. + */ +void abe_1616_irq_pingpong_player_1616bits(void) +{ +#if ENABLE_DEFAULT_PLAYERS + /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp[N_SAMPLES_MAX], audio_sample; +#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ + const s32 audio_pattern[DATA_SIZE] = { + 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, + 9630, 5063, 0, -5063, -9630, -13254, -15581, -16383, + -15581, -13254, -9630, -5063 + }; + /* read the address of the Pong buffer */ + abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + /* each stereo sample weights 4 bytes (format 16+16) */ + n_samples = n_bytes / 4; + /* generate a test pattern */ + for (i = 0; i < n_samples; i++) { + /* circular addressing */ + audio_sample = audio_pattern[idx]; + idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1); + temp[i] = (audio_sample << 16) | (audio_sample & 0x0000FFFF); + } + abe_set_ping_pong_buffer(MM_DL_PORT, 0); + /* copy the pattern (flush it) to DMEM pointer update + * not necessary here because the buffer size do not + * change from one ping to the other pong + */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, + (u32 *) &(temp[0]), n_bytes); + abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); +#endif +} +/** + * abe_default_irq_aps_adaptation + * + * updates the APS filter and gain + */ +void abe_default_irq_aps_adaptation(void) +{ +} +/** + * abe_read_sys_clock + * @time: pointer to the system clock + * + * returns the current time indication for the LOG + */ +void abe_read_sys_clock(u32 *time) +{ + static u32 clock; + *time = clock; + clock++; +} +/** + * abe_aps_tuning + * + * Tune APS parameters + * + */ +void abe_aps_tuning(void) +{ +} diff --git a/sound/soc/omap/abe/abe_ext.h b/sound/soc/omap/abe/abe_ext.h new file mode 100644 index 00000000000..eed6395a9e2 --- /dev/null +++ b/sound/soc/omap/abe/abe_ext.h @@ -0,0 +1,222 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_EXT_H_ +#define _ABE_EXT_H_ +/* Tuning is done on PC ? */ +#define PC_SIMULATION 0 +/* + * OS DEPENDENT MMU CONFIGURATION + */ +#define _lock_enter +#define _lock_exit +#define ABE_PMEM_BASE_OFFSET_MPU 0xe0000 +#define ABE_CMEM_BASE_OFFSET_MPU 0xa0000 +#define ABE_SMEM_BASE_OFFSET_MPU 0xc0000 +#define ABE_DMEM_BASE_OFFSET_MPU 0x80000 +#define ABE_ATC_BASE_OFFSET_MPU 0xf1000 +/* default base address for io_base */ +#define ABE_DEFAULT_BASE_ADDRESS_L3 0x49000000L +/* base address used for L3/DMA access */ +#define ABE_ATC_BASE_ADDRESS_L3 0x490F1000L +/* base address used for L4/MCU access */ +#define ABE_ATC_BASE_ADDRESS_L4 0x401F1000L +/* 64kB as seen from DMA access */ +#define ABE_DMEM_BASE_ADDRESS_L3 0x49080000L +/* 64kB as seen from MCU access */ +#define ABE_DMEM_BASE_ADDRESS_L4 0x40180000L +/* 8kB as seen from MPU access */ +#define ABE_PMEM_BASE_ADDRESS_MPU 0x490E0000L +/* 8kB */ +#define ABE_CMEM_BASE_ADDRESS_MPU 0x490A0000L +/* 24kB */ +#define ABE_SMEM_BASE_ADDRESS_MPU 0x490C0000L +/* 64kB */ +#define ABE_DMEM_BASE_ADDRESS_MPU 0x49080000L +#define ABE_ATC_BASE_ADDRESS_MPU 0x490F1000L +/* + * HARDWARE AND PERIPHERAL DEFINITIONS + */ +/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/ +#define ABE_PMEM_SIZE 8192 +/* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/ +#define ABE_CMEM_SIZE 8192 +/* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/ +#define ABE_SMEM_SIZE 24576 +/* DMEM SIZE in bytes */ +#define ABE_DMEM_SIZE 65536L +/* ATC REGISTERS SIZE in bytes */ +#define ABE_ATC_DESC_SIZE 512 +/* holds the MCU Irq signal */ +#define ABE_MCU_IRQSTATUS_RAW 0x24 +/* status : clear the IRQ */ +#define ABE_MCU_IRQSTATUS 0x28 +/* holds the DSP Irq signal */ +#define ABE_DSP_IRQSTATUS_RAW 0x4C +/* holds the DMA req lines to the sDMA */ +#define ABE_DMASTATUS_RAW 0x84 +#define EVENT_GENERATOR_COUNTER 0x68 +/* PLL output/desired sampling rate = (32768 * 6000)/96000 */ +#define EVENT_GENERATOR_COUNTER_DEFAULT 2048 +/* PLL output/desired sampling rate = (32768 * 6000)/88200 */ +#define EVENT_GENERATOR_COUNTER_44100 2228 +/* start / stop the EVENT generator */ +#define EVENT_GENERATOR_START 0x6C +#define EVENT_GENERATOR_ON 1 +#define EVENT_GENERATOR_OFF 0 +/* selection of the EVENT generator source */ +#define EVENT_SOURCE_SELECTION 0x70 +#define EVENT_SOURCE_DMA 0 +#define EVENT_SOURCE_COUNTER 1 +/* selection of the ABE DMA req line from ATC */ +#define AUDIO_ENGINE_SCHEDULER 0x74 +#define ABE_ATC_DMIC_DMA_REQ 1 +#define ABE_ATC_MCPDMDL_DMA_REQ 2 +#define ABE_ATC_MCPDMUL_DMA_REQ 3 +/* Direction=0 means input from ABE point of view */ +#define ABE_ATC_DIRECTION_IN 0 +/* Direction=1 means output from ABE point of view */ +#define ABE_ATC_DIRECTION_OUT 1 +/* + * DMA requests + */ +/*Internal connection doesn't connect at ABE boundary */ +#define External_DMA_0 0 +/*Transmit request digital microphone */ +#define DMIC_DMA_REQ 1 +/*Multichannel PDM downlink */ +#define McPDM_DMA_DL 2 +/*Multichannel PDM uplink */ +#define McPDM_DMA_UP 3 +/*MCBSP module 1 - transmit request */ +#define MCBSP1_DMA_TX 4 +/*MCBSP module 1 - receive request */ +#define MCBSP1_DMA_RX 5 +/*MCBSP module 2 - transmit request */ +#define MCBSP2_DMA_TX 6 +/*MCBSP module 2 - receive request */ +#define MCBSP2_DMA_RX 7 +/*MCBSP module 3 - transmit request */ +#define MCBSP3_DMA_TX 8 +/*MCBSP module 3 - receive request */ +#define MCBSP3_DMA_RX 9 +/*SLIMBUS module 1 - transmit request channel 0 */ +#define SLIMBUS1_DMA_TX0 10 +/*SLIMBUS module 1 - transmit request channel 1 */ +#define SLIMBUS1_DMA_TX1 11 +/*SLIMBUS module 1 - transmit request channel 2 */ +#define SLIMBUS1_DMA_TX2 12 +/*SLIMBUS module 1 - transmit request channel 3 */ +#define SLIMBUS1_DMA_TX3 13 +/*SLIMBUS module 1 - transmit request channel 4 */ +#define SLIMBUS1_DMA_TX4 14 +/*SLIMBUS module 1 - transmit request channel 5 */ +#define SLIMBUS1_DMA_TX5 15 +/*SLIMBUS module 1 - transmit request channel 6 */ +#define SLIMBUS1_DMA_TX6 16 +/*SLIMBUS module 1 - transmit request channel 7 */ +#define SLIMBUS1_DMA_TX7 17 +/*SLIMBUS module 1 - receive request channel 0 */ +#define SLIMBUS1_DMA_RX0 18 +/*SLIMBUS module 1 - receive request channel 1 */ +#define SLIMBUS1_DMA_RX1 19 +/*SLIMBUS module 1 - receive request channel 2 */ +#define SLIMBUS1_DMA_RX2 20 +/*SLIMBUS module 1 - receive request channel 3 */ +#define SLIMBUS1_DMA_RX3 21 +/*SLIMBUS module 1 - receive request channel 4 */ +#define SLIMBUS1_DMA_RX4 22 +/*SLIMBUS module 1 - receive request channel 5 */ +#define SLIMBUS1_DMA_RX5 23 +/*SLIMBUS module 1 - receive request channel 6 */ +#define SLIMBUS1_DMA_RX6 24 +/*SLIMBUS module 1 - receive request channel 7 */ +#define SLIMBUS1_DMA_RX7 25 +/*McASP - Data transmit DMA request line */ +#define McASP1_AXEVT 26 +/*McASP - Data receive DMA request line */ +#define McASP1_AREVT 29 +/*DUMMY FIFO @@@ */ +#define _DUMMY_FIFO_ 30 +/*DMA of the Circular buffer peripheral 0 */ +#define CBPr_DMA_RTX0 32 +/*DMA of the Circular buffer peripheral 1 */ +#define CBPr_DMA_RTX1 33 +/*DMA of the Circular buffer peripheral 2 */ +#define CBPr_DMA_RTX2 34 +/*DMA of the Circular buffer peripheral 3 */ +#define CBPr_DMA_RTX3 35 +/*DMA of the Circular buffer peripheral 4 */ +#define CBPr_DMA_RTX4 36 +/*DMA of the Circular buffer peripheral 5 */ +#define CBPr_DMA_RTX5 37 +/*DMA of the Circular buffer peripheral 6 */ +#define CBPr_DMA_RTX6 38 +/*DMA of the Circular buffer peripheral 7 */ +#define CBPr_DMA_RTX7 39 +/* + * ATC DESCRIPTORS - DESTINATIONS + */ +#define DEST_DMEM_access 0x00 +#define DEST_MCBSP1_ TX 0x01 +#define DEST_MCBSP2_ TX 0x02 +#define DEST_MCBSP3_TX 0x03 +#define DEST_SLIMBUS1_TX0 0x04 +#define DEST_SLIMBUS1_TX1 0x05 +#define DEST_SLIMBUS1_TX2 0x06 +#define DEST_SLIMBUS1_TX3 0x07 +#define DEST_SLIMBUS1_TX4 0x08 +#define DEST_SLIMBUS1_TX5 0x09 +#define DEST_SLIMBUS1_TX6 0x0A +#define DEST_SLIMBUS1_TX7 0x0B +#define DEST_MCPDM_DL 0x0C +#define DEST_MCASP_TX0 0x0D +#define DEST_MCASP_TX1 0x0E +#define DEST_MCASP_TX2 0x0F +#define DEST_MCASP_TX3 0x10 +#define DEST_EXTPORT0 0x11 +#define DEST_EXTPORT1 0x12 +#define DEST_EXTPORT2 0x13 +#define DEST_EXTPORT3 0x14 +#define DEST_MCPDM_ON 0x15 +#define DEST_CBP_CBPr 0x3F +/* + * ATC DESCRIPTORS - SOURCES + */ +#define SRC_DMEM_access 0x0 +#define SRC_MCBSP1_ RX 0x01 +#define SRC_MCBSP2_RX 0x02 +#define SRC_MCBSP3_RX 0x03 +#define SRC_SLIMBUS1_RX0 0x04 +#define SRC_SLIMBUS1_RX1 0x05 +#define SRC_SLIMBUS1_RX2 0x06 +#define SRC_SLIMBUS1_RX3 0x07 +#define SRC_SLIMBUS1_RX4 0x08 +#define SRC_SLIMBUS1_RX5 0x09 +#define SRC_SLIMBUS1_RX6 0x0A +#define SRC_SLIMBUS1_RX7 0x0B +#define SRC_DMIC_UP 0x0C +#define SRC_MCPDM_UP 0x0D +#define SRC_MCASP_RX0 0x0E +#define SRC_MCASP_RX1 0x0F +#define SRC_MCASP_RX2 0x10 +#define SRC_MCASP_RX3 0x11 +#define SRC_CBP_CBPr 0x3F +#endif/* _ABE_EXT_H_ */ diff --git a/sound/soc/omap/abe/abe_firmware.c b/sound/soc/omap/abe/abe_firmware.c new file mode 100644 index 00000000000..061afac3605 --- /dev/null +++ b/sound/soc/omap/abe/abe_firmware.c @@ -0,0 +1,24119 @@ +0x00009060, /* VERSION NUMBER */ +0x00002000, /* PMEM LENGTH IN BYTES */ +0x000013E0, /* CMEM LENGTH IN BYTES */ +0x00010000, /* DMEM LENGTH IN BYTES */ +0x000044E8, /* SMEM LENGTH IN BYTES */ +0x1600200f, +0x0a000670, +0x08200000, +0x08200000, +0x07800000, +0x1602d1ce, +0x014000e0, +0x014000e1, +0x014000e2, +0x014000e3, +0x014000e4, +0x014000e5, +0x014000e6, +0x014000e7, +0x014000e8, +0x014000e9, +0x014000ea, +0x014000eb, +0x014000ec, +0x014000ed, +0x014000ef, +0x014000ef, +0x144000e4, +0x9e000000, +0x0a200c40, +0x9e000040, +0x0a200c40, +0x9e000080, +0x0a200c40, +0x9e0000c0, +0x0a200c40, +0x9e080000, +0x0a200c40, +0x9e080100, +0x0a200c40, +0x9e080200, +0x0a200c40, +0x9e080300, +0x0a200c40, +0x9e080400, +0x0a200c40, +0x9e080500, +0x0a200c40, +0x9e080600, +0x0a200c40, +0x9e080700, +0x0a200c40, +0x9c050800, +0x0a200c40, +0x16000010, +0x16000001, +0x17000102, +0x01400042, +0x17800103, +0x01400043, +0x98020000, +0x9d0c8118, +0x07800000, +0x9f16001a, +0x9f12021a, +0x9f12031a, +0x9f12051a, +0x98800380, +0x9d0c8118, +0x08200000, +0x9d0c8118, +0x07800000, +0x9f15001a, +0x9f11041a, +0x98800410, +0x9d0c8118, +0x08200000, +0x400002c0, +0x048002ff, +0x000000c5, +0x000004c6, +0x9c028000, +0x400006c7, +0x12000155, +0x013ffefe, +0xc00008c4, +0x1e080000, +0x020005de, +0x00000ac3, +0xdc02b160, +0x04c3ff2d, +0xdc01ba70, +0x128002dd, +0xdc02a440, +0x048fffdd, +0x9c061830, +0x0b200000, +0x003ffefe, +0x000002c4, +0x400004c5, +0x048ffeff, +0x000006c6, +0x000008c7, +0x9d02a040, +0x9d02a950, +0x9d01b260, +0x9d02bc70, +0x08200000, +0x1602c7c6, +0x00000068, +0x16003fc5, +0x01000058, +0x1602c88a, +0x000000a9, +0x16003fc6, +0x00000068, +0x0400089b, +0x4000009c, +0x1602c80e, +0x410000ec, +0x0600000c, +0x1600274d, +0x0a800870, +0x1602e903, +0x00000030, +0x00000231, +0x00000435, +0x04800211, +0x04400511, +0x1602c944, +0x0000004e, +0x0300010e, +0x04800211, +0x04400511, +0x0300010c, +0x04800211, +0x04400511, +0x03000109, +0x01000231, +0x0a200480, +0x04800299, +0x410000a9, +0x05c00b90, +0x4ac00700, +0x04a01085, +0x1602c8c4, +0x40000047, +0x1602c94e, +0x04200599, +0x400000e1, +0x04800177, +0x010000a9, +0x41000047, +0x04a00111, +0x410000e1, +0x06000001, +0x4aa00a50, +0x1602c90d, +0x400000d6, +0x16022e89, +0x400002d7, +0x04800166, +0x410000a9, +0x04900077, +0x010000d6, +0x010002d7, +0x1602c7c6, +0x00000068, +0x16003fc5, +0x01000058, +0x1600c005, +0x1602d141, +0x16000002, +0x40000011, +0x1602d100, +0x9e0e0550, +0xdd140530, +0x160ffff4, +0x41000002, +0x06000001, +0x08400000, +0x01000004, +0x9d140550, +0x0a8006b0, +0x0a000a50, +0x048006ff, +0x013ffafb, +0x013ffcfc, +0x413ffefe, +0x04a0020b, +0x004002bc, +0x0600000c, +0x1600274d, +0x0a800bf0, +0x0a200480, +0x0a000b90, +0x003ffefe, +0x003ffcfc, +0x003ffafb, +0x048ffaff, +0x08200000, +0x07800000, +0x01400040, +0x01400041, +0x01400042, +0x01400043, +0x08200000, +0x16000494, +0x160004a5, +0x160004b6, +0x16000007, +0x9c032040, +0x9c032950, +0x9c033260, +0x9e0f0070, +0x9e0f0170, +0x9e0f0270, +0x9d032040, +0x9d032950, +0x9d033260, +0x08200000, +0x9f158048, +0x07800000, +0x07800000, +0x9d088118, +0x98800d80, +0x08200000, +0x9f158048, +0x9f040040, +0x07800000, +0x9f03fc10, +0x07800000, +0x07800000, +0x07800000, +0x9d188148, +0x98800de0, +0x08200000, +0x9f158048, +0x07800000, +0x07800000, +0x9d188148, +0x9d188108, +0x98800e80, +0x08200000, +0x9f158048, +0x07800000, +0x07800000, +0x9d0e0040, +0x07800000, +0x07800000, +0x9d1e8148, +0x9d1e8108, +0x98800ef0, +0x08200000, +0x9f158018, +0x9f040010, +0x07800000, +0x9f03fc10, +0x07800000, +0x07800000, +0x07800000, +0x9d0e0010, +0x07800000, +0x07800000, +0x9d1e8108, +0x98800f90, +0x08200000, +0x9c080048, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8118, +0x98801060, +0x08200000, +0x9c180028, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8108, +0x988010d0, +0x08200000, +0x9c180068, +0x9c180028, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8148, +0x98801140, +0x08200000, +0x9c1e0048, +0x9c1e0008, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8148, +0x988011c0, +0x08200000, +0x9c1e0008, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8108, +0x98801240, +0x08200000, +0x16000494, +0x160004a5, +0x160004b6, +0x160000bd, +0x9c032340, +0x9c032c50, +0x9c033560, +0x9c180028, +0x9c180068, +0x9f1d0010, +0x9c1800a8, +0x9c1800e8, +0x9f1d00b0, +0x07800000, +0x9d0c8318, +0x9d0c84b8, +0x9c180028, +0x9c180068, +0x9f1d0010, +0x07800000, +0x07800000, +0x9d0c8518, +0x98801320, +0x9d032340, +0x9d032c50, +0x9d033560, +0x08200000, +0x160004f4, +0x16000505, +0x16000516, +0x9c03a440, +0x9c03ad50, +0x9c03b660, +0x160000bd, +0x9f158418, +0x9f1585b8, +0x07800000, +0x9d188108, +0x9d188148, +0x9d188188, +0x9c0c0618, +0x07800000, +0x9d1881c8, +0x9d188108, +0x9d188148, +0x988014d0, +0x9d032440, +0x9d032d50, +0x9d033660, +0x08200000, +0x1600000d, +0x9e0f00d0, +0x00800e0d, +0x9f158038, +0x07800000, +0x04a002dd, +0x9d188108, +0x9f158038, +0x07800000, +0x98801630, +0x9d188108, +0x08200000, +0x9e088100, +0x07800000, +0x07800000, +0x12800277, +0x04c0ff77, +0x04a00174, +0x12800266, +0x04c0ff66, +0x04000645, +0x060ffff4, +0x17000454, +0x12000244, +0x9e0f0140, +0x07800000, +0x07800000, +0x9c0c0118, +0x07800000, +0x07800000, +0x9d0c8118, +0x988017b0, +0x08200000, +0x08200000, +0x08200000, +0x08200000, +0x9c038600, +0x07800000, +0x07800000, +0x9c180770, +0xdc100348, +0x160fff05, +0x9f000810, +0x9f118412, +0x9f001010, +0x9f002810, +0x9c0c00b8, +0x160ffd80, +0x9d0c8410, +0x9f1d8012, +0x9f001810, +0x9f0400d0, +0x9c0c0210, +0x16000204, +0xdd0e00b0, +0x16000005, +0x9f1d80b2, +0x9f0000b0, +0x9f0020b0, +0x9f0400d0, +0x05800560, +0x0a8019d0, +0x9c0c0510, +0x0a0019e0, +0x9c0c0618, +0x16000014, +0x9d0c81e8, +0x9d0c8148, +0x0a801a50, +0x9c0c05b0, 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Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_FUNCTIONSID_H_ +#define _ABE_FUNCTIONSID_H_ +/* + * TASK function ID definitions + */ +#define C_ABE_FW_FUNCTION_IIR 0 +#define C_ABE_FW_FUNCTION_monoToStereoPack 1 +#define C_ABE_FW_FUNCTION_stereoToMonoSplit 2 +#define C_ABE_FW_FUNCTION_decimator 3 +#define C_ABE_FW_FUNCTION_OS0Fill 4 +#define C_ABE_FW_FUNCTION_mixer2 5 +#define C_ABE_FW_FUNCTION_mixer4 6 +#define C_ABE_FW_FUNCTION_inplaceGain 7 +#define C_ABE_FW_FUNCTION_StreamRouting 8 +#define C_ABE_FW_FUNCTION_gainConverge 9 +#define C_ABE_FW_FUNCTION_dualIir 10 +#define C_ABE_FW_FUNCTION_IO_DL_pp 11 +#define C_ABE_FW_FUNCTION_IO_generic 12 +#define C_ABE_FW_FUNCTION_irq_fifo_debug 13 +#define C_ABE_FW_FUNCTION_synchronize_pointers 14 +#define C_ABE_FW_FUNCTION_VIBRA2 15 +#define C_ABE_FW_FUNCTION_VIBRA1 16 +#define C_ABE_FW_FUNCTION_APS_core 17 +#define C_ABE_FW_FUNCTION_IIR_SRC_MIC 18 +#define C_ABE_FW_FUNCTION_wrappers 19 +#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper 20 +#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper 21 +#define C_ABE_FW_FUNCTION_mem_init 22 +#define C_ABE_FW_FUNCTION_debug_vx_asrc 23 +#define C_ABE_FW_FUNCTION_IIR_SRC2 24 +/* + * COPY function ID definitions + */ +#define NULL_COPY_CFPID 0 +#define S2D_STEREO_16_16_CFPID 1 +#define S2D_MONO_MSB_CFPID 2 +#define S2D_STEREO_MSB_CFPID 3 +#define S2D_STEREO_RSHIFTED_16_CFPID 4 +#define S2D_MONO_RSHIFTED_16_CFPID 5 +#define D2S_STEREO_16_16_CFPID 6 +#define D2S_MONO_MSB_CFPID 7 +#define D2S_MONO_RSHIFTED_16_CFPID 8 +#define D2S_STEREO_RSHIFTED_16_CFPID 9 +#define D2S_STEREO_MSB_CFPID 10 +#define COPY_DMIC_CFPID 11 +#define COPY_MCPDM_DL_CFPID 12 +#define COPY_MM_UL_CFPID 13 +#define SPLIT_SMEM_CFPID 14 +#define MERGE_SMEM_CFPID 15 +#define SPLIT_TDM_CFPID 16 +#define MERGE_TDM_CFPID 17 +#define ROUTE_MM_UL_CFPID 18 +#define IO_IP_CFPID 19 +#define COPY_UNDERFLOW_CFPID 20 +#endif/* _ABE_FUNCTIONSID_H_ */ diff --git a/sound/soc/omap/abe/abe_fw.h b/sound/soc/omap/abe/abe_fw.h new file mode 100644 index 00000000000..5691e4e0996 --- /dev/null +++ b/sound/soc/omap/abe/abe_fw.h @@ -0,0 +1,379 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software` + * 02110-1301 USA + */ +#ifndef _ABE_FW_H_ +#define _ABE_FW_H_ +#include "abe_cm_addr.h" +#include "abe_sm_addr.h" +#include "abe_dm_addr.h" +#include "abe_typedef.h" +/* + * GLOBAL DEFINITION + */ +/* one scheduler loop = 4kHz = 12 samples at 48kHz */ +#define FW_SCHED_LOOP_FREQ 4000 +/* one scheduler loop = 4kHz = 12 samples at 48kHz */ +#define FW_SCHED_LOOP_FREQ_DIV1000 (FW_SCHED_LOOP_FREQ/1000) +#define EVENT_FREQUENCY 96000 +#define SLOTS_IN_SCHED_LOOP (96000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_8kHz ( 8000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_16kHz (16000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_24kHz (24000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_48kHz (48000/FW_SCHED_LOOP_FREQ) +#define TASKS_IN_SLOT 8 +/* + * DMEM AREA - SCHEDULER + */ +#define dmem_mm_trace D_DEBUG_FIFO_ADDR +#define dmem_mm_trace_size ((D_DEBUG_FIFO_ADDR_END-D_DEBUG_FIFO_ADDR+1)/4) +#define ATC_SIZE 8 /* 8 bytes per descriptors */ +typedef struct { + unsigned rdpt:7; /* first 32bits word of the descriptor */ + unsigned reserved0:1; + unsigned cbsize:7; + unsigned irqdest:1; + unsigned cberr:1; + unsigned reserved1:5; + unsigned cbdir:1; + unsigned nw:1; + unsigned wrpt:7; + unsigned reserved2:1; + unsigned badd:12; /* second 32bits word of the descriptor */ + unsigned iter:7; /* iteration field overlaps the 16 bits boundary */ + unsigned srcid:6; + unsigned destid:6; + unsigned desen:1; +} abe_satcdescriptor_aess; +/* + * table of scheduler tasks : + * char scheduler_table[24 x 4] : four bytes used at OPP100% + */ +#define dmem_scheduler_table D_multiFrame_ADDR +#define dmem_eanc_task_pointer D_pFastLoopBack_ADDR +/* + * OPP value : + * pointer increment steps in the scheduler table + */ +#define dmem_scheduler_table_step D_taskStep_ADDR +/* + * table of scheduler tasks (max 64) : + * char task_descriptors[64 x 8] : eight bytes per task + * TASK INDEX, INITPTR 1,2,3, INITREG, Loop Counter, Reserved 1,2 + */ +#define dmem_task_descriptor D_tasksList_ADDR +/* + * I/O DESCRIPTORS + */ +#define dmem_port_descriptors D_IOdescr_ADDR +/* ping_pong_t descriptors table + * structure of 8 bytes: + * uint16 base_address1 + * uint16 size1 (16bits address format) + * uint16 base_address2 + * uint16 size2 + * } ping_pong_t + * ping_pong_t dmem_ping_pong_t [8] + */ +/* U8 address */ +#define dmem_ping_pong_buffer D_PING_ADDR +/* + * IRQ mask used with ports with IRQ (DMA or host) + * uint32 dmem_irq_masks [8] + */ +#define dmem_irq_masks D_IRQMask_ADDR +/* + * tables of to the 8 FIFO sequences (delayed commands) holding 12bytes tasks + * in the format + * structure { + * 1) Down counter delay on 16bits, decremented on each scheduler period + * 2) Code on 8 bits for the type of operation to execute : call or data move. + * 3) Three 16bits parameters (for data move example example : source/ + * destination/counter) + * 4) Three bytes reserved + * } seq_fw_task_t + * + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * } FIFO_generic; + * seq_fw_task_t FIFO_CONTENT [8]; 96 bytes + * + * FIFO_SEQ dmem_fifo_sequences [8]; all FIFO sequences + */ +#define dmem_fifo_sequences D_DCFifo_ADDR +#define dmem_fifo_sequences_descriptors D_DCFifoDesc_ADDR +/* + * IRQ FIFOs + * + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 IRQ_CODES [6]; + * } dmem_fifo_irq_mcu; 32 bytes + * } dmem_fifo_irq_dsp; 32 bytes + */ +#define dmem_fifo_irq_mcu_descriptor D_McuIrqFifoDesc_ADDR +#define dmem_fifo_irq_dsp_descriptor D_DspIrqFifoDesc_ADDR +#define dmem_fifo_irq_mcu D_McuIrqFifo_ADDR +#define dmem_fifo_irq_dsp D_DspIrqFifo_ADDR +/* + * remote debugger exchange buffer + * uint32 dmem_debug_ae2hal [32] + * uint32 dmem_debug_hal2ae [32] + */ +#define dmem_debug_ae2hal D_DebugAbe2hal_ADDR +#define dmem_debug_hal2ae D_Debug_hal2abe_ADDR +/* + * DMEM address of the ASRC ppm drift parameter for ASRCs (voice and multimedia + * paths) + * uint32 smem_asrc(x)_drift + */ +#define dmem_asrc1_drift D_ASRC1drift_ADDR +#define dmem_asrc2_drift D_ASRC2drift_ADDR +/* + * DMEM indexes of the router uplink paths + * uint8 dmem_router_index [8] + */ +// OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +//#define dmem_router_index +/* + * analog control circular buffer commands to Phoenix + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [6]; + * } dmem_commands_to_phoenix; 32 bytes + */ +#define dmem_commands_to_phoenix D_Cmd2PhenixFifo_ADDR +#define dmem_commands_to_phoenix_descriptor D_Cmd2PhenixFifoDesc_ADDR +/* + * analog control circular buffer commands from Phoenix (status line) + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [6]; + * } dmem_commands_to_phoenix; 32 bytes + */ +#define dmem_commands_from_phoenix D_StatusFromPhenixFifo_ADDR +#define dmem_commands_from_phoenix_descriptor D_StatusFromPhenixFifoDesc_ADDR +/* + * DEBUG mask + * uint16 dmem_debug_trace_mask + * each bit of this word enables a type a trace in the debug circular buffer + */ +// OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +//#define dmem_debug_trace_mask +/* + * DEBUG circular buffer + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [14]; = TIMESTAMP + CODE + * } dmem_debug_trace_buffer; 64 bytes + * should be much larger (depends on the DMEM mapping...) + */ +#define dmem_debug_trace_buffer +#define dmem_debug_trace_fifo D_debugFifo_ADDR +#define dmem_debug_trace_descriptor D_debugFifoDesc_ADDR +/* + * Infinite counter incremented on each sheduler periods (~250 us) + * uint16 dmem_debug_time_stamp + */ +#define dmem_debug_time_stamp D_loopCounter_ADDR +/* + * ATC BUFFERS + IO TASKS SMEM buffers + */ +#define dmem_dmic D_DMIC_UL_FIFO_ADDR +#define dmem_dmic_size (D_DMIC_UL_FIFO_sizeof/4) +#define dmem_amic D_McPDM_UL_FIFO_ADDR +#define dmem_amic_size (D_McPDM_UL_FIFO_sizeof/4) +#define smem_amic AMIC_96_labelID +#define dmem_mcpdm D_McPDM_DL_FIFO_ADDR +#define dmem_mcpdm_size (D_McPDM_DL_FIFO_sizeof/4) +#define dmem_mm_ul D_MM_UL_FIFO_ADDR +#define dmem_mm_ul_size (D_MM_UL_FIFO_sizeof/4) +/* managed directly by the router */ +#define smem_mm_ul MM_UL_labelID +#define dmem_mm_ul2 D_MM_UL2_FIFO_ADDR +#define dmem_mm_ul2_size (D_MM_UL2_FIFO_sizeof/4) +/* managed directly by the router */ +#define smem_mm_ul2 MM_UL2_labelID +#define dmem_mm_dl D_MM_DL_FIFO_ADDR +#define dmem_mm_dl_size (D_MM_DL_FIFO_sizeof/4) +#define smem_mm_dl MM_DL_labelID +#define dmem_vx_dl D_VX_DL_FIFO_ADDR +#define dmem_vx_dl_size (D_VX_DL_FIFO_sizeof/4) +#define smem_vx_dl IO_VX_DL_ASRC_labelID /* Voice_16k_DL_labelID */ +#define dmem_vx_ul D_VX_UL_FIFO_ADDR +#define dmem_vx_ul_size (D_VX_UL_FIFO_sizeof/4) +#define smem_vx_ul Voice_8k_UL_labelID +#define dmem_tones_dl D_TONES_DL_FIFO_ADDR +#define dmem_tones_dl_size (D_TONES_DL_FIFO_sizeof/4) +#define smem_tones_dl Tones_labelID +#define dmem_vib_dl D_VIB_DL_FIFO_ADDR +#define dmem_vib_dl_size (D_VIB_DL_FIFO_sizeof/4) +#define smem_vib IO_VIBRA_DL_labelID +#define dmem_mm_ext_out D_MM_EXT_OUT_FIFO_ADDR +#define dmem_mm_ext_out_size (D_MM_EXT_OUT_FIFO_sizeof/4) +#define smem_mm_ext_out DL1_GAIN_out_labelID +#define dmem_mm_ext_in D_MM_EXT_IN_FIFO_ADDR +#define dmem_mm_ext_in_size (D_MM_EXT_IN_FIFO_sizeof/4) +/*IO_MM_EXT_IN_ASRC_labelID ASRC input buffer, size 40 */ +#define smem_mm_ext_in_opp100 IO_MM_EXT_IN_ASRC_labelID +/* at OPP 50 without ASRC */ +#define smem_mm_ext_in_opp50 MM_EXT_IN_labelID +#define dmem_bt_vx_dl D_BT_DL_FIFO_ADDR +#define dmem_bt_vx_dl_size (D_BT_DL_FIFO_sizeof/4) +#define smem_bt_vx_dl_opp50 BT_DL_8k_labelID +/*BT_DL_8k_opp100_labelID ASRC output buffer, size 40 */ +#define smem_bt_vx_dl_opp100 BT_DL_8k_opp100_labelID +#define dmem_bt_vx_ul D_BT_UL_FIFO_ADDR +#define dmem_bt_vx_ul_size (D_BT_UL_FIFO_sizeof/4) +#define smem_bt_vx_ul_opp50 BT_UL_8k_labelID +/*IO_BT_UL_ASRC_labelID ASRC input buffer, size 40 */ +#define smem_bt_vx_ul_opp100 IO_BT_UL_ASRC_labelID +/* + * INITPTR / INITREG AREA + */ +/* + * POINTER - used for the port descriptor programming + * corresponds to 8bits addresses to the INITPTR area + * + * List from ABE_INITxxx_labels.h + */ +#define ptr_ul_rec +#define ptr_vx_dl +#define ptr_mm_dl +#define ptr_mm_ext +#define ptr_tones +#define ptr_vibra2 +/* + * SMEM AREA + */ +/* + * PHOENIX OFFSET in SMEM + * used to subtract a DC offset on the headset path (power consumption optimization) + */ +/* OC: exact usage to be detailled */ +#define smem_phoenix_offset S_PhoenixOffset_ADDR +/* + * EQUALIZERS Z AREA + * used to reset the filter memory - IIR-8 (max) + * int24 stereo smem_equ(x) [8x2 + 1] + */ +#define smem_equ1 S_EQU1_data_ADDR +#define smem_equ2 S_EQU2_data_ADDR +#define smem_equ3 S_EQU3_data_ADDR +#define smem_equ4 S_EQU4_data_ADDR +#define smem_sdt S_SDT_data_ADDR +/* + * GAIN SMEM on PORT + * int32 smem_G0 [18] : desired gain on the ports + * format of G0 = 6 bits left shifted desired gain in linear 24bits format + * int24 stereo G0 [18] = G0 + * int24 stereo GI [18] current value of the gain in the same format of G0 + * List of smoothed gains : + * 6 DMIC 0 1 2 3 4 5 + * 2 AMIC L R + * 4 PORT1/2_RX L R + * 2 MM_EXT L R + * 2 MM_VX_DL L R + * 2 IHF L R + * --------------- + * 18 = TOTAL + */ +#if 0 +#define smem_g0 S_GTarget_ADDR // [9] 2 gains in 1 SM address +#define smem_g1 S_GCurrent_ADDR // [9] 2 gains in 1 SM address +#endif +/* + * COEFFICIENTS AREA + */ +/* + * delay coefficients used in the IIR-1 filters + * int24 cmem_gain_delay_iir1[9 x 2] (a, (1-a)) + * + * 3 for 6 DMIC 0 1 2 3 4 5 + * 1 for 2 AMIC L R + * 2 for 4 PORT1/2_RX L R + * 1 for 2 MM_EXT L R + * 1 for 2 MM_VX_DL L R + * 1 for 2 IHF L R + */ +#define cmem_gain_alpha C_Alpha_ADDR +#define cmem_gain_1_alpha C_1_Alpha_ADDR +/* + * gain controls + */ +#define GAIN_LEFT_OFFSET 0 +#define GAIN_RIGHT_OFFSET 1 +/* stereo gains */ +#define dmic1_gains_offset 0 +#define dmic2_gains_offset 2 +#define dmic3_gains_offset 4 +#define amic_gains_offset 6 +#define dl1_gains_offset 8 +#define dl2_gains_offset 10 +#define splitters_gains_offset 12 +#define mixer_dl1_offset 14 +#define mixer_dl2_offset 18 +#define mixer_echo_offset 22 +#define mixer_sdt_offset 24 +#define mixer_vxrec_offset 26 +#define mixer_audul_offset 30 +#define gain_unused_offset 34 +/* + * DMIC SRC 96->48 + * the filter is changed depending on the decimatio ratio used (16/25/32/40) + * int32 cmem_src2_dmic [6] IIR with 2 coefs in the recursive part and 4 coefs + * in the direct part + */ +#define cmem_src2_dmic +/* + * EANC coefficients + * structure of : + * 20 Q6.26 coef for the FIR + * 16 Q6.26 coef for the IIR + * 1 Q6.26 coef for Lambda + */ +#define cmem_eanc_coef_fir +#define cmem_eanc_coef_iir +#define cmem_eanc_coef_lambda +/* + * EQUALIZERS - SDT - COEF AREA + * int24 cmem_equ(x) [8x2+1] + */ +#define cmem_equ1 C_EQU1_data_ADDR +#define cmem_equ2 C_EQU2_data_ADDR +#define cmem_equ3 C_EQU3_data_ADDR +#define cmem_equ4 C_EQU4_data_ADDR +#define cmem_sdt C_SDT_data_ADDR +/* + * APS - COEF AREA + * int24 cmem_aps(x) [16] + */ +#define cmem_aps1 +#define cmem_aps2 +#define cmem_aps3 +/* + * DITHER - COEF AREA + * int24 cmem_dither(x) [4] + */ +#define cmem_dither +#endif /* _ABE_FW_H_ */ diff --git a/sound/soc/omap/abe/abe_ini.c b/sound/soc/omap/abe/abe_ini.c new file mode 100644 index 00000000000..c193393568b --- /dev/null +++ b/sound/soc/omap/abe/abe_ini.c @@ -0,0 +1,2279 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +#include "abe_dm_addr.h" +/* + * initialize the default values for call-backs to subroutines + * - FIFO IRQ call-backs for sequenced tasks + * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols) + * - Remote debugger interface + * - Error monitoring + * - Activity Tracing + */ +/** + * abe_hw_configuration + * + */ +void abe_hw_configuration() +{ + u32 atc_reg; + /* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */ + atc_reg = 0xFF; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4); + /* enables the MCU IRQ from AESS to Cortex A9 */ + atc_reg = 0x01; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x3C, &atc_reg, 4); +} +/** + * abe_build_scheduler_table + * + */ +void abe_build_scheduler_table() +{ + u16 i, n; + u8 *ptr; + char aUplinkMuxing[16]; +#define ABE_TASK_ID(ID) (D_tasksList_ADDR + sizeof(ABE_STask)*(ID)) + /* LOAD OF THE TASKS' MULTIFRAME */ + /* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED + IN "abe_init_io_tasks" */ + for (ptr = (u8 *) &(MultiFrame[0][0]), i = 0; + i < sizeof(MultiFrame); i++) + *ptr++ = 0; + /* MultiFrame[0][0] = 0; */ + /* MultiFrame[0][1] = 0; */ + MultiFrame[0][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_DL); + /* MultiFrame[0][3] = 0; */ + /* MultiFrame[0][4] = 0; */ + /* MultiFrame[0][5] = 0; */ + /* MultiFrame[0][6] = 0; */ + /* MultiFrame[0][7] = 0; */ + /* MultiFrame[1][0] = 0; */ + /* MultiFrame[1][1] = 0; */ +#define TASK_ASRC_VX_DL_SLT 1 +#define TASK_ASRC_VX_DL_IDX 2 + MultiFrame[1][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8); +#define TASK_VX_DL_SLT 1 +#define TASK_VX_DL_IDX 3 + MultiFrame[1][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48); + /* MultiFrame[1][4] = 0; */ + /* MultiFrame[1][5] = 0; */ + MultiFrame[1][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2Mixer); + MultiFrame[1][7] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VIB_DL); + MultiFrame[2][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1Mixer); + MultiFrame[2][1] = ABE_TASK_ID(C_ABE_FW_TASK_SDTMixer); + /* MultiFrame[2][2] = 0; */ + /* MultiFrame[2][3] = 0; */ + /* MultiFrame[2][4] = 0; */ + MultiFrame[2][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC); + /* MultiFrame[2][6] = 0; */ + /* MultiFrame[2][7] = 0; */ + MultiFrame[3][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_GAIN); + /* MultiFrame[3][1] = 0; */ + /* MultiFrame[3][2] = 0; */ + /* MultiFrame[3][3] = 0; */ + /* MultiFrame[3][4] = 0; */ + /* MultiFrame[3][5] = 0; */ + MultiFrame[3][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_GAIN); + MultiFrame[3][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_EQ); + MultiFrame[4][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_EQ); + /* MultiFrame[4][1] = 0; */ + MultiFrame[4][2] = ABE_TASK_ID(C_ABE_FW_TASK_VXRECMixer); + MultiFrame[4][3] = ABE_TASK_ID(C_ABE_FW_TASK_VXREC_SPLIT); + /* MultiFrame[4][4] = 0; */ + /* MultiFrame[4][5] = 0; */ + MultiFrame[4][6] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA1); + MultiFrame[4][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA2); + MultiFrame[5][0] = 0; + MultiFrame[5][1] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP); + MultiFrame[5][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_UL); + /* MultiFrame[5][3] = 0; */ + /* MultiFrame[5][4] = 0; */ + /* MultiFrame[5][5] = 0; */ + /* MultiFrame[5][6] = 0; */ + MultiFrame[5][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_SPLIT); + MultiFrame[6][0] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP); + /* MultiFrame[6][1] = 0; */ + /* MultiFrame[6][2] = 0; */ + /* MultiFrame[6][3] = 0; */ + /* MultiFrame[6][4] = 0; */ + MultiFrame[6][5] = ABE_TASK_ID(C_ABE_FW_TASK_EchoMixer); + /* MultiFrame[6][6] = 0; */ + /* MultiFrame[6][7] = 0; */ + MultiFrame[7][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL); + /* MultiFrame[7][1] = 0; */ + MultiFrame[7][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_SPLIT); + MultiFrame[7][3] = ABE_TASK_ID(C_ABE_FW_TASK_DBG_SYNC); + /* MultiFrame[7][4] = 0; */ + MultiFrame[7][5] = ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_SPLIT); + /* MultiFrame[7][6] = 0; */ + /* MultiFrame[7][7] = 0; */ + /* MultiFrame[8][0] = 0; */ + /* MultiFrame[8][1] = 0; */ + MultiFrame[8][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_96_48_LP); + /* MultiFrame[8][3] = 0; */ + MultiFrame[8][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_SPLIT); + /* MultiFrame[8][5] = 0; */ + /* MultiFrame[8][6] = 0; */ + /* MultiFrame[8][7] = 0; */ + /* MultiFrame[9][0] = 0; */ + /* MultiFrame[9][1] = 0; */ + MultiFrame[9][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_96_48_LP); + /* MultiFrame[9][3] = 0; */ + MultiFrame[9][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_SPLIT); + /* MultiFrame[9][5] = 0; */ + MultiFrame[9][6] = 0; + MultiFrame[9][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP); + /* MultiFrame[10][0] = 0; */ + /* MultiFrame[10][1] = 0; */ + MultiFrame[10][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_96_48_LP); + /* MultiFrame[10][3] = 0; */ + MultiFrame[10][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_SPLIT); + /* MultiFrame[10][5] = 0; */ + /* MultiFrame[10][6] = 0; */ + MultiFrame[10][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP); + /* MultiFrame[11][0] = 0; */ + /* MultiFrame[11][1] = 0; */ + MultiFrame[11][2] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_96_48_LP); + /* MultiFrame[11][3] = 0; */ + MultiFrame[11][4] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_SPLIT); + /* MultiFrame[11][5] = 0; */ + /* MultiFrame[11][6] = 0; */ + MultiFrame[11][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_PACK); + /* MultiFrame[12][0] = 0; */ + /* MultiFrame[12][1] = 0; */ + /* MultiFrame[12][2] = 0; */ + MultiFrame[12][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_ROUTING); + MultiFrame[12][4] = ABE_TASK_ID(C_ABE_FW_TASK_ULMixer); +#define TASK_VX_UL_SLT 12 +#define TASK_VX_UL_IDX 5 + MultiFrame[12][5] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8); + /* MultiFrame[12][6] = 0; */ + /* MultiFrame[12][7] = 0; */ + /* MultiFrame[13][0] = 0; */ + /* MultiFrame[13][1] = 0; */ + MultiFrame[13][2] = ABE_TASK_ID(C_ABE_FW_TASK_MM_UL2_ROUTING); + MultiFrame[13][3] = ABE_TASK_ID(C_ABE_FW_TASK_SideTone); + /* MultiFrame[13][4] = 0; */ + MultiFrame[13][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_DL); + /* MultiFrame[13][6] = 0; */ + /* MultiFrame[13][7] = 0; */ + /* MultiFrame[14][0] = 0; */ + /* MultiFrame[14][1] = 0; */ + /* MultiFrame[14][2] = 0; */ + MultiFrame[14][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC); +#define TASK_BT_DL_48_8_SLT 14 +#define TASK_BT_DL_48_8_IDX 4 + MultiFrame[14][4] = ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_8); + /* MultiFrame[14][5] = 0; */ + /* MultiFrame[14][6] = 0; */ + /* MultiFrame[14][7] = 0; */ +#define TASK_ASRC_BT_UL_SLT 15 +#define TASK_ASRC_BT_UL_IDX 6 + MultiFrame[15][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_OUT); + /* MultiFrame[15][1] = 0; */ + /* MultiFrame[15][2] = 0; */ + MultiFrame[15][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_UL); + /* MultiFrame[15][4] = 0; */ + /* MultiFrame[15][5] = 0; */ + MultiFrame[15][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_UL_8); + /* MultiFrame[15][7] = 0; */ + /* MultiFrame[16][0] = 0; */ + /* MultiFrame[16][1] = 0; */ +#define TASK_ASRC_VX_UL_SLT 16 +#define TASK_ASRC_VX_UL_IDX 2 + MultiFrame[16][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8); + MultiFrame[16][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_UL); + /* MultiFrame[16][4] = 0; */ + /* MultiFrame[16][5] = 0; */ + /* MultiFrame[16][6] = 0; */ + /* MultiFrame[16][7] = 0; */ + /* MultiFrame[17][0] = 0; */ + /* MultiFrame[17][1] = 0; */ +#define TASK_BT_UL_8_48_SLT 17 +#define TASK_BT_UL_8_48_IDX 2 + MultiFrame[17][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48); + MultiFrame[17][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL2); + /* MultiFrame[17][4] = 0; */ + /* MultiFrame[17][5] = 0; */ + /* MultiFrame[17][6] = 0; */ + /* MultiFrame[17][7] = 0; */ +#define TASK_IO_MM_DL_SLT 18 +#define TASK_IO_MM_DL_IDX 0 + MultiFrame[18][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL); + /* MultiFrame[18][1] = 0; */ + /* MultiFrame[18][2] = 0; */ + /* MultiFrame[18][3] = 0; */ + /* MultiFrame[18][4] = 0; */ + /* MultiFrame[18][5] = 0; */ +#define TASK_ASRC_BT_DL_SLT 18 +#define TASK_ASRC_BT_DL_IDX 6 + MultiFrame[18][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_DL_8); + /* MultiFrame[18][7] = 0; */ + MultiFrame[19][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL); + /* MultiFrame[19][1] = 0 */ + /* MultiFrame[19][2] = 0; */ + /* MultiFrame[19][3] = 0; */ + /* MultiFrame[19][4] = 0; */ + /* MultiFrame[19][5] = 0; */ + /* MM_UL is moved to OPP 100% */ + MultiFrame[19][6] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL); + /* MultiFrame[19][7] = 0; */ + MultiFrame[20][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_TONES_DL); + /* MultiFrame[20][1] = 0; */ + /* MultiFrame[20][2] = 0; */ + /* MultiFrame[20][3] = 0; */ + /* MultiFrame[20][4] = 0; */ + /* MultiFrame[20][5] = 0; */ + MultiFrame[20][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_MM_EXT_IN); + /* MultiFrame[20][7] = 0; */ + /* MultiFrame[21][0] = 0; */ + MultiFrame[21][1] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs); + /* MultiFrame[21][2] = 0; */ + MultiFrame[21][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN); + /* MultiFrame[21][4] = 0; */ + /* MultiFrame[21][5] = 0; */ + /* MultiFrame[21][6] = 0; */ + /* MultiFrame[21][7] = 0; */ + /* MUST STAY ON SLOT 22 */ + MultiFrame[22][0] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUG_IRQFIFO); + MultiFrame[22][1] = ABE_TASK_ID(C_ABE_FW_TASK_INIT_FW_MEMORY); + MultiFrame[22][2] = 0; + /* MultiFrame[22][3] = 0; */ + /* MM_EXT_IN_SPLIT task must be after IO_MM_EXT_IN and before + ASRC_MM_EXT_IN in order to manage OPP50 <-> transitions */ + MultiFrame[22][4] = ABE_TASK_ID(C_ABE_FW_TASK_MM_EXT_IN_SPLIT); + /* MultiFrame[22][5] = 0; */ + /* MultiFrame[22][6] = 0; */ + /* MultiFrame[22][7] = 0; */ + MultiFrame[23][0] = ABE_TASK_ID(C_ABE_FW_TASK_GAIN_UPDATE); + /* MultiFrame[23][1] = 0; */ + /* MultiFrame[23][2] = 0; */ + /* MultiFrame[23][3] = 0; */ + /* MultiFrame[23][4] = 0; */ + /* MultiFrame[23][5] = 0; */ + /* MultiFrame[23][6] = 0; */ + /* MultiFrame[23][7] = 0; */ + /* MultiFrame[24][0] = 0; */ + /* MultiFrame[24][1] = 0; */ + /* MultiFrame[24][2] = 0; */ + /* MultiFrame[24][3] = 0; */ + /* MultiFrame[24][4] = 0; */ + /* MultiFrame[24][5] = 0; */ + /* MultiFrame[24][6] = 0; */ + /* MultiFrame[24][7] = 0; */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, + (u32 *) MultiFrame, sizeof(MultiFrame)); + /* reset the uplink router */ + n = (D_aUplinkRouting_sizeof) >> 1; + for (i = 0; i < n; i++) + aUplinkMuxing[i] = ZERO_labelID; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, + (u32 *) aUplinkMuxing, sizeof(aUplinkMuxing)); +} +/** + * abe_init_atc + * @id: ABE port ID + * + * load the DMEM ATC/AESS descriptors + */ +void abe_init_atc(u32 id) +{ + u8 iter; + s32 datasize; +#define JITTER_MARGIN 4 + /* load default values of the descriptor */ + atc_desc.rdpt = atc_desc.wrpt = atc_desc.irqdest = atc_desc.cberr = 0; + atc_desc.desen = atc_desc.nw = 0; + atc_desc.reserved0 = atc_desc.reserved1 = atc_desc.reserved2 = 0; + atc_desc.srcid = atc_desc.destid = atc_desc.badd = atc_desc.iter = + atc_desc.cbsize = 0; + datasize = abe_dma_port_iter_factor(&((abe_port[id]).format)); + iter = (u8) abe_dma_port_iteration(&((abe_port[id]).format)); + /* if the ATC FIFO is too small there will be two ABE firmware + utasks to do the copy this happems on DMIC and MCPDMDL */ + /* VXDL_8kMono = 4 = 2 + 2x1 */ + /* VXDL_16kstereo = 12 = 8 + 2x2 */ + /* MM_DL_1616 = 14 = 12 + 2x1 */ + /* DMIC = 84 = 72 + 2x6 */ + /* VXUL_8kMono = 2 */ + /* VXUL_16kstereo = 4 */ + /* MM_UL2_Stereo = 4 */ + /* PDMDL = 12 */ + /* IN from AESS point of view */ + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) + if (iter + 2 * datasize > 126) + atc_desc.wrpt = + (iter >> 1) + ((JITTER_MARGIN - 1) * datasize); + else + atc_desc.wrpt = iter + ((JITTER_MARGIN - 1) * datasize); + else + atc_desc.wrpt = 0 + ((JITTER_MARGIN + 1) * datasize); + switch ((abe_port[id]).protocol.protocol_switch) { + case SLIMBUS_PORT_PROT: + atc_desc.cbdir = (abe_port[id]).protocol.direction; + atc_desc.cbsize = + (abe_port[id]).protocol.p.prot_slimbus.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4; + atc_desc.iter = (abe_port[id]).protocol.p.prot_slimbus.iter; + atc_desc.srcid = + abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus. + desc_addr1 >> 3]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_slimbus. + desc_addr1, (u32 *) &atc_desc, + sizeof(atc_desc)); + atc_desc.badd = + (abe_port[id]).protocol.p.prot_slimbus.buf_addr2; + atc_desc.srcid = + abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus. + desc_addr2 >> 3]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_slimbus. + desc_addr2, (u32 *) &atc_desc, + sizeof(atc_desc)); + break; + case SERIAL_PORT_PROT: + atc_desc.cbdir = (abe_port[id]).protocol.direction; + atc_desc.cbsize = + (abe_port[id]).protocol.p.prot_serial.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4; + atc_desc.iter = (abe_port[id]).protocol.p.prot_serial.iter; + atc_desc.srcid = + abe_atc_srcid[(abe_port[id]).protocol.p.prot_serial. + desc_addr >> 3]; + atc_desc.destid = + abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial. + desc_addr >> 3]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_serial.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); + break; + case DMIC_PORT_PROT: + atc_desc.cbdir = ABE_ATC_DIRECTION_IN; + atc_desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4; + atc_desc.iter = DMIC_ITER; + atc_desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE), + (u32 *) &atc_desc, sizeof(atc_desc)); + break; + case MCPDMDL_PORT_PROT: + atc_desc.cbdir = ABE_ATC_DIRECTION_OUT; + atc_desc.cbsize = + (abe_port[id]).protocol.p.prot_mcpdmdl.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4; + atc_desc.iter = MCPDM_DL_ITER; + atc_desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE), + (u32 *) &atc_desc, sizeof(atc_desc)); + break; + case MCPDMUL_PORT_PROT: + atc_desc.cbdir = ABE_ATC_DIRECTION_IN; + atc_desc.cbsize = + (abe_port[id]).protocol.p.prot_mcpdmul.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4; + atc_desc.iter = MCPDM_UL_ITER; + atc_desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ]; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE), + (u32 *) &atc_desc, sizeof(atc_desc)); + break; + case PINGPONG_PORT_PROT: + /* software protocol, nothing to do on ATC */ + break; + case DMAREQ_PORT_PROT: + atc_desc.cbdir = (abe_port[id]).protocol.direction; + atc_desc.cbsize = + (abe_port[id]).protocol.p.prot_dmareq.buf_size; + atc_desc.badd = + ((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4; + /* CBPr needs ITER=1. this is the eDMA job to do the iterations */ + atc_desc.iter = 1; + /* input from ABE point of view */ + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) { + /* atc_atc_desc.rdpt = 127; */ + /* atc_atc_desc.wrpt = 0; */ + atc_desc.srcid = abe_atc_srcid + [(abe_port[id]).protocol.p.prot_dmareq. + desc_addr >> 3]; + } else { + /* atc_atc_desc.rdpt = 0; */ + /* atc_atc_desc.wrpt = 127; */ + atc_desc.destid = abe_atc_dstid + [(abe_port[id]).protocol.p.prot_dmareq. + desc_addr >> 3]; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); + break; + } +} +/** + * abe_init_dma_t + * @ id: ABE port ID + * @ prot: protocol being used + * + * load the dma_t with physical information from AE memory mapping + */ +void abe_init_dma_t(u32 id, abe_port_protocol_t *prot) +{ + abe_dma_t_offset dma; + u32 idx; + /* default dma_t points to address 0000... */ + dma.data = 0; + dma.iter = 0; + switch (prot->protocol_switch) { + case PINGPONG_PORT_PROT: + for (idx = 0; idx < 32; idx++) { + if (((prot->p).prot_pingpong.irq_data) == + (u32) (1 << idx)) + break; + } + (prot->p).prot_dmareq.desc_addr = + ((CBPr_DMA_RTX0 + idx)*ATC_SIZE); + /* translate byte address/size in DMEM words */ + dma.data = (prot->p).prot_pingpong.buf_addr >> 2; + dma.iter = (prot->p).prot_pingpong.buf_size >> 2; + break; + case DMAREQ_PORT_PROT: + for (idx = 0; idx < 32; idx++) { + if (((prot->p).prot_dmareq.dma_data) == + (u32) (1 << idx)) + break; + } + dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + (idx << 2)); + dma.iter = (prot->p).prot_dmareq.iter; + (prot->p).prot_dmareq.desc_addr = + ((CBPr_DMA_RTX0 + idx)*ATC_SIZE); + break; + case SLIMBUS_PORT_PROT: + case SERIAL_PORT_PROT: + case DMIC_PORT_PROT: + case MCPDMDL_PORT_PROT: + case MCPDMUL_PORT_PROT: + default: + break; + } + /* upload the dma type */ + abe_port[id].dma = dma; +} +/** + * abe_disenable_dma_request + * Parameter: + * Operations: + * Return value: + */ +void abe_disable_enable_dma_request(u32 id, u32 on_off) +{ + u8 desc_third_word[4], irq_dmareq_field; + u32 sio_desc_address; + u32 struct_offset; + if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) { + irq_dmareq_field = + (u8) (on_off * + abe_port[id].protocol.p.prot_pingpong.irq_data); + sio_desc_address = D_PingPongDesc_ADDR; + struct_offset = (u32) &(desc_pp.data_size) - (u32) &(desc_pp); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_desc_address + struct_offset, + (u32 *) desc_third_word, 4); + desc_third_word[2] = irq_dmareq_field; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address + struct_offset, + (u32 *) desc_third_word, 4); + } else { + /* serial interface: sync ATC with Firmware activity */ + sio_desc_address = + dmem_port_descriptors + + (id * sizeof(ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_desc_address, (u32 *) &sio_desc, + sizeof(sio_desc)); + if (on_off) { + sio_desc.atc_irq_data = + (u8) abe_port[id].protocol.p.prot_dmareq. + dma_data; + sio_desc.on_off = 0x80; + } else { + sio_desc.atc_irq_data = 0; + sio_desc.on_off = 0; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address, (u32 *) &sio_desc, + sizeof(sio_desc)); + } +} +void abe_enable_dma_request(u32 id) +{ + abe_disable_enable_dma_request(id, 1); +} +/** + * abe_disable_dma_request + * + * Parameter: + * Operations: + * Return value: + * + */ +void abe_disable_dma_request(u32 id) +{ + abe_disable_enable_dma_request(id, 0); +} +/** + * abe_enable_atc + * Parameter: + * Operations: + * Return value: + */ +void abe_enable_atc(u32 id) +{ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); + atc_desc.desen = 1; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); +} +/** + * abe_disable_atc + * Parameter: + * Operations: + * Return value: + */ +void abe_disable_atc(u32 id) +{ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); + atc_desc.desen = 0; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32 *) &atc_desc, sizeof(atc_desc)); +} +/** + * abe_init_io_tasks + * @prot : protocol being used + * + * load the micro-task parameters doing to DMEM <==> SMEM data moves + * + * I/O descriptors input parameters : + * For Read from DMEM usually THR1/THR2 = X+1/X-1 + * For Write to DMEM usually THR1/THR2 = 2/0 + * UP_1/2 =X+1/X-1 + */ +void abe_init_io_tasks(u32 id, abe_data_format_t *format, + abe_port_protocol_t *prot) +{ + u32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id, + io_flag; + u32 copy_func_index, before_func_index, after_func_index; + u32 dmareq_addr, dmareq_field; + u32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32; + u32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1; + u32 copy_func_index2, atc_desc_address1, atc_desc_address2; + if (prot->protocol_switch == PINGPONG_PORT_PROT) { + /* ping_pong is only supported on MM_DL */ + if (MM_DL_PORT != id) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } + smem1 = smem_mm_dl; + copy_func_index = (u8) abe_dma_port_copy_subroutine_id(id); + dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr; + dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data; + datasize = abe_dma_port_iter_factor(format); + /* number of "samples" either mono or stereo */ + iter = abe_dma_port_iteration(format); + iter_samples = (iter / datasize); + /* load the IO descriptor */ + /* no drift */ + desc_pp.drift_ASRC = 0; + /* no drift */ + desc_pp.drift_io = 0; + desc_pp.hw_ctrl_addr = (u16) dmareq_addr; + desc_pp.copy_func_index = (u8) copy_func_index; + desc_pp.smem_addr = (u8) smem1; + /* DMA req 0 is used for CBPr0 */ + desc_pp.atc_irq_data = (u8) dmareq_field; + /* size of block transfer */ + desc_pp.x_io = (u8) iter_samples; + desc_pp.data_size = (u8) datasize; + /* address comunicated in Bytes */ + desc_pp.workbuff_BaseAddr = + (u16) (abe_base_address_pingpong[1]); + /* size comunicated in XIO sample */ + desc_pp.workbuff_Samples = 0; + desc_pp.nextbuff0_BaseAddr = + (u16) (abe_base_address_pingpong[0]); + desc_pp.nextbuff1_BaseAddr = + (u16) (abe_base_address_pingpong[1]); + if (dmareq_addr == ABE_DMASTATUS_RAW) { + desc_pp.nextbuff0_Samples = + (u16) ((abe_size_pingpong >> 2) / datasize); + desc_pp.nextbuff1_Samples = + (u16) ((abe_size_pingpong >> 2) / datasize); + } else { + desc_pp.nextbuff0_Samples = 0; + desc_pp.nextbuff1_Samples = 0; + } + /* next buffer to send is B1, first IRQ fills B0 */ + desc_pp.counter = 0; + /* send a DMA req to fill B0 with N samples + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW, + &(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */ + sio_desc_address = D_PingPongDesc_ADDR; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address, (u32 *) &desc_pp, + sizeof(desc_pp)); + } else { + io_sub_id = dmareq_addr = ABE_DMASTATUS_RAW; + dmareq_field = 0; + atc_desc_address1 = atc_desc_address2 = 0; + /* default: repeat of the last downlink samples in case of + DMA errors, (disable=0x00) */ + io_flag = 0xFF; + datasize2 = datasize = abe_dma_port_iter_factor(format); + x_io = (u8) abe_dma_port_iteration(format); + nsamp = (x_io / datasize); + atc_ptr_saved2 = atc_ptr_saved = DMIC_ATC_PTR_labelID + id; + smem1 = abe_port[id].smem_buffer1; + smem3 = smem2 = abe_port[id].smem_buffer2; + copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(id); + before_func_index = after_func_index = + copy_func_index2 = NULL_COPY_CFPID; + switch (prot->protocol_switch) { + case DMIC_PORT_PROT: + /* DMIC port is read in two steps */ + x_io = x_io >> 1; + nsamp = nsamp >> 1; + atc_desc_address1 = (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE); + io_sub_id = IO_IP_CFPID; + break; + case MCPDMDL_PORT_PROT: + /* PDMDL port is written to in two steps */ + x_io = x_io >> 1; + atc_desc_address1 = + (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE); + io_sub_id = IO_IP_CFPID; + break; + case MCPDMUL_PORT_PROT: + atc_desc_address1 = + (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE); + io_sub_id = IO_IP_CFPID; + break; + case SLIMBUS_PORT_PROT: + atc_desc_address1 = + abe_port[id].protocol.p.prot_slimbus.desc_addr1; + atc_desc_address2 = + abe_port[id].protocol.p.prot_slimbus.desc_addr2; + copy_func_index2 = NULL_COPY_CFPID; + /* @@@@@@ + #define SPLIT_SMEM_CFPID 9 + #define MERGE_SMEM_CFPID 10 + #define SPLIT_TDM_12_CFPID 11 + #define MERGE_TDM_12_CFPID 12 + */ + io_sub_id = IO_IP_CFPID; + break; + case SERIAL_PORT_PROT: /* McBSP/McASP */ + atc_desc_address1 = + (s16) abe_port[id].protocol.p.prot_serial. + desc_addr; + io_sub_id = IO_IP_CFPID; + break; + case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */ + dmareq_addr = + abe_port[id].protocol.p.prot_dmareq.dma_addr; + dmareq_field = 0; + atc_desc_address1 = + abe_port[id].protocol.p.prot_dmareq.desc_addr; + io_sub_id = IO_IP_CFPID; + break; + } + /* special situation of the PING_PONG protocol which has its own SIO descriptor format */ + /* + Sequence of operations on ping-pong buffers B0/B1 + ----------------------------------------------------------------- time --------------------------------------------->>>> + Host Application is ready to send data from DDR to B0 + SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0 + FIRMWARE starts with #12 B1 data, sends IRQ/DMAreq sens #pong B1 data sends IRQ/DMAreq sends #ping B0 v sends B1 samples + ARM / SDMA | fills B0 | fills B1 ... | fills B0 ... + Counter 0 1 2 3 + */ + if (MM_UL_PORT == id) { + copy_func_index1 = COPY_MM_UL_CFPID; + before_func_index = ROUTE_MM_UL_CFPID; + } + /* check for 8kHz/16kHz */ + if (VX_DL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + if (abe_port[id].format.f == 8000) { + MultiFrame[TASK_ASRC_VX_DL_SLT] + [TASK_ASRC_VX_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8); + MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48); + /*Voice_8k_DL_labelID */ + smem1 = IO_VX_DL_ASRC_labelID; + } else { + MultiFrame[TASK_ASRC_VX_DL_SLT] + [TASK_ASRC_VX_DL_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_ASRC_VX_DL_16); + MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_16_48); + /* Voice_16k_DL_labelID */ + smem1 = IO_VX_DL_ASRC_labelID; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + /* check for 8kHz/16kHz */ + if (VX_UL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + if (abe_port[id].format.f == 8000) { + MultiFrame[TASK_ASRC_VX_UL_SLT] + [TASK_ASRC_VX_UL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8); + MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8); + /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_8); */ + smem1 = Voice_8k_UL_labelID; + } else { + MultiFrame[TASK_ASRC_VX_UL_SLT] + [TASK_ASRC_VX_UL_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_ASRC_VX_UL_16); + MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16); + /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_16); */ + smem1 = Voice_16k_UL_labelID; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + /* check for 8kHz/16kHz */ + if (BT_VX_DL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, + sizeof(u32)); + if (abe_port[id].format.f == 8000) { + MultiFrame[TASK_ASRC_BT_DL_SLT] + [TASK_ASRC_BT_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_DL_8); + if (dOppMode32 == DOPPMODE32_OPP100) { + MultiFrame[TASK_BT_DL_48_8_SLT] + [TASK_BT_DL_48_8_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_BT_DL_48_8_OPP100); + smem1 = BT_DL_8k_opp100_labelID; + } else { + MultiFrame[TASK_BT_DL_48_8_SLT] + [TASK_BT_DL_48_8_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_BT_DL_48_8); + smem1 = BT_DL_8k_labelID; + } + } else { + MultiFrame[TASK_ASRC_BT_DL_SLT] + [TASK_ASRC_BT_DL_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_ASRC_BT_DL_16); + if (dOppMode32 == DOPPMODE32_OPP100) { + MultiFrame[TASK_BT_DL_48_8_SLT] + [TASK_BT_DL_48_8_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_BT_DL_48_16_OPP100); + smem1 = BT_DL_16k_opp100_labelID; + } else { + MultiFrame[TASK_BT_DL_48_8_SLT] + [TASK_BT_DL_48_8_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_BT_DL_48_16); + smem1 = BT_DL_16k_labelID; + } + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + /* check for 8kHz/16kHz */ + if (BT_VX_UL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + /* set the SMEM buffer -- programming sequence */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, + sizeof(u32)); + if (abe_port[id].format.f == 8000) { + MultiFrame[TASK_ASRC_BT_UL_SLT] + [TASK_ASRC_BT_UL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_BT_UL_8); + MultiFrame[TASK_BT_UL_8_48_SLT] + [TASK_BT_UL_8_48_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48); + if (dOppMode32 == DOPPMODE32_OPP100) + /* ASRC input buffer, size 40 */ + smem1 = smem_bt_vx_ul_opp100; + else + /* at OPP 50 without ASRC */ + smem1 = BT_UL_8k_labelID; + } else { + MultiFrame[TASK_ASRC_BT_UL_SLT] + [TASK_ASRC_BT_UL_IDX] = + ABE_TASK_ID + (C_ABE_FW_TASK_ASRC_BT_UL_16); + MultiFrame[TASK_BT_UL_8_48_SLT] + [TASK_BT_UL_8_48_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_16_48); + if (dOppMode32 == DOPPMODE32_OPP100) + /* ASRC input buffer, size 40 */ + smem1 = smem_bt_vx_ul_opp100; + else + /* at OPP 50 without ASRC */ + smem1 = BT_UL_16k_labelID; + } + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + if (MM_DL_PORT == id) { + /* check for CBPr / serial_port / Ping-pong access */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + smem1 = smem_mm_dl; + } + if (MM_EXT_IN_PORT == id) { + /* set the SMEM buffer -- programming sequence */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, + sizeof(u32)); + if (dOppMode32 == DOPPMODE32_OPP100) + /* ASRC input buffer, size 40 */ + smem1 = smem_mm_ext_in_opp100; + else + /* at OPP 50 without ASRC */ + smem1 = smem_mm_ext_in_opp50; + } + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) + direction = 0; + else + /* offset of the write pointer in the ATC descriptor */ + direction = 3; + sio_desc.drift_ASRC = 0; + sio_desc.drift_io = 0; + sio_desc.io_type_idx = (u8) io_sub_id; + sio_desc.samp_size = (u8) datasize; + sio_desc.hw_ctrl_addr = (u16) (dmareq_addr << 2); + sio_desc.atc_irq_data = (u8) dmareq_field; + sio_desc.flow_counter = (u16) 0; + sio_desc.direction_rw = (u8) direction; + sio_desc.repeat_last_samp = (u8) io_flag; + sio_desc.nsamp = (u8) nsamp; + sio_desc.x_io = (u8) x_io; + /* set ATC ON */ + sio_desc.on_off = 0x80; + sio_desc.split_addr1 = (u16) smem1; + sio_desc.split_addr2 = (u16) smem2; + sio_desc.split_addr3 = (u16) smem3; + sio_desc.before_f_index = (u8) before_func_index; + sio_desc.after_f_index = (u8) after_func_index; + sio_desc.smem_addr1 = (u16) smem1; + sio_desc.atc_address1 = (u16) atc_desc_address1; + sio_desc.atc_pointer_saved1 = (u16) atc_ptr_saved; + sio_desc.data_size1 = (u8) datasize; + sio_desc.copy_f_index1 = (u8) copy_func_index1; + sio_desc.smem_addr2 = (u16) smem2; + sio_desc.atc_address2 = (u16) atc_desc_address2; + sio_desc.atc_pointer_saved2 = (u16) atc_ptr_saved2; + sio_desc.data_size2 = (u8) datasize2; + sio_desc.copy_f_index2 = (u8) copy_func_index2; + sio_desc_address = dmem_port_descriptors + (id * + sizeof + (ABE_SIODescriptor)); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address, (u32 *) &sio_desc, + sizeof(sio_desc)); + } +} +/** + * abe_enable_pp_io_task + * @id: port_id + * + * + */ +void abe_enable_pp_io_task(u32 id) +{ + /* MM_DL managed in ping-pong */ + if (MM_DL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_IO_PING_PONG); + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + /* ping_pong is only supported on MM_DL */ + else { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } +} +/** + * abe_disable_pp_io_task + * @id: port_id + * + * + */ +void abe_disable_pp_io_task(u32 id) +{ + /* MM_DL managed in ping-pong */ + if (MM_DL_PORT == id) { + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = 0; + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32 *) MultiFrame, + sizeof(MultiFrame)); + } + /* ping_pong is only supported on MM_DL */ + else { + abe_dbg_param |= ERR_API; + abe_dbg_error_log(ABE_PARAMETER_ERROR); + } +} +/** + * abe_init_dmic + * @x: d + * + * + */ +void abe_init_dmic(u32 x) +{ +} +/** + * abe_init_mcpdm + * @x: d + * + */ +void abe_init_mcpdm(u32 x) +{ +} +/** + * abe_reset_feature + * @x: index of the feature to be initialized + * + * reload the configuration + */ +void abe_reset_one_feature(u32 x) +{ + all_feature[x] = all_feature_init[x]; /* load default fields */ + /* abe_call_subroutine ((all_feature[x]).disable_feature, NOPARAMETER, + NOPARAMETER, NOPARAMETER, NOPARAMETER); */ +} +/** + * abe_reset_all_feature + * + * load default configuration for all features + * struct { + * uint16 load_default_data; + * uint16 read_parameter; + * uint16 write_parameter; + * uint16 running_status; + * uint16 fw_input_buffer_address; + * uint16 fw_output_buffer_address; + * uint16 fw_scheduler_slot_position; + * uint16 fw_scheduler_subslot_position; + * uint16 min_opp; + * char name[NBCHARFEATURENAME]; + * } abe_feature_t; + */ +void abe_reset_all_features(void) +{ + u16 i; + for (i = 0; i < MAXNBFEATURE; i++) + abe_reset_one_feature(i); +} +/** + * abe_reset_all_ports + * + * load default configuration for all features + */ +void abe_reset_all_ports(void) +{ + u16 i; + for (i = 0; i < LAST_PORT_ID; i++) + abe_reset_port(i); + /* mixers' configuration */ + abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2); + abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES); + abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES); + abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2); + abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER); + abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER); + abe_write_mixer(MIXECHO, MUTE_GAIN, RAMP_100MS, MIX_ECHO_DL1); + abe_write_mixer(MIXECHO, MUTE_GAIN, RAMP_100MS, MIX_ECHO_DL2); + abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL); + abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES); + abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_100MS, MIX_AUDUL_INPUT_UPLINK); + abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL); + abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES); + abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL); + abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL); + abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL); + abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); +} +/** + * abe_clean_temporay buffers + * + * clear temporary buffers + */ +void abe_clean_temporary_buffers(u32 id) +{ + switch (id) { + case DMIC_PORT: + abe_reset_mem(ABE_DMEM, D_DMIC_UL_FIFO_ADDR, + D_DMIC_UL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3, + S_DMIC0_96_48_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3, + S_DMIC1_96_48_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, + S_DMIC1_96_48_data_sizeof << 3); + abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR + dmic1_gains_offset) << 2, 6 << 2); /* reset current gains */ + abe_reset_mem(ABE_SMEM, + (S_GCurrent_ADDR + dmic1_gains_offset) << 3, + 6 << 3); + abe_reset_gain_mixer(GAINS_DMIC1, 0); + abe_reset_gain_mixer(GAINS_DMIC2, 0); + abe_reset_gain_mixer(GAINS_DMIC3, 0); + break; + case PDM_UL_PORT: + abe_reset_mem(ABE_DMEM, D_McPDM_UL_FIFO_ADDR, + D_McPDM_UL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_AMIC_96_48_data_ADDR << 3, + S_AMIC_96_48_data_sizeof << 3); + abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR + amic_gains_offset) << 2, 2 << 2); /* reset current gains */ + abe_reset_mem(ABE_SMEM, + (S_GCurrent_ADDR + amic_gains_offset) << 3, + 6 << 3); + abe_reset_gain_mixer(GAINS_AMIC, 0); + break; + case BT_VX_UL_PORT: + abe_reset_mem(ABE_DMEM, D_BT_UL_FIFO_ADDR, D_BT_UL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_HP_data_ADDR << 3, + S_BT_UL_8_48_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_LP_data_ADDR << 3, + S_BT_UL_8_48_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_HP_data_ADDR << 3, + S_BT_UL_16_48_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_LP_data_ADDR << 3, + S_BT_UL_16_48_LP_data_sizeof << 3); + break; + case MM_UL_PORT: + abe_reset_mem(ABE_DMEM, D_MM_UL_FIFO_ADDR, D_MM_UL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_MM_UL_ADDR << 3, S_MM_UL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, + D_MM_UL2_FIFO_sizeof << 3); + break; + case MM_UL2_PORT: + abe_reset_mem(ABE_DMEM, D_MM_UL2_FIFO_ADDR, + D_MM_UL2_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, + S_MM_UL2_sizeof << 3); + break; + case VX_UL_PORT: + abe_reset_mem(ABE_DMEM, D_VX_UL_FIFO_ADDR, D_VX_UL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_VX_UL_ADDR << 3, S_VX_UL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_HP_data_ADDR << 3, + S_VX_UL_48_8_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3, + S_VX_UL_48_8_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3, + S_VX_UL_48_16_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3, + S_VX_UL_48_16_LP_data_sizeof << 3); + abe_reset_gain_mixer(MIXAUDUL, MIX_AUDUL_INPUT_UPLINK); + break; + case MM_DL_PORT: + abe_reset_mem(ABE_DMEM, D_MM_DL_FIFO_ADDR, D_MM_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_MM_DL_ADDR << 3, S_MM_DL_sizeof << 3); + abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_MM_DL); + abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_MM_DL); + break; + case VX_DL_PORT: + abe_reset_mem(ABE_DMEM, D_VX_DL_FIFO_ADDR, D_VX_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_VX_DL_ADDR << 3, S_VX_DL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_HP_data_ADDR << 3, + S_VX_DL_8_48_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3, + S_VX_DL_8_48_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3, + S_VX_DL_16_48_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3, + S_VX_DL_16_48_LP_data_sizeof << 3); + abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_VX_DL); + abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_VX_DL); + break; + case TONES_DL_PORT: + abe_reset_mem(ABE_DMEM, D_TONES_DL_FIFO_ADDR, + D_TONES_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_Tones_ADDR << 3, S_Tones_sizeof << 3); + abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_TONES); + abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_TONES); + break; + case VIB_DL_PORT: + abe_reset_mem(ABE_DMEM, D_VIB_DL_FIFO_ADDR, + D_VIB_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_VIBRA_ADDR << 3, S_VIBRA_sizeof << 3); + break; + case BT_VX_DL_PORT: + abe_reset_mem(ABE_DMEM, D_BT_DL_FIFO_ADDR, D_BT_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_BT_DL_ADDR << 3, S_BT_DL_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_HP_data_ADDR << 3, + S_BT_DL_48_8_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_LP_data_ADDR << 3, + S_BT_DL_48_8_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_HP_data_ADDR << 3, + S_BT_DL_48_16_HP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_LP_data_ADDR << 3, + S_BT_DL_48_16_LP_data_sizeof << 3); + break; + case PDM_DL_PORT: + abe_reset_mem(ABE_DMEM, D_McPDM_DL_FIFO_ADDR, + D_McPDM_DL_FIFO_sizeof); + abe_reset_mem(ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3, + S_DL2_M_LR_EQ_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3, + S_DL1_M_EQ_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3, + S_EARP_48_96_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3, + S_IHF_48_96_LP_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3, + S_APS_DL1_EQ_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3, + S_APS_DL2_EQ_data_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_APS_DL2_L_IIRmem1_ADDR << 3, + S_APS_DL2_L_IIRmem1_sizeof << 3); + abe_reset_mem(ABE_SMEM, S_APS_DL2_R_IIRmem1_ADDR << 3, + S_APS_DL2_R_IIRmem1_sizeof << 3); + abe_reset_gain_mixer(GAINS_DL1, GAIN_LEFT_OFFSET); + abe_reset_gain_mixer(GAINS_DL1, GAIN_RIGHT_OFFSET); + abe_reset_gain_mixer(GAINS_DL2, GAIN_LEFT_OFFSET); + abe_reset_gain_mixer(GAINS_DL2, GAIN_RIGHT_OFFSET); + abe_reset_gain_mixer(MIXSDT, MIX_SDT_INPUT_UP_MIXER); + abe_reset_gain_mixer(MIXSDT, MIX_SDT_INPUT_DL1_MIXER); + break; + case MM_EXT_OUT_PORT: + abe_reset_mem(ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR, + D_MM_EXT_OUT_FIFO_sizeof); + break; + case MM_EXT_IN_PORT: + abe_reset_mem(ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR, + D_MM_EXT_IN_FIFO_sizeof); + break; + } +} +/** + * abe_clear_current_gain_mixer + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + * restart the working gain value of the mixers when a port is enabled + */ +void abe_reset_gain_mixer(u32 id, u32 p) +{ + u32 lin_g, mixer_target, mixer_offset; + switch (id) { + default: + case GAINS_DMIC1: + mixer_offset = dmic1_gains_offset; + break; + case GAINS_DMIC2: + mixer_offset = dmic2_gains_offset; + break; + case GAINS_DMIC3: + mixer_offset = dmic3_gains_offset; + break; + case GAINS_AMIC: + mixer_offset = amic_gains_offset; + break; + case GAINS_DL1: + mixer_offset = dl1_gains_offset; + break; + case GAINS_DL2: + mixer_offset = dl2_gains_offset; + break; + case GAINS_SPLIT: + mixer_offset = splitters_gains_offset; + break; + case MIXDL1: + mixer_offset = mixer_dl1_offset; + break; + case MIXDL2: + mixer_offset = mixer_dl2_offset; + break; + case MIXECHO: + mixer_offset = mixer_echo_offset; + break; + case MIXSDT: + mixer_offset = mixer_sdt_offset; + break; + case MIXVXREC: + mixer_offset = mixer_vxrec_offset; + break; + case MIXAUDUL: + mixer_offset = mixer_audul_offset; + break; + } + /* SMEM word32 address for the CURRENT gain values */ + mixer_target = (S_GCurrent_ADDR << 1); + mixer_target += mixer_offset; + mixer_target += p; + /* translate coef address in Bytes */ + mixer_target <<= 2; + lin_g = 0; + /* load the S_G_Target SMEM table */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target, + (u32 *) &lin_g, sizeof(lin_g)); +} +/** + * abe_init_asrc_vx_dl + * + * Initialize the following ASRC VX_DL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_DL_VX_Coefs pointer + * 10. CMEM for ASRC_DL_VX_Coefs pointer + * ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_DL_VX pointer + * 12. CMEM for XinASRC_DL_VX pointer + * XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 + * 13. SMEM for IO_VX_DL_ASRC pointer + * 14. CMEM for IO_VX_DL_ASRC pointer + * IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_vx_dl(s32 dppm) +{ + s32 el[45]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + temp0 = 0; + temp1 = 1; + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + (1 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i + 1] = 1; + adppm = dppm; + } else { + el[i + 1] = -1; + adppm = (-1 * dppm); + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + (2 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + (3 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = dtemp << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + (4 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = (-dtemp) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + (5 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0x00400000; + } else { + el[i + 1] = (0x00100000 - (dtemp / 2)) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_DL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x00000020; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_DL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x003fffe0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + (VX_DL_PORT * sizeof(ABE_SIODescriptor)) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 9. SMEM for ASRC_DL_VX_Coefs pointer */ + /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0 + /1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_DL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = C_CoefASRC16_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_VX_sizeof; + el[i + 2] = C_CoefASRC15_VX_ADDR; + el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + /* 10. CMEM for ASRC_DL_VX_Coefs pointer */ + /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/ + 1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_DL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 11. SMEM for XinASRC_DL_VX pointer */ + /* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_DL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_DL_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_DL_VX_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 12. CMEM for XinASRC_DL_VX pointer */ + /* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_DL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 13. SMEM for IO_VX_DL_ASRC pointer */ + /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ + ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = IO_VX_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_DL_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_DL_VX_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 14. CMEM for IO_VX_DL_ASRC pointer */ + /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ + ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = IO_VX_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_DL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 42); +} +/** + * abe_init_asrc_vx_ul + * + * Initialize the following ASRC VX_UL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_UL_VX_Coefs pointer + * 10. CMEM for ASRC_UL_VX_Coefs pointer + * ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof + * /0/1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_UL_VX pointer + * 12. CMEM for XinASRC_UL_VX pointer + * XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 + * 13. SMEM for UL_48_8_DEC pointer + * 14. CMEM for UL_48_8_DEC pointer + * UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + * 15. SMEM for UL_48_16_DEC pointer + * 16. CMEM for UL_48_16_DEC pointer + * UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_vx_ul(s32 dppm) +{ + s32 el[51]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + temp0 = 0; + temp1 = 1; + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + (1 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i + 1] = 1; + adppm = dppm; + } else { + el[i + 1] = -1; + adppm = (-1 * dppm); + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + (2 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + (3 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = dtemp << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + (4 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = (-dtemp) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + (5 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0x00400000; + } else { + el[i + 1] = (0x00100000 - (dtemp / 2)) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_UL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x00000020; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_UL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x003fffe0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + (VX_UL_PORT * sizeof(ABE_SIODescriptor)) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 9. SMEM for ASRC_UL_VX_Coefs pointer */ + /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_UL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = C_CoefASRC16_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_VX_sizeof; + el[i + 2] = C_CoefASRC15_VX_ADDR; + el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + /* 10. CMEM for ASRC_UL_VX_Coefs pointer */ + /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_UL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 11. SMEM for XinASRC_UL_VX pointer */ + /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_UL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_UL_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 12. CMEM for XinASRC_UL_VX pointer */ + /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_UL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 13. SMEM for UL_48_8_DEC pointer */ + /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = UL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_UL_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 14. CMEM for UL_48_8_DEC pointer */ + /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = UL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 15. SMEM for UL_48_16_DEC pointer */ + /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = UL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_UL_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 16. CMEM for UL_48_16_DEC pointer */ + /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = UL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 48); +} +/** + * abe_init_asrc_mm_ext_in + * + * Initialize the following ASRC MM_EXT_IN parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_MM_EXT_IN_Coefs pointer + * 10. CMEM for ASRC_MM_EXT_IN_Coefs pointer + * ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof/ + * 0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 + * 11. SMEM for XinASRC_MM_EXT_IN pointer + * 12. CMEM for XinASRC_MM_EXT_IN pointer + * XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 + * 13. SMEM for IO_MM_EXT_IN_ASRC pointer + * 14. CMEM for IO_MM_EXT_IN_ASRC pointer + * IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/ + * ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 + */ +void abe_init_asrc_mm_ext_in(s32 dppm) +{ + s32 el[45]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + temp0 = 0; + temp1 = 1; + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (1 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i + 1] = 1; + adppm = dppm; + } else { + el[i + 1] = -1; + adppm = (-1 * dppm); + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (2 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (3 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = dtemp << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (4 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0; + } else { + el[i + 1] = (-dtemp) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (5 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i + 1] = 0x00400000; + } else { + el[i + 1] = (0x00100000 - (dtemp / 2)) << 2; + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_MM_EXT_IN_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x00000020; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_MM_EXT_IN_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x003fffe0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + (MM_EXT_IN_PORT * sizeof(ABE_SIODescriptor)) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 9. SMEM for ASRC_MM_EXT_IN_Coefs pointer */ + /* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof + /0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_MM_EXT_IN_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = C_CoefASRC16_MM_ADDR; + el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_MM_sizeof; + el[i + 2] = C_CoefASRC15_MM_ADDR; + el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_MM_sizeof; + i = i + 3; + /*10. CMEM for ASRC_MM_EXT_IN_Coefs pointer */ + /* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof + /0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_MM_EXT_IN_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 11. SMEM for XinASRC_MM_EXT_IN pointer */ + /* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_MM_EXT_IN_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_MM_EXT_IN_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_MM_EXT_IN_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 12. CMEM for XinASRC_MM_EXT_IN pointer */ + /* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_MM_EXT_IN_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + /* 13. SMEM for IO_MM_EXT_IN_ASRC pointer */ + /* IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/ + ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = IO_MM_EXT_IN_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_MM_EXT_IN_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_MM_EXT_IN_sizeof; + el[i + 2] = temp0; + i = i + 3; + /* 14. CMEM for IO_MM_EXT_IN_ASRC pointer */ + /* IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/ + ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = IO_MM_EXT_IN_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_MM_EXT_IN_FIR_L + ASRC_margin + ASRC_N_48k) << 16) + + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 42); +} +/** + * abe_init_asrc_bt_ul + * + * Initialize the following ASRC BT_UL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_BT_UL_Coefs pointer + * 10. CMEM for ASRC_BT_UL_Coefs pointer + * ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_BT_UL pointer + * 12. CMEM for XinASRC_BT_UL pointer + * XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/0/0/0/0 + * 13. SMEM for IO_BT_UL_ASRC pointer + * 14. CMEM for IO_BT_UL_ASRC pointer + * IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_bt_ul(s32 dppm) +{ + s32 el[45]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + temp0 = 0; + temp1 = 1; + + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_UL_ADDR + (1 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i + 1] = 1; + adppm = dppm; + } else { + el[i + 1] = -1; + adppm = (-1 * dppm); + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_UL_ADDR + (2 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_UL_ADDR + (3 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0; + else + el[i + 1] = dtemp << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_UL_ADDR + (4 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0; + else + el[i + 1] = (-dtemp) << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_UL_ADDR + (5 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0x00400000; + else + el[i + 1] = (0x00100000 - (dtemp / 2)) << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_BT_UL_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x00000020; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_BT_UL_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x003fffe0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + (BT_VX_UL_PORT * sizeof(ABE_SIODescriptor)) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 9. SMEM for ASRC_BT_UL_Coefs pointer */ + /* ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0 + /1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_BT_UL_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = C_CoefASRC16_VX_ADDR; + el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_VX_sizeof; + el[i + 2] = C_CoefASRC15_VX_ADDR; + el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + + /* 10. CMEM for ASRC_BT_UL_Coefs pointer */ + /* ASRC_BT_UL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/ + 1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_BT_UL_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 11. SMEM for XinASRC_BT_UL pointer */ + /* XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_BT_UL_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_BT_UL_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_BT_UL_sizeof; + el[i + 2] = temp0; + i = i + 3; + + /* 12. CMEM for XinASRC_BT_UL pointer */ + /* XinASRC_BT_UL = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_BT_UL_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 13. SMEM for IO_BT_UL_ASRC pointer */ + /* IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/ + ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = IO_BT_UL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = S_XinASRC_BT_UL_ADDR; + el[i + 1] = (el[i + 1] << 8) + S_XinASRC_BT_UL_sizeof; + el[i + 2] = temp0; + i = i + 3; + + /* 14. CMEM for IO_BT_UL_ASRC pointer */ + /* IO_BT_UL_ASRC = S_XinASRC_BT_UL_ADDR/S_XinASRC_BT_UL_sizeof/ + ASRC_BT_UL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = IO_BT_UL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_BT_UL_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 42); +} +/** + * abe_init_asrc_bt_dl + * + * Initialize the following ASRC BT_DL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_BT_DL_Coefs pointer + * 10. CMEM for ASRC_BT_DL_Coefs pointer + * ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof + * /0/1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_BT_DL pointer + * 12. CMEM for XinASRC_BT_DL pointer + * XinASRC_BT_DL = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0 + * 13. SMEM for DL_48_8_DEC pointer + * 14. CMEM for DL_48_8_DEC pointer + * DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + * ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 + * 15. SMEM for DL_48_16_DEC pointer + * 16. CMEM for DL_48_16_DEC pointer + * DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + * ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_bt_dl(s32 dppm) +{ + s32 el[51]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + temp0 = 0; + temp1 = 1; + + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_DL_ADDR + (1 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i + 1] = 1; + adppm = dppm; + } else { + el[i + 1] = -1; + adppm = (-1 * dppm); + } + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L); + + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_DL_ADDR + (2 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_DL_ADDR + (3 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0; + else + el[i + 1] = dtemp << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_DL_ADDR + (4 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0; + else + el[i + 1] = (-dtemp) << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_BT_DL_ADDR + (5 * sizeof(s32)); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) + el[i + 1] = 0x00400000; + else + el[i + 1] = (0x00100000 - (dtemp / 2)) << 2; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_BT_DL_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x00000020; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_BT_DL_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = 0x003fffe0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + (BT_VX_DL_PORT * sizeof(ABE_SIODescriptor)) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i + 1] = temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 9. SMEM for ASRC_BT_DL_Coefs pointer */ + /* ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_BT_DL_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = (C_CoefASRC16_VX_ADDR << 8) + C_CoefASRC16_VX_sizeof; + el[i + 2] = (C_CoefASRC15_VX_ADDR << 8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + + /* 10. CMEM for ASRC_BT_DL_Coefs pointer */ + /* ASRC_BT_DL_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_BT_DL_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 11. SMEM for XinASRC_BT_DL pointer */ + /* XinASRC_BT_DL = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_BT_DL_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = (S_XinASRC_BT_DL_ADDR << 8) + S_XinASRC_BT_DL_sizeof; + el[i + 2] = temp0; + i = i + 3; + + /* 12. CMEM for XinASRC_BT_DL pointer */ + /* XinASRC_BT_DL = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_BT_DL_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 13. SMEM for DL_48_8_DEC pointer */ + /* DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = DL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = (S_XinASRC_BT_DL_ADDR << 8) + S_XinASRC_BT_DL_sizeof; + el[i + 2] = temp0; + i = i + 3; + + /* 14. CMEM for DL_48_8_DEC pointer */ + /* DL_48_8_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = DL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_BT_DL_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + i = i + 3; + + /* 15. SMEM for DL_48_16_DEC pointer */ + /* DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = DL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i + 1] = (S_XinASRC_BT_DL_ADDR << 8) + S_XinASRC_BT_DL_sizeof; + el[i + 2] = temp0; + i = i + 3; + + /* 16. CMEM for DL_48_16_DEC pointer */ + /* DL_48_16_DEC = S_XinASRC_BT_DL_ADDR/S_XinASRC_BT_DL_sizeof/ + ASRC_BT_DL_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = DL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i + 1] = ((ASRC_BT_DL_FIR_L + ASRC_margin) << 16) + (temp1 << 12) + + (temp0 << 4) + temp0; + /* dummy field */ + el[i + 2] = temp0; + abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 48); +} diff --git a/sound/soc/omap/abe/abe_initxxx_labels.h b/sound/soc/omap/abe/abe_initxxx_labels.h new file mode 100644 index 00000000000..5120c000dfa --- /dev/null +++ b/sound/soc/omap/abe/abe_initxxx_labels.h @@ -0,0 +1,332 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_INITXXX_LABELS_H_ +#define _ABE_INITXXX_LABELS_H_ +#define Dummy_Regs_labelID 0 +#define Dummy_AM_labelID 1 +#define Voice_8k_UL_labelID 2 +#define Voice_8k_DL_labelID 3 +#define ECHO_REF_8K_labelID 4 +#define Voice_16k_UL_labelID 5 +#define Voice_16k_DL_labelID 6 +#define ECHO_REF_16K_labelID 7 +#define MM_DL_labelID 8 +#define IO_VX_DL_ASRC_labelID 9 +#define IO_MM_EXT_IN_ASRC_labelID 10 +#define IO_VIBRA_DL_labelID 11 +#define ZERO_labelID 12 +#define GTarget_labelID 13 +#define GCurrent_labelID 14 +#define Gr_1_labelID 15 +#define Gr_2_labelID 16 +#define Gr_Regs_labelID 17 +#define DMIC0_Gain_labelID 18 +#define DMIC1_Gain_labelID 19 +#define DMIC2_Gain_labelID 20 +#define DMIC3_Gain_labelID 21 +#define AMIC_Gain_labelID 22 +#define MIXDL1_Gain_labelID 23 +#define MIXDL2_Gain_labelID 24 +#define DEFAULT_Gain_labelID 25 +#define DL1_M_G_Tones_labelID 26 +#define DL2_M_G_Tones_labelID 27 +#define Echo_M_G_labelID 28 +#define SDT_M_G_labelID 29 +#define VXREC_M_G_VX_DL_labelID 30 +#define UL_M_G_VX_DL_labelID 31 +#define DL1_M_labelID 32 +#define DL2_M_labelID 33 +#define MM_UL2_labelID 34 +#define VX_DL_labelID 35 +#define Tones_labelID 36 +#define DL_M_MM_UL2_VX_DL_labelID 37 +#define Echo_M_labelID 38 +#define VX_UL_labelID 39 +#define VX_UL_M_labelID 40 +#define SDT_F_labelID 41 +#define SDT_F_data_labelID 42 +#define SDT_Coef_labelID 43 +#define SDT_Regs_labelID 44 +#define SDT_M_labelID 45 +#define DL1_EQ_labelID 46 +#define DL2_EQ_labelID 47 +#define DL1_GAIN_out_labelID 48 +#define DL2_GAIN_out_labelID 49 +#define DMIC1_labelID 50 +#define DMIC1_L_labelID 51 +#define DMIC1_R_labelID 52 +#define DMIC2_labelID 53 +#define DMIC2_L_labelID 54 +#define DMIC2_R_labelID 55 +#define DMIC3_labelID 56 +#define DMIC3_L_labelID 57 +#define DMIC3_R_labelID 58 +#define MIC4_labelID 59 +#define MIC4_L_labelID 60 +#define MIC4_R_labelID 61 +#define BT_UL_L_labelID 62 +#define BT_UL_R_labelID 63 +#define AMIC_labelID 64 +#define AMIC_L_labelID 65 +#define AMIC_R_labelID 66 +#define EchoRef_L_labelID 67 +#define EchoRef_R_labelID 68 +#define MM_DL_L_labelID 69 +#define MM_DL_R_labelID 70 +#define MM_UL_labelID 71 +#define AMIC_96_labelID 72 +#define DMIC0_96_labelID 73 +#define DMIC1_96_labelID 74 +#define DMIC2_96_labelID 75 +#define UL_MIC_48K_labelID 76 +#define EQ_DL_48K_labelID 77 +#define EQ_48K_labelID 78 +#define McPDM_Out1_labelID 79 +#define McPDM_Out2_labelID 80 +#define McPDM_Out3_labelID 81 +#define VX_UL_MUX_labelID 82 +#define MM_UL2_MUX_labelID 83 +#define MM_UL_MUX_labelID 84 +#define XinASRC_DL_VX_labelID 85 +#define ASRC_DL_VX_Coefs_labelID 86 +#define ASRC_DL_VX_Alpha_labelID 87 +#define ASRC_DL_VX_VarsBeta_labelID 88 +#define ASRC_DL_VX_8k_Regs_labelID 89 +#define XinASRC_UL_VX_labelID 90 +#define ASRC_UL_VX_Coefs_labelID 91 +#define ASRC_UL_VX_Alpha_labelID 92 +#define ASRC_UL_VX_VarsBeta_labelID 93 +#define ASRC_UL_VX_8k_Regs_labelID 94 +#define UL_48_8_DEC_labelID 95 +#define ASRC_DL_VX_16k_Regs_labelID 96 +#define ASRC_UL_VX_16k_Regs_labelID 97 +#define UL_48_16_DEC_labelID 98 +#define XinASRC_MM_EXT_IN_labelID 99 +#define ASRC_MM_EXT_IN_Coefs_labelID 100 +#define ASRC_MM_EXT_IN_Alpha_labelID 101 +#define ASRC_MM_EXT_IN_VarsBeta_labelID 102 +#define ASRC_MM_EXT_IN_Regs_labelID 103 +#define VX_REC_labelID 104 +#define VXREC_UL_M_Tones_VX_UL_labelID 105 +#define VX_REC_L_labelID 106 +#define VX_REC_R_labelID 107 +#define DL2_M_L_labelID 108 +#define DL2_M_R_labelID 109 +#define DL1_M_data_labelID 110 +#define DL1_M_Coefs_labelID 111 +#define DL2_M_LR_data_labelID 112 +#define DL2_M_LR_Coefs_labelID 113 +#define SRC_6_LP_COEFS_labelID 114 +#define SRC_6_LP_GAIN_COEFS_labelID 115 +#define SRC_6_HP_COEFS_labelID 116 +#define SRC_3_LP_COEFS_labelID 117 +#define SRC_3_LP_GAIN_COEFS_labelID 118 +#define SRC_3_HP_COEFS_labelID 119 +#define VX_DL_8_48_LP_DATA_labelID 120 +#define VX_DL_8_48_HP_DATA_labelID 121 +#define VX_DL_16_48_LP_DATA_labelID 122 +#define VX_DL_16_48_HP_DATA_labelID 123 +#define VX_UL_48_8_LP_DATA_labelID 124 +#define VX_UL_48_8_HP_DATA_labelID 125 +#define VX_UL_48_16_LP_DATA_labelID 126 +#define VX_UL_48_16_HP_DATA_labelID 127 +#define BT_UL_8_48_LP_DATA_labelID 128 +#define BT_UL_8_48_HP_DATA_labelID 129 +#define BT_UL_16_48_LP_DATA_labelID 130 +#define BT_UL_16_48_HP_DATA_labelID 131 +#define BT_DL_48_8_LP_DATA_labelID 132 +#define BT_DL_48_8_HP_DATA_labelID 133 +#define BT_DL_48_16_LP_DATA_labelID 134 +#define BT_DL_48_16_HP_DATA_labelID 135 +#define ECHO_REF_48_16_LP_DATA_labelID 136 +#define ECHO_REF_48_16_HP_DATA_labelID 137 +#define ECHO_REF_48_8_LP_DATA_labelID 138 +#define ECHO_REF_48_8_HP_DATA_labelID 139 +#define ECHO_REF_DEC_labelID 140 +#define VX_UL_8_TEMP_labelID 141 +#define VX_UL_16_TEMP_labelID 142 +#define UP_DOWN_8_48_labelID 143 +#define UP_DOWN_16_48_labelID 144 +#define SRC_6_LP_48k_labelID 145 +#define SRC_6_HP_labelID 146 +#define SRC_3_LP_48k_labelID 147 +#define SRC_3_HP_labelID 148 +#define EARP_48_96_LP_DATA_labelID 149 +#define SRC_48_96_LP_labelID 150 +#define IHF_48_96_LP_DATA_labelID 151 +#define EQ_VX_UL_16K_labelID 152 +#define pAPS_iir1_p23_labelID 153 +#define pAPS_iir1_p45_labelID 154 +#define APS_IIR_Regs_labelID 155 +#define pAPS_core_DL1_p1_labelID 156 +#define pAPS_core_DL1_p23_labelID 157 +#define pAPS_core_DL1_p45_labelID 158 +#define pAPS_core_DL1_r_labelID 159 +#define pAPS_DL2L_core_r_labelID 160 +#define pAPS_DL2R_core_r_labelID 161 +#define pAPS_COIL_core_DL1_p1_labelID 162 +#define pAPS_COIL_core_DL1_p23_labelID 163 +#define pAPS_COIL_core_DL1_p45_labelID 164 +#define pAPS_COIL_core_DL1_r_labelID 165 +#define DL2_L_APS_IIR_p23_labelID 166 +#define DL2_R_APS_IIR_p23_labelID 167 +#define DL2_L_APS_IIR_p45_labelID 168 +#define DL2_R_APS_IIR_p45_labelID 169 +#define DL2_L_APS_CORE_p1_labelID 170 +#define DL2_L_APS_CORE_p23_labelID 171 +#define DL2_L_APS_CORE_p45_labelID 172 +#define DL2_R_APS_CORE_p1_labelID 173 +#define DL2_R_APS_CORE_p23_labelID 174 +#define DL2_R_APS_CORE_p45_labelID 175 +#define DL2_L_APS_COIL_CORE_p1_labelID 176 +#define DL2_L_APS_COIL_CORE_p23_labelID 177 +#define DL2_L_APS_COIL_CORE_p45_labelID 178 +#define pAPS_COIL_DL2L_core_r_labelID 179 +#define DL2_R_APS_COIL_CORE_p1_labelID 180 +#define DL2_R_APS_COIL_CORE_p23_labelID 181 +#define DL2_R_APS_COIL_CORE_p45_labelID 182 +#define pAPS_COIL_DL2R_core_r_labelID 183 +#define DL1_APS_labelID 184 +#define DL2_L_APS_labelID 185 +#define DL2_R_APS_labelID 186 +#define DL1_APS_EQ_p23_labelID 187 +#define DL1_APS_EQ_p45_labelID 188 +#define DL2_APS_EQ_p23_labelID 189 +#define DL2_APS_EQ_p45_labelID 190 +#define pVIBRA1_p0_labelID 191 +#define pVIBRA1_p1_labelID 192 +#define pVIBRA1_p23_labelID 193 +#define pVIBRA1_p45_labelID 194 +#define pVibra1_pR1_labelID 195 +#define pVibra1_pR2_labelID 196 +#define pVibra1_pR3_labelID 197 +#define pVIBRA1_r_labelID 198 +#define pVIBRA2_p0_labelID 199 +#define pVIBRA2_p1_labelID 200 +#define pVIBRA2_p23_labelID 201 +#define pVIBRA2_p45_labelID 202 +#define pCtrl_p67_labelID 203 +#define pVIBRA2_r_labelID 204 +#define VIBRA_labelID 205 +#define PING_labelID 206 +#define PING_Regs_labelID 207 +#define UP_48_96_LP_COEFS_labelID 208 +#define AMIC_96_48_data_labelID 209 +#define DOWN_96_48_AMIC_Coefs_labelID 210 +#define DOWN_96_48_DMIC_Coefs_labelID 211 +#define DOWN_96_48_AMIC_Regs_labelID 212 +#define DOWN_96_48_DMIC_Regs_labelID 213 +#define DMIC0_96_48_data_labelID 214 +#define DMIC1_96_48_data_labelID 215 +#define DMIC2_96_48_data_labelID 216 +#define SIO_DMIC_labelID 217 +#define SIO_PDM_UL_labelID 218 +#define SIO_BT_VX_UL_labelID 219 +#define SIO_MM_UL_labelID 220 +#define SIO_MM_UL2_labelID 221 +#define SIO_VX_UL_labelID 222 +#define SIO_MM_DL_labelID 223 +#define SIO_VX_DL_labelID 224 +#define SIO_TONES_DL_labelID 225 +#define SIO_VIB_DL_labelID 226 +#define SIO_BT_VX_DL_labelID 227 +#define SIO_PDM_DL_labelID 228 +#define SIO_MM_EXT_OUT_labelID 229 +#define SIO_MM_EXT_IN_labelID 230 +#define SIO_TDM_OUT_labelID 231 +#define SIO_TDM_IN_labelID 232 +#define DMIC_ATC_PTR_labelID 233 +#define MCPDM_UL_ATC_PTR_labelID 234 +#define BT_VX_UL_ATC_PTR_labelID 235 +#define MM_UL_ATC_PTR_labelID 236 +#define MM_UL2_ATC_PTR_labelID 237 +#define VX_UL_ATC_PTR_labelID 238 +#define MM_DL_ATC_PTR_labelID 239 +#define VX_DL_ATC_PTR_labelID 240 +#define TONES_DL_ATC_PTR_labelID 241 +#define VIB_DL_ATC_PTR_labelID 242 +#define BT_VX_DL_ATC_PTR_labelID 243 +#define PDM_DL_ATC_PTR_labelID 244 +#define MM_EXT_OUT_ATC_PTR_labelID 245 +#define MM_EXT_IN_ATC_PTR_labelID 246 +#define TDM_OUT_ATC_PTR_labelID 247 +#define TDM_IN_ATC_PTR_labelID 248 +#define MCU_IRQ_FIFO_ptr_labelID 249 +#define DEBUG_IRQ_FIFO_reg_labelID 250 +#define UP_DOWN_48_96_labelID 251 +#define OSR96_2_labelID 252 +#define DEBUG_GAINS_labelID 253 +#define DBG_8K_PATTERN_labelID 254 +#define DBG_16K_PATTERN_labelID 255 +#define DBG_24K_PATTERN_labelID 256 +#define DBG_48K_PATTERN_labelID 257 +#define DBG_96K_PATTERN_labelID 258 +#define UL_VX_UL_48_8K_labelID 259 +#define UL_VX_UL_48_16K_labelID 260 +#define BT_DL_labelID 261 +#define BT_UL_labelID 262 +#define BT_DL_8k_labelID 263 +#define BT_DL_16k_labelID 264 +#define BT_UL_8k_labelID 265 +#define BT_UL_16k_labelID 266 +#define MM_EXT_IN_labelID 267 +#define MM_EXT_IN_L_labelID 268 +#define MM_EXT_IN_R_labelID 269 +#define ECHO_REF_48_16_WRAP_labelID 270 +#define ECHO_REF_48_8_WRAP_labelID 271 +#define BT_UL_16_48_WRAP_labelID 272 +#define BT_UL_8_48_WRAP_labelID 273 +#define BT_DL_48_16_WRAP_labelID 274 +#define BT_DL_48_8_WRAP_labelID 275 +#define VX_DL_16_48_WRAP_labelID 276 +#define VX_DL_8_48_WRAP_labelID 277 +#define VX_UL_48_16_WRAP_labelID 278 +#define VX_UL_48_8_WRAP_labelID 279 +#define APS_DL1_IRQs_WRAP_labelID 280 +#define APS_DL2_L_IRQs_WRAP_labelID 281 +#define APS_DL2_R_IRQs_WRAP_labelID 282 +#define ATC_NULL_BUFFER_labelID 283 +#define MEM_INIT_hal_mem_labelID 284 +#define MEM_INIT_write_mem_labelID 285 +#define MEM_INIT_regs_labelID 286 +#define GAIN_0DB_labelID 287 +#define XinASRC_BT_UL_labelID 288 +#define IO_BT_UL_ASRC_labelID 289 +#define ASRC_BT_UL_Coefs_labelID 290 +#define ASRC_BT_UL_Alpha_labelID 291 +#define ASRC_BT_UL_VarsBeta_labelID 292 +#define ASRC_BT_UL_8k_Regs_labelID 293 +#define ASRC_BT_UL_16k_Regs_labelID 294 +#define XinASRC_BT_DL_labelID 295 +#define DL_48_8_DEC_labelID 296 +#define DL_48_16_DEC_labelID 297 +#define BT_DL_8k_TEMP_labelID 298 +#define BT_DL_16k_TEMP_labelID 299 +#define BT_DL_8k_opp100_labelID 300 +#define BT_DL_16k_opp100_labelID 301 +#define ASRC_BT_DL_Coefs_labelID 302 +#define ASRC_BT_DL_Alpha_labelID 303 +#define ASRC_BT_DL_VarsBeta_labelID 304 +#define ASRC_BT_DL_8k_Regs_labelID 305 +#define ASRC_BT_DL_16k_Regs_labelID 306 +#define BT_DL_48_8_OPP100_WRAP_labelID 307 +#define BT_DL_48_16_OPP100_WRAP_labelID 308 +#endif/* _ABE_INITXXXX_LABELS_H_ */ diff --git a/sound/soc/omap/abe/abe_irq.c b/sound/soc/omap/abe/abe_irq.c new file mode 100644 index 00000000000..cfed1c2cb5a --- /dev/null +++ b/sound/soc/omap/abe/abe_irq.c @@ -0,0 +1,62 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +/* + * initialize the default values for call-backs to subroutines + * - FIFO IRQ call-backs for sequenced tasks + * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols) + * - Remote debugger interface + * - Error monitoring + * - Activity Tracing + */ +/** + * abe_irq_ping_pong + * + * Call the respective subroutine depending on the IRQ FIFO content: + * APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], loopCounter to [15:0] + * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0] + * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0] + */ +void abe_irq_ping_pong(void) +{ + abe_call_subroutine(abe_irq_pingpong_player_id, NOPARAMETER, + NOPARAMETER, NOPARAMETER, NOPARAMETER); +} +/** + * abe_irq_check_for_sequences +* @i: sequence ID + * + * check the active sequence list + * + */ +void abe_irq_check_for_sequences(u32 i) +{ +} +/** + * abe_irq_aps + * + * call the application subroutines that updates the acoustics protection filters + */ +void abe_irq_aps(u32 aps_info) +{ + abe_call_subroutine(abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER, + NOPARAMETER, NOPARAMETER); +} diff --git a/sound/soc/omap/abe/abe_lib.c b/sound/soc/omap/abe/abe_lib.c new file mode 100644 index 00000000000..d95afe74343 --- /dev/null +++ b/sound/soc/omap/abe/abe_lib.c @@ -0,0 +1,394 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" +/** +* abe_fprintf +* @line: character line to be printed +* +* Print ABE debug messages. +*/ +/** + * abe_read_feature_from_port + * @x: d + * + * TBD + * + */ +void abe_read_feature_from_port(u32 x) +{ +} +/** + * abe_write_feature_to_port + * @x: d + * + * TBD + * + */ +void abe_write_feature_to_port(u32 x) +{ +} +/** + * abe_read_fifo + * @x: d + * + * TBD + */ +void abe_read_fifo(u32 x) +{ +} +/** + * abe_write_fifo + * @mem_bank: currently only ABE_DMEM supported + * @addr: FIFO descriptor address ( descriptor fields : READ ptr, WRITE ptr, + * FIFO START_ADDR, FIFO END_ADDR) + * @data: data to write to FIFO + * @number: number of 32-bit words to write to DMEM FIFO + * + * write DMEM FIFO and update FIFO descriptor, it is assumed that FIFO descriptor + * is located in DMEM + */ +void abe_write_fifo(u32 memory_bank, u32 descr_addr, u32 *data, u32 nb_data32) +{ + u32 fifo_addr[4]; + u32 i; + /* read FIFO descriptor from DMEM */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, descr_addr, + &fifo_addr[0], 4 * sizeof(u32)); + /* WRITE ptr < FIFO start address */ + if (fifo_addr[1] < fifo_addr[2]) + abe_dbg_error_log(ABE_FW_FIFO_WRITE_PTR_ERR); + /* WRITE ptr > FIFO end address */ + if (fifo_addr[1] > fifo_addr[3]) + abe_dbg_error_log(ABE_FW_FIFO_WRITE_PTR_ERR); + switch (memory_bank) { + case ABE_DMEM: + for (i = 0; i < nb_data32; i++) { + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (s32) fifo_addr[1], (u32 *) (data + i), + 4); + /* increment WRITE pointer */ + fifo_addr[1] = fifo_addr[1] + 4; + if (fifo_addr[1] > fifo_addr[3]) + fifo_addr[1] = fifo_addr[2]; + if (fifo_addr[1] == fifo_addr[0]) + abe_dbg_error_log(ABE_FW_FIFO_WRITE_PTR_ERR); + } + /* update WRITE pointer in DMEM */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, descr_addr + + sizeof(u32), &fifo_addr[1], 4); + break; + default: + /* printf("currently only DMEM FIFO write supported ERROR\n"); */ + break; + } +} +/** + * abe_monitoring + * + * checks the internal status of ABE and HAL + */ +void abe_monitoring(void) +{ + abe_dbg_param = 0; +} +/** + * abe_format_switch + * @f: port format + * @iter: port iteration + * @mulfac: multiplication factor + * + * translates the sampling and data length to ITER number for the DMA + * and the multiplier factor to apply during data move with DMEM + * + */ +void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac) +{ + u32 n_freq; +#if FW_SCHED_LOOP_FREQ==4000 + switch (f->f) { + /* nb of samples processed by scheduling loop */ + case 8000: + n_freq = 2; + break; + case 16000: + n_freq = 4; + break; + case 24000: + n_freq = 6; + break; + case 44100: + n_freq = 12; + break; + case 96000: + n_freq = 24; + break; + default/*case 48000 */ : + n_freq = 12; + break; + } +#else + /* erroneous cases */ + n_freq = 0; +#endif + switch (f->samp_format) { + case MONO_MSB: + case MONO_RSHIFTED_16: + case STEREO_16_16: + *mulfac = 1; + break; + case STEREO_MSB: + case STEREO_RSHIFTED_16: + *mulfac = 2; + break; + case THREE_MSB: + *mulfac = 3; + break; + case FOUR_MSB: + *mulfac = 4; + break; + case FIVE_MSB: + *mulfac = 5; + break; + case SIX_MSB: + *mulfac = 6; + break; + case SEVEN_MSB: + *mulfac = 7; + break; + case EIGHT_MSB: + *mulfac = 8; + break; + case NINE_MSB: + *mulfac = 9; + break; + default: + *mulfac = 1; + break; + } + *iter = (n_freq * (*mulfac)); +} +/** + * abe_dma_port_iteration + * @f: port format + * + * translates the sampling and data length to ITER number for the DMA + */ +u32 abe_dma_port_iteration(abe_data_format_t *f) +{ + u32 iter, mulfac; + abe_format_switch(f, &iter, &mulfac); + return iter; +} +/** + * abe_dma_port_iter_factor + * @f: port format + * + * returns the multiplier factor to apply during data move with DMEM + */ +u32 abe_dma_port_iter_factor(abe_data_format_t *f) +{ + u32 iter, mulfac; + abe_format_switch(f, &iter, &mulfac); + return mulfac; +} +/** + * abe_dma_port_copy_subroutine_id + * + * @port_id: ABE port ID + * + * returns the index of the function doing the copy in I/O tasks + */ +u32 abe_dma_port_copy_subroutine_id(u32 port_id) +{ + u32 sub_id; + if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) { + switch (abe_port[port_id].format.samp_format) { + case MONO_MSB: + sub_id = D2S_MONO_MSB_CFPID; + break; + case MONO_RSHIFTED_16: + sub_id = D2S_MONO_RSHIFTED_16_CFPID; + break; + case STEREO_RSHIFTED_16: + sub_id = D2S_STEREO_RSHIFTED_16_CFPID; + break; + case STEREO_16_16: + sub_id = D2S_STEREO_16_16_CFPID; + break; + case STEREO_MSB: + sub_id = D2S_STEREO_MSB_CFPID; + break; + case SIX_MSB: + if (port_id == DMIC_PORT) { + sub_id = COPY_DMIC_CFPID; + break; + } + default: + sub_id = NULL_COPY_CFPID; + break; + } + } else { + switch (abe_port[port_id].format.samp_format) { + case MONO_MSB: + sub_id = S2D_MONO_MSB_CFPID; + break; + case MONO_RSHIFTED_16: + sub_id = S2D_MONO_RSHIFTED_16_CFPID; + break; + case STEREO_RSHIFTED_16: + sub_id = S2D_STEREO_RSHIFTED_16_CFPID; + break; + case STEREO_16_16: + sub_id = S2D_STEREO_16_16_CFPID; + break; + case STEREO_MSB: + sub_id = S2D_STEREO_MSB_CFPID; + break; + case SIX_MSB: + if (port_id == PDM_DL_PORT) { + sub_id = COPY_MCPDM_DL_CFPID; + break; + } + if (port_id == MM_UL_PORT) { + sub_id = COPY_MM_UL_CFPID; + break; + } + case THREE_MSB: + case FOUR_MSB: + case FIVE_MSB: + case SEVEN_MSB: + case EIGHT_MSB: + case NINE_MSB: + sub_id = COPY_MM_UL_CFPID; + break; + default: + sub_id = NULL_COPY_CFPID; + break; + } + } + return sub_id; +} +/** + * abe_int_2_float + * returns a mantissa on 16 bits and the exponent + * 0x4000.0000 leads to M=0x4000 X=15 + * 0x0004.0000 leads to M=0x4000 X=4 + * 0x0000.0001 leads to M=0x4000 X=-14 + * + */ +void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp) +{ + u32 i; + *exp = 0; + *mantissa = 0; + for (i = 0; i < 32; i++) { + if ((1 << i) > data) + break; + } + *exp = i - 15; + *mantissa = (*exp > 0) ? data >> (*exp) : data << (*exp); +} +/** + * abe_gain_offset + * returns the offset to firmware data structures + * + */ +void abe_gain_offset(u32 id, u32 *mixer_offset) +{ + switch (id) { + default: + case GAINS_DMIC1: + *mixer_offset = dmic1_gains_offset; + break; + case GAINS_DMIC2: + *mixer_offset = dmic2_gains_offset; + break; + case GAINS_DMIC3: + *mixer_offset = dmic3_gains_offset; + break; + case GAINS_AMIC: + *mixer_offset = amic_gains_offset; + break; + case GAINS_DL1: + *mixer_offset = dl1_gains_offset; + break; + case GAINS_DL2: + *mixer_offset = dl2_gains_offset; + break; + case GAINS_SPLIT: + *mixer_offset = splitters_gains_offset; + break; + case MIXDL1: + *mixer_offset = mixer_dl1_offset; + break; + case MIXDL2: + *mixer_offset = mixer_dl2_offset; + break; + case MIXECHO: + *mixer_offset = mixer_echo_offset; + break; + case MIXSDT: + *mixer_offset = mixer_sdt_offset; + break; + case MIXVXREC: + *mixer_offset = mixer_vxrec_offset; + break; + case MIXAUDUL: + *mixer_offset = mixer_audul_offset; + break; + } +} +/** + * abe_decide_main_port - Select stynchronization port for Event generator. + * @id: audio port name + * + * tells the FW which is the reference stream for adjusting + * the processing on 23/24/25 slots + * + * takes the first port in a list which is slave on the data interface + */ +u32 abe_valid_port_for_synchro(u32 id) +{ + if ((abe_port[id].protocol.protocol_switch == + DMAREQ_PORT_PROT) || + (abe_port[id].protocol.protocol_switch == + PINGPONG_PORT_PROT) || + (abe_port[id].status != OMAP_ABE_PORT_ACTIVITY_RUNNING)) + return 0; + else + return 1; +} +void abe_decide_main_port(void) +{ + u32 id, id_not_found; + id_not_found = 1; + for (id = 0; id < LAST_PORT_ID - 1; id++) { + if (abe_valid_port_for_synchro(abe_port_priority[id])) { + id_not_found = 0; + break; + } + } + /* if no port is currently activated, the default one is PDM_DL */ + if (id_not_found) + abe_select_main_port(PDM_DL_PORT); + else + abe_select_main_port(abe_port_priority[id]); +} diff --git a/sound/soc/omap/abe/abe_lib.h b/sound/soc/omap/abe/abe_lib.h new file mode 100644 index 00000000000..647a941482d --- /dev/null +++ b/sound/soc/omap/abe/abe_lib.h @@ -0,0 +1,122 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +/** + * abe_fprintf + * + * Parameter : + * character line to be printed + * + * Operations : + * + * Return value : + * None. + */ +void abe_fprintf(char *line); +/* + * ABE_READ_FEATURE_FROM_PORT + * + * Parameter : + * x : d + * + * Operations : + * + * + * Return value : + * + */ +void abe_read_feature_from_port(u32 x); +/* + * ABE_WRITE_FEATURE_TO_PORT + * + * Parameter : + * x : d + * + * Operations : + * + * + * Return value : + * + */ +void abe_write_feature_to_port(u32 x); +/* + * ABE_READ_FIFO + * + * Parameter : + * x : d + * + * Operations : + * + * + * Return value : + * + */ +void abe_read_fifo(u32 x); +/* + * ABE_WRITE_FIFO + * + * Parameter : + * mem_bank : currently only ABE_DMEM supported + * addr : FIFO descriptor address ( descriptor fields : READ ptr, + * WRITE ptr, FIFO START_ADDR, FIFO END_ADDR) + * data to write to FIFO + * number of 32-bit words to write to DMEM FIFO + * + * Operations : + * write DMEM FIFO and update FIFO descriptor, it is assumed that FIFO + * descriptor is located in DMEM + * + * Return value : + * none + */ +void abe_write_fifo(u32 mem_bank, u32 addr, u32 *data, u32 nb_data32); +/* + * ABE_BLOCK_COPY + * + * Parameter : + * direction of the data move (Read/Write) + * memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO + * address of the memory copy (byte addressing) + * long pointer to the data + * number of data to move + * + * Operations : + * block data move + * + * Return value : + * none + */ +void abe_block_copy(u32 direction, u32 memory_bank, u32 address, u32 *data, + u32 nb); +/* + * ABE_RESET_MEM + * + * Parameter : + * memory bank among DMEM, SMEM + * address of the memory copy (byte addressing) + * number of data to move + * + * Operations : + * reset memory + * + * Return value : + * none + */ +void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes); diff --git a/sound/soc/omap/abe/abe_main.h b/sound/soc/omap/abe/abe_main.h new file mode 100644 index 00000000000..4d60c088a80 --- /dev/null +++ b/sound/soc/omap/abe/abe_main.h @@ -0,0 +1,48 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_MAIN_H_ +#define _ABE_MAIN_H_ +#include <linux/io.h> +#include "abe_dm_addr.h" +#include "abe_sm_addr.h" +#include "abe_cm_addr.h" +#include "abe_define.h" +#include "abe_fw.h" +#include "abe_def.h" +#include "abe_typ.h" +#include "abe_ext.h" +#include "abe_dbg.h" +#include "abe_lib.h" +#include "abe_ref.h" +#include "abe_api.h" +#include "abe_typedef.h" +#include "abe_functionsid.h" +#include "abe_taskid.h" +#include "abe_initxxx_labels.h" +#include "abe_fw.h" +/* pipe connection to the TARGET simulator */ +#define ABE_DEBUG_CHECKERS 0 +/* simulator data extracted from a text-file */ +#define ABE_DEBUG_HWFILE 0 +/* low-level log files */ +#define ABE_DEBUG_LL_LOG 0 +#define ABE_DEBUG (ABE_DEBUG_CHECKERS | ABE_DEBUG_HWFILE | ABE_DEBUG_LL_LOG) +#endif /* _ABE_MAIN_H_ */ diff --git a/sound/soc/omap/abe/abe_mem.c b/sound/soc/omap/abe/abe_mem.c new file mode 100644 index 00000000000..cbd0afb8d82 --- /dev/null +++ b/sound/soc/omap/abe/abe_mem.c @@ -0,0 +1,100 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_main.h" + +/** + * abe_block_copy + * @direction: direction of the data move (Read/Write) + * @memory_bamk:memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO + * @address: address of the memory copy (byte addressing) + * @data: pointer to the data to transfer + * @nb_bytes: number of data to move + * + * Memory transfer to/from ABE to MPU + */ +void abe_block_copy(u32 direction, u32 memory_bank, u32 address, + u32 *data, u32 nb_bytes) +{ + u32 i; + u32 base_address = 0, *src_ptr, *dst_ptr, n; + switch (memory_bank) { + case ABE_PMEM: + base_address = (u32) io_base + ABE_PMEM_BASE_OFFSET_MPU; + break; + case ABE_CMEM: + base_address = (u32) io_base + ABE_CMEM_BASE_OFFSET_MPU; + break; + case ABE_SMEM: + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + break; + case ABE_DMEM: + base_address = (u32) io_base + ABE_DMEM_BASE_OFFSET_MPU; + break; + case ABE_ATC: + base_address = (u32) io_base + ABE_ATC_BASE_OFFSET_MPU; + break; + default: + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + abe_dbg_param |= ERR_LIB; + abe_dbg_error_log(ABE_BLOCK_COPY_ERR); + break; + } + if (direction == COPY_FROM_HOST_TO_ABE) { + dst_ptr = (u32 *) (base_address + address); + src_ptr = (u32 *) data; + } else { + dst_ptr = (u32 *) data; + src_ptr = (u32 *) (base_address + address); + } + n = (nb_bytes / 4); + for (i = 0; i < n; i++) + *dst_ptr++ = *src_ptr++; +} +/** + * abe_reset_mem + * + * @memory_bank: memory bank among DMEM, SMEM + * @address: address of the memory copy (byte addressing) + * @nb_bytes: number of data to move + * + * Reset ABE memory + */ +void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes) +{ + u32 i; + u32 *dst_ptr, n; + u32 base_address = 0; + switch (memory_bank) { + case ABE_SMEM: + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + break; + case ABE_DMEM: + base_address = (u32) io_base + ABE_DMEM_BASE_OFFSET_MPU; + break; + case ABE_CMEM: + base_address = (u32) io_base + ABE_CMEM_BASE_OFFSET_MPU; + break; + } + dst_ptr = (u32 *) (base_address + address); + n = (nb_bytes / 4); + for (i = 0; i < n; i++) + *dst_ptr++ = 0; +} diff --git a/sound/soc/omap/abe/abe_ref.h b/sound/soc/omap/abe/abe_ref.h new file mode 100644 index 00000000000..91f8e472dc0 --- /dev/null +++ b/sound/soc/omap/abe/abe_ref.h @@ -0,0 +1,158 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_REF_H_ +#define _ABE_REF_H_ +/* + * 'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ... + */ +/* + * HAL EXTERNAL AP + */ +/* + * HAL INTERNAL AP + */ +void abe_decide_main_port(void); +void abe_gain_offset(u32 id, u32 *mixer_offset); +void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp); +void abe_reset_gain_mixer(u32 id, u32 p); +void abe_load_embeddded_patterns(void); +void abe_build_scheduler_table(void); +void abe_reset_one_feature(u32 x); +void abe_reset_all_features(void); +void abe_reset_all_ports(void); +void abe_reset_all_fifo(void); +void abe_reset_all_sequence(void); +u32 abe_dma_port_iteration(abe_data_format_t *format); +void abe_read_sys_clock(u32 *time); +void abe_enable_dma_request(u32 id); +void abe_disable_dma_request(u32 id); +void abe_enable_atc(u32 id); +void abe_disable_atc(u32 id); +void abe_init_atc(u32 id); +void abe_init_io_tasks(u32 id, abe_data_format_t *format, + abe_port_protocol_t *prot); +void abe_enable_pp_io_task(u32 id); +void abe_disable_pp_io_task(u32 id); +void abe_init_dma_t(u32 id, abe_port_protocol_t *prot); +u32 abe_dma_port_iter_factor(abe_data_format_t *f); +u32 abe_dma_port_copy_subroutine_id(u32 i); +void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4); +void abe_monitoring(void); +void abe_lock_execution(void); +void abe_unlock_execution(void); +void abe_hw_configuration(void); +void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params); +abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n); +void abe_irq_ping_pong(void); +void abe_irq_check_for_sequences(u32 seq_info); +void abe_default_irq_pingpong_player(void); +void abe_default_irq_pingpong_player_32bits(void); +void abe_rshifted16_irq_pingpong_player_32bits(void); +void abe_1616_irq_pingpong_player_1616bits(void); +void abe_default_irq_aps_adaptation(void); +void abe_irq_aps(u32 aps_info); +void abe_clean_temporary_buffers(u32 id); +void abe_dbg_log(u32 x, u32 y, u32 z, u32 t); +void abe_dbg_error_log(u32 x); +void abe_init_asrc_vx_dl(s32 dppm); +void abe_init_asrc_vx_ul(s32 dppm); +void abe_init_asrc_mm_ext_in(s32 dppm); +void abe_init_asrc_bt_ul(s32 dppm); +void abe_init_asrc_bt_dl(s32 dppm); +//u8 *memmove(u8 *dst, u8 *src, u32 n); +//u32 __get_unaligned_memmove32(void *p); +//void __put_unaligned_memmove32(u32 val, void *p); +/* + * HAL INTERNAL DATA + */ +extern void __iomem *io_base; +extern u16 MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT]; +extern ABE_SIODescriptor sio_desc; +extern ABE_SPingPongDescriptor desc_pp; +extern abe_satcdescriptor_aess atc_desc; +extern const u32 abe_port_priority[LAST_PORT_ID - 1]; +extern u32 abe_compensated_mixer_gain; +extern u8 abe_muted_gains_indicator[MAX_NBGAIN_CMEM]; +extern u32 abe_desired_gains_decibel[MAX_NBGAIN_CMEM]; +extern u32 abe_muted_gains_decibel[MAX_NBGAIN_CMEM]; +extern u32 abe_desired_gains_linear[MAX_NBGAIN_CMEM]; +extern u32 abe_desired_ramp_delay_ms[MAX_NBGAIN_CMEM]; +extern u32 pdm_dl1_status; +extern u32 pdm_dl2_status; +extern u32 pdm_vib_status; +extern const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE]; +extern u32 abe_firmware_version_number; +extern const u32 abe_atc_srcid[]; +extern const u32 abe_atc_dstid[]; +extern abe_port_t abe_port[]; +extern abe_feature_t feature[]; +extern const abe_port_t abe_port_init[]; +extern abe_feature_t all_feature[]; +extern const abe_feature_t all_feature_init[]; +extern abe_seq_t all_sequence[]; +extern const abe_seq_t all_sequence_init[]; +extern const abe_router_t abe_router_ul_table_preset + [NBROUTE_CONFIG][NBROUTE_UL]; +extern abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL]; +extern u32 abe_dbg_output; +extern u32 abe_dbg_mask; +extern u32 abe_dbg_activity_log[D_DEBUG_HAL_TASK_sizeof]; +extern u32 abe_dbg_activity_log_write_pointer; +extern u32 abe_dbg_param; +extern u32 abe_current_event_id; +extern const abe_sequence_t seq_null; +/* table of new subroutines called in the sequence */ +extern abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE]; +/* number of parameters per calls */ +extern u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE]; +extern u32 abe_subroutine_id[MAXNBSUBROUTINE]; +extern u32 *abe_all_subroutine_params[MAXNBSUBROUTINE]; +extern u32 abe_subroutine_write_pointer; +extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; +extern u32 abe_sequence_write_pointer; +/* current number of pending sequences (avoids to look in the table) */ +extern u32 abe_nb_pending_sequences; +/* pending sequences due to ressource collision */ +extern u32 abe_pending_sequences[MAXNBSEQUENCE]; +/* mask of unsharable ressources among other sequences */ +extern u32 abe_global_sequence_mask; +/* table of active sequences */ +extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS]; +/* index of the plugged subroutine doing ping-pong cache-flush + DMEM accesses */ +extern u32 abe_irq_pingpong_player_id; +extern u32 abe_irq_aps_adaptation_id; +/* base addresses of the ping pong buffers */ +extern u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS]; +/* size of each ping/pong buffers */ +extern u32 abe_size_pingpong; +/* number of ping/pong buffer being used */ +extern u32 abe_nb_pingpong; +/* circular read pointer to IRQ/DBG DMEM buffer */ +extern u32 abe_irq_dbg_read_ptr; +/* extern const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof]; */ +extern const u32 abe_db2lin_table[]; +extern const u32 abe_alpha_iir[64]; +extern const u32 abe_1_alpha_iir[64]; +#endif/* _ABE_REF_H_ */ diff --git a/sound/soc/omap/abe/abe_seq.c b/sound/soc/omap/abe/abe_seq.c new file mode 100644 index 00000000000..797fef3bd78 --- /dev/null +++ b/sound/soc/omap/abe/abe_seq.c @@ -0,0 +1,248 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include <linux/module.h> +#include "abe_main.h" +/** + * abe_null_subroutine + * + */ +void abe_null_subroutine_0(void) +{ +} +void abe_null_subroutine_2(u32 a, u32 b) +{ +} +void abe_null_subroutine_4(u32 a, u32 b, u32 c, u32 d) +{ +} +/** + * abe_init_subroutine_table - initializes the default table of pointers + * to subroutines + * + * initializes the default table of pointers to subroutines + * + */ +void abe_init_subroutine_table(void) +{ + u32 id; + /* reset the table's pointers */ + abe_subroutine_write_pointer = 0; + /* the first index is the NULL task */ + abe_add_subroutine(&id, (abe_subroutine2) abe_null_subroutine_2, + SUB_0_PARAM, (u32 *) 0); + /* write mixer has 4 parameters */ + abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]), + (abe_subroutine2) abe_write_mixer, SUB_4_PARAM, + (u32 *) 0); + /* ping-pong player IRQ */ + abe_add_subroutine(&abe_irq_pingpong_player_id, + (abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM, + (u32 *) 0); + abe_add_subroutine(&abe_irq_aps_adaptation_id, + (abe_subroutine2) abe_default_irq_aps_adaptation, + SUB_0_PARAM, (u32 *) 0); +} +/** + * abe_add_subroutine + * @id: ABE port id + * @f: pointer to the subroutines + * @nparam: number of parameters + * @params: pointer to the psrameters + * + * add one function pointer more and returns the index to it + */ +void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params) +{ + u32 i, i_found; + if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) || ((u32) f == 0)) { + abe_dbg_param |= ERR_SEQ; + abe_dbg_error_log(ABE_PARAMETER_OVERFLOW); + } else { + /* search if this subroutine address was not already + * declared, then return the previous index + */ + for (i_found = abe_subroutine_write_pointer, i = 0; + i < abe_subroutine_write_pointer; i++) { + if (f == abe_all_subsubroutine[i]) + i_found = i; + } + if (i_found == abe_subroutine_write_pointer) { + *id = abe_subroutine_write_pointer; + abe_all_subsubroutine + [abe_subroutine_write_pointer] = (f); + abe_all_subroutine_params + [abe_subroutine_write_pointer] = params; + abe_all_subsubroutine_nparam + [abe_subroutine_write_pointer] = nparam; + abe_subroutine_write_pointer++; + } else { + abe_all_subroutine_params[i_found] = params; + *id = i_found; + } + } +} + +EXPORT_SYMBOL_GPL(abe_add_subroutine); + +/** + * abe_add_sequence + * @id: returned sequence index after pluging a new sequence (index in the tables) + * @s: sequence to be inserted + * + * Load a time-sequenced operations. + */ +void abe_add_sequence(u32 *id, abe_sequence_t *s) +{ + abe_seq_t *seq_src, *seq_dst; + u32 i, no_end_of_sequence_found; + seq_src = &(s->seq1); + seq_dst = &((abe_all_sequence[abe_sequence_write_pointer]).seq1); + if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((u32) s == 0)) { + abe_dbg_param |= ERR_SEQ; + abe_dbg_error_log(ABE_PARAMETER_OVERFLOW); + } else { + *id = abe_subroutine_write_pointer; + /* copy the mask */ + (abe_all_sequence[abe_sequence_write_pointer]).mask = s->mask; + for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS; + i++, seq_src++, seq_dst++) { + /* sequence copied line by line */ + (*seq_dst) = (*seq_src); + /* stop when the line start with time=(-1) */ + if ((*(s32 *) seq_src) == (-1)) { + /* stop when the line start with time=(-1) */ + no_end_of_sequence_found = 0; + break; + } + } + abe_subroutine_write_pointer++; + if (no_end_of_sequence_found) + abe_dbg_error_log(ABE_SEQTOOLONG); + } +} +/** + * abe_reset_one_sequence + * @id: sequence ID + * + * load default configuration for that sequence + * kill running activities + */ +void abe_reset_one_sequence(u32 id) +{ +} +/** + * abe_reset_all_sequence + * + * load default configuration for all sequences + * kill any running activities + */ +void abe_reset_all_sequence(void) +{ + u32 i; + abe_init_subroutine_table(); + /* arrange to have the first sequence index=0 to the NULL operation + sequence */ + abe_add_sequence(&i, (abe_sequence_t *) &seq_null); + /* reset the the collision protection mask */ + abe_global_sequence_mask = 0; + /* reset the pending sequences list */ + for (abe_nb_pending_sequences = i = 0; i < MAXNBSEQUENCE; i++) + abe_pending_sequences[i] = 0; +} +/** + * abe_call_subroutine + * @idx: index to the table of all registered Call-backs and subroutines + * + * run and log a subroutine + */ +void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4) +{ + abe_subroutine0 f0; + abe_subroutine1 f1; + abe_subroutine2 f2; + abe_subroutine3 f3; + abe_subroutine4 f4; + u32 *params; + if (idx >= MAXNBSUBROUTINE) + return; + switch (idx) { + /* call the subroutines defined at compilation time + (const .. sequences) */ +#if 0 + case SUB_WRITE_MIXER_DL1: + abe_write_mixer_dl1(p1, p2, p3) + abe_fprintf("write_mixer"); + break; +#endif + /* call the subroutines defined at execution time + (dynamic sequences) */ + default: + switch (abe_all_subsubroutine_nparam[idx]) { + case SUB_0_PARAM: + f0 = (abe_subroutine0) abe_all_subsubroutine[idx]; + (*f0) (); + break; + case SUB_1_PARAM: + f1 = (abe_subroutine1) abe_all_subsubroutine[idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32 *) 0) + p1 = params[0]; + (*f1) (p1); + break; + case SUB_2_PARAM: + f2 = abe_all_subsubroutine[idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32 *) 0) { + p1 = params[0]; + p2 = params[1]; + } + (*f2) (p1, p2); + break; + case SUB_3_PARAM: + f3 = (abe_subroutine3) abe_all_subsubroutine[idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32 *) 0) { + p1 = params[0]; + p2 = params[1]; + p3 = params[2]; + } + (*f3) (p1, p2, p3); + break; + case SUB_4_PARAM: + f4 = (abe_subroutine4) abe_all_subsubroutine[idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32 *) 0) { + p1 = params[0]; + p2 = params[1]; + p3 = params[2]; + p4 = params[3]; + } + (*f4) (p1, p2, p3, p4); + break; + default: + break; + } + } +} diff --git a/sound/soc/omap/abe/abe_sm_addr.h b/sound/soc/omap/abe/abe_sm_addr.h new file mode 100644 index 00000000000..53447b64ec3 --- /dev/null +++ b/sound/soc/omap/abe/abe_sm_addr.h @@ -0,0 +1,503 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_SM_ADDR_H_ +#define _ABE_SM_ADDR_H_ +#define init_SM_ADDR 0 +#define init_SM_ADDR_END 309 +#define init_SM_sizeof 310 +#define S_Data0_ADDR 310 +#define S_Data0_ADDR_END 310 +#define S_Data0_sizeof 1 +#define S_Temp_ADDR 311 +#define S_Temp_ADDR_END 311 +#define S_Temp_sizeof 1 +#define S_PhoenixOffset_ADDR 312 +#define S_PhoenixOffset_ADDR_END 312 +#define S_PhoenixOffset_sizeof 1 +#define S_GTarget1_ADDR 313 +#define S_GTarget1_ADDR_END 319 +#define S_GTarget1_sizeof 7 +#define S_Gtarget_DL1_ADDR 320 +#define S_Gtarget_DL1_ADDR_END 321 +#define S_Gtarget_DL1_sizeof 2 +#define S_Gtarget_DL2_ADDR 322 +#define S_Gtarget_DL2_ADDR_END 323 +#define S_Gtarget_DL2_sizeof 2 +#define S_Gtarget_Echo_ADDR 324 +#define S_Gtarget_Echo_ADDR_END 324 +#define S_Gtarget_Echo_sizeof 1 +#define S_Gtarget_SDT_ADDR 325 +#define S_Gtarget_SDT_ADDR_END 325 +#define S_Gtarget_SDT_sizeof 1 +#define S_Gtarget_VxRec_ADDR 326 +#define S_Gtarget_VxRec_ADDR_END 327 +#define S_Gtarget_VxRec_sizeof 2 +#define S_Gtarget_UL_ADDR 328 +#define S_Gtarget_UL_ADDR_END 329 +#define S_Gtarget_UL_sizeof 2 +#define S_Gtarget_unused_ADDR 330 +#define S_Gtarget_unused_ADDR_END 330 +#define S_Gtarget_unused_sizeof 1 +#define S_GCurrent_ADDR 331 +#define S_GCurrent_ADDR_END 348 +#define S_GCurrent_sizeof 18 +#define S_GAIN_ONE_ADDR 349 +#define S_GAIN_ONE_ADDR_END 349 +#define S_GAIN_ONE_sizeof 1 +#define S_Tones_ADDR 350 +#define S_Tones_ADDR_END 361 +#define S_Tones_sizeof 12 +#define S_VX_DL_ADDR 362 +#define S_VX_DL_ADDR_END 373 +#define S_VX_DL_sizeof 12 +#define S_MM_UL2_ADDR 374 +#define S_MM_UL2_ADDR_END 385 +#define S_MM_UL2_sizeof 12 +#define S_MM_DL_ADDR 386 +#define S_MM_DL_ADDR_END 397 +#define S_MM_DL_sizeof 12 +#define S_DL1_M_Out_ADDR 398 +#define S_DL1_M_Out_ADDR_END 409 +#define S_DL1_M_Out_sizeof 12 +#define S_DL2_M_Out_ADDR 410 +#define S_DL2_M_Out_ADDR_END 421 +#define S_DL2_M_Out_sizeof 12 +#define S_Echo_M_Out_ADDR 422 +#define S_Echo_M_Out_ADDR_END 433 +#define S_Echo_M_Out_sizeof 12 +#define S_SDT_M_Out_ADDR 434 +#define S_SDT_M_Out_ADDR_END 445 +#define S_SDT_M_Out_sizeof 12 +#define S_VX_UL_ADDR 446 +#define S_VX_UL_ADDR_END 457 +#define S_VX_UL_sizeof 12 +#define S_VX_UL_M_ADDR 458 +#define S_VX_UL_M_ADDR_END 469 +#define S_VX_UL_M_sizeof 12 +#define S_BT_DL_ADDR 470 +#define S_BT_DL_ADDR_END 481 +#define S_BT_DL_sizeof 12 +#define S_BT_UL_ADDR 482 +#define S_BT_UL_ADDR_END 493 +#define S_BT_UL_sizeof 12 +#define S_BT_DL_8k_ADDR 494 +#define S_BT_DL_8k_ADDR_END 496 +#define S_BT_DL_8k_sizeof 3 +#define S_BT_DL_16k_ADDR 497 +#define S_BT_DL_16k_ADDR_END 501 +#define S_BT_DL_16k_sizeof 5 +#define S_BT_UL_8k_ADDR 502 +#define S_BT_UL_8k_ADDR_END 503 +#define S_BT_UL_8k_sizeof 2 +#define S_BT_UL_16k_ADDR 504 +#define S_BT_UL_16k_ADDR_END 507 +#define S_BT_UL_16k_sizeof 4 +#define S_SDT_F_ADDR 508 +#define S_SDT_F_ADDR_END 519 +#define S_SDT_F_sizeof 12 +#define S_SDT_F_data_ADDR 520 +#define S_SDT_F_data_ADDR_END 528 +#define S_SDT_F_data_sizeof 9 +#define S_MM_DL_OSR_ADDR 529 +#define S_MM_DL_OSR_ADDR_END 552 +#define S_MM_DL_OSR_sizeof 24 +#define S_24_zeros_ADDR 553 +#define S_24_zeros_ADDR_END 576 +#define S_24_zeros_sizeof 24 +#define S_DMIC1_ADDR 577 +#define S_DMIC1_ADDR_END 588 +#define S_DMIC1_sizeof 12 +#define S_DMIC2_ADDR 589 +#define S_DMIC2_ADDR_END 600 +#define S_DMIC2_sizeof 12 +#define S_DMIC3_ADDR 601 +#define S_DMIC3_ADDR_END 612 +#define S_DMIC3_sizeof 12 +#define S_AMIC_ADDR 613 +#define S_AMIC_ADDR_END 624 +#define S_AMIC_sizeof 12 +#define S_DMIC1_L_ADDR 625 +#define S_DMIC1_L_ADDR_END 636 +#define S_DMIC1_L_sizeof 12 +#define S_DMIC1_R_ADDR 637 +#define S_DMIC1_R_ADDR_END 648 +#define S_DMIC1_R_sizeof 12 +#define S_DMIC2_L_ADDR 649 +#define S_DMIC2_L_ADDR_END 660 +#define S_DMIC2_L_sizeof 12 +#define S_DMIC2_R_ADDR 661 +#define S_DMIC2_R_ADDR_END 672 +#define S_DMIC2_R_sizeof 12 +#define S_DMIC3_L_ADDR 673 +#define S_DMIC3_L_ADDR_END 684 +#define S_DMIC3_L_sizeof 12 +#define S_DMIC3_R_ADDR 685 +#define S_DMIC3_R_ADDR_END 696 +#define S_DMIC3_R_sizeof 12 +#define S_BT_UL_L_ADDR 697 +#define S_BT_UL_L_ADDR_END 708 +#define S_BT_UL_L_sizeof 12 +#define S_BT_UL_R_ADDR 709 +#define S_BT_UL_R_ADDR_END 720 +#define S_BT_UL_R_sizeof 12 +#define S_AMIC_L_ADDR 721 +#define S_AMIC_L_ADDR_END 732 +#define S_AMIC_L_sizeof 12 +#define S_AMIC_R_ADDR 733 +#define S_AMIC_R_ADDR_END 744 +#define S_AMIC_R_sizeof 12 +#define S_EchoRef_L_ADDR 745 +#define S_EchoRef_L_ADDR_END 756 +#define S_EchoRef_L_sizeof 12 +#define S_EchoRef_R_ADDR 757 +#define S_EchoRef_R_ADDR_END 768 +#define S_EchoRef_R_sizeof 12 +#define S_MM_DL_L_ADDR 769 +#define S_MM_DL_L_ADDR_END 780 +#define S_MM_DL_L_sizeof 12 +#define S_MM_DL_R_ADDR 781 +#define S_MM_DL_R_ADDR_END 792 +#define S_MM_DL_R_sizeof 12 +#define S_MM_UL_ADDR 793 +#define S_MM_UL_ADDR_END 912 +#define S_MM_UL_sizeof 120 +#define S_AMIC_96k_ADDR 913 +#define S_AMIC_96k_ADDR_END 936 +#define S_AMIC_96k_sizeof 24 +#define S_DMIC0_96k_ADDR 937 +#define S_DMIC0_96k_ADDR_END 960 +#define S_DMIC0_96k_sizeof 24 +#define S_DMIC1_96k_ADDR 961 +#define S_DMIC1_96k_ADDR_END 984 +#define S_DMIC1_96k_sizeof 24 +#define S_DMIC2_96k_ADDR 985 +#define S_DMIC2_96k_ADDR_END 1008 +#define S_DMIC2_96k_sizeof 24 +#define S_UL_VX_UL_48_8K_ADDR 1009 +#define S_UL_VX_UL_48_8K_ADDR_END 1020 +#define S_UL_VX_UL_48_8K_sizeof 12 +#define S_UL_VX_UL_48_16K_ADDR 1021 +#define S_UL_VX_UL_48_16K_ADDR_END 1032 +#define S_UL_VX_UL_48_16K_sizeof 12 +#define S_UL_MIC_48K_ADDR 1033 +#define S_UL_MIC_48K_ADDR_END 1044 +#define S_UL_MIC_48K_sizeof 12 +#define S_Voice_8k_UL_ADDR 1045 +#define S_Voice_8k_UL_ADDR_END 1047 +#define S_Voice_8k_UL_sizeof 3 +#define S_Voice_8k_DL_ADDR 1048 +#define S_Voice_8k_DL_ADDR_END 1049 +#define S_Voice_8k_DL_sizeof 2 +#define S_McPDM_Out1_ADDR 1050 +#define S_McPDM_Out1_ADDR_END 1073 +#define S_McPDM_Out1_sizeof 24 +#define S_McPDM_Out2_ADDR 1074 +#define S_McPDM_Out2_ADDR_END 1097 +#define S_McPDM_Out2_sizeof 24 +#define S_McPDM_Out3_ADDR 1098 +#define S_McPDM_Out3_ADDR_END 1121 +#define S_McPDM_Out3_sizeof 24 +#define S_Voice_16k_UL_ADDR 1122 +#define S_Voice_16k_UL_ADDR_END 1126 +#define S_Voice_16k_UL_sizeof 5 +#define S_Voice_16k_DL_ADDR 1127 +#define S_Voice_16k_DL_ADDR_END 1130 +#define S_Voice_16k_DL_sizeof 4 +#define S_XinASRC_DL_VX_ADDR 1131 +#define S_XinASRC_DL_VX_ADDR_END 1170 +#define S_XinASRC_DL_VX_sizeof 40 +#define S_XinASRC_UL_VX_ADDR 1171 +#define S_XinASRC_UL_VX_ADDR_END 1210 +#define S_XinASRC_UL_VX_sizeof 40 +#define S_XinASRC_MM_EXT_IN_ADDR 1211 +#define S_XinASRC_MM_EXT_IN_ADDR_END 1250 +#define S_XinASRC_MM_EXT_IN_sizeof 40 +#define S_VX_REC_ADDR 1251 +#define S_VX_REC_ADDR_END 1262 +#define S_VX_REC_sizeof 12 +#define S_VX_REC_L_ADDR 1263 +#define S_VX_REC_L_ADDR_END 1274 +#define S_VX_REC_L_sizeof 12 +#define S_VX_REC_R_ADDR 1275 +#define S_VX_REC_R_ADDR_END 1286 +#define S_VX_REC_R_sizeof 12 +#define S_DL2_M_L_ADDR 1287 +#define S_DL2_M_L_ADDR_END 1298 +#define S_DL2_M_L_sizeof 12 +#define S_DL2_M_R_ADDR 1299 +#define S_DL2_M_R_ADDR_END 1310 +#define S_DL2_M_R_sizeof 12 +#define S_DL2_M_LR_EQ_data_ADDR 1311 +#define S_DL2_M_LR_EQ_data_ADDR_END 1335 +#define S_DL2_M_LR_EQ_data_sizeof 25 +#define S_DL1_M_EQ_data_ADDR 1336 +#define S_DL1_M_EQ_data_ADDR_END 1360 +#define S_DL1_M_EQ_data_sizeof 25 +#define S_EARP_48_96_LP_data_ADDR 1361 +#define S_EARP_48_96_LP_data_ADDR_END 1375 +#define S_EARP_48_96_LP_data_sizeof 15 +#define S_IHF_48_96_LP_data_ADDR 1376 +#define S_IHF_48_96_LP_data_ADDR_END 1390 +#define S_IHF_48_96_LP_data_sizeof 15 +#define S_VX_UL_8_TEMP_ADDR 1391 +#define S_VX_UL_8_TEMP_ADDR_END 1392 +#define S_VX_UL_8_TEMP_sizeof 2 +#define S_VX_UL_16_TEMP_ADDR 1393 +#define S_VX_UL_16_TEMP_ADDR_END 1396 +#define S_VX_UL_16_TEMP_sizeof 4 +#define S_VX_DL_8_48_LP_data_ADDR 1397 +#define S_VX_DL_8_48_LP_data_ADDR_END 1407 +#define S_VX_DL_8_48_LP_data_sizeof 11 +#define S_VX_DL_8_48_HP_data_ADDR 1408 +#define S_VX_DL_8_48_HP_data_ADDR_END 1414 +#define S_VX_DL_8_48_HP_data_sizeof 7 +#define S_VX_DL_16_48_LP_data_ADDR 1415 +#define S_VX_DL_16_48_LP_data_ADDR_END 1425 +#define S_VX_DL_16_48_LP_data_sizeof 11 +#define S_VX_DL_16_48_HP_data_ADDR 1426 +#define S_VX_DL_16_48_HP_data_ADDR_END 1430 +#define S_VX_DL_16_48_HP_data_sizeof 5 +#define S_VX_UL_48_8_LP_data_ADDR 1431 +#define S_VX_UL_48_8_LP_data_ADDR_END 1441 +#define S_VX_UL_48_8_LP_data_sizeof 11 +#define S_VX_UL_48_8_HP_data_ADDR 1442 +#define S_VX_UL_48_8_HP_data_ADDR_END 1448 +#define S_VX_UL_48_8_HP_data_sizeof 7 +#define S_VX_UL_48_16_LP_data_ADDR 1449 +#define S_VX_UL_48_16_LP_data_ADDR_END 1459 +#define S_VX_UL_48_16_LP_data_sizeof 11 +#define S_VX_UL_48_16_HP_data_ADDR 1460 +#define S_VX_UL_48_16_HP_data_ADDR_END 1466 +#define S_VX_UL_48_16_HP_data_sizeof 7 +#define S_BT_UL_8_48_LP_data_ADDR 1467 +#define S_BT_UL_8_48_LP_data_ADDR_END 1477 +#define S_BT_UL_8_48_LP_data_sizeof 11 +#define S_BT_UL_8_48_HP_data_ADDR 1478 +#define S_BT_UL_8_48_HP_data_ADDR_END 1484 +#define S_BT_UL_8_48_HP_data_sizeof 7 +#define S_BT_UL_16_48_LP_data_ADDR 1485 +#define S_BT_UL_16_48_LP_data_ADDR_END 1495 +#define S_BT_UL_16_48_LP_data_sizeof 11 +#define S_BT_UL_16_48_HP_data_ADDR 1496 +#define S_BT_UL_16_48_HP_data_ADDR_END 1500 +#define S_BT_UL_16_48_HP_data_sizeof 5 +#define S_BT_DL_48_8_LP_data_ADDR 1501 +#define S_BT_DL_48_8_LP_data_ADDR_END 1511 +#define S_BT_DL_48_8_LP_data_sizeof 11 +#define S_BT_DL_48_8_HP_data_ADDR 1512 +#define S_BT_DL_48_8_HP_data_ADDR_END 1518 +#define S_BT_DL_48_8_HP_data_sizeof 7 +#define S_BT_DL_48_16_LP_data_ADDR 1519 +#define S_BT_DL_48_16_LP_data_ADDR_END 1529 +#define S_BT_DL_48_16_LP_data_sizeof 11 +#define S_BT_DL_48_16_HP_data_ADDR 1530 +#define S_BT_DL_48_16_HP_data_ADDR_END 1534 +#define S_BT_DL_48_16_HP_data_sizeof 5 +#define S_ECHO_REF_48_8_LP_data_ADDR 1535 +#define S_ECHO_REF_48_8_LP_data_ADDR_END 1545 +#define S_ECHO_REF_48_8_LP_data_sizeof 11 +#define S_ECHO_REF_48_8_HP_data_ADDR 1546 +#define S_ECHO_REF_48_8_HP_data_ADDR_END 1552 +#define S_ECHO_REF_48_8_HP_data_sizeof 7 +#define S_ECHO_REF_48_16_LP_data_ADDR 1553 +#define S_ECHO_REF_48_16_LP_data_ADDR_END 1563 +#define S_ECHO_REF_48_16_LP_data_sizeof 11 +#define S_ECHO_REF_48_16_HP_data_ADDR 1564 +#define S_ECHO_REF_48_16_HP_data_ADDR_END 1568 +#define S_ECHO_REF_48_16_HP_data_sizeof 5 +#define S_APS_IIRmem1_ADDR 1569 +#define S_APS_IIRmem1_ADDR_END 1577 +#define S_APS_IIRmem1_sizeof 9 +#define S_APS_M_IIRmem2_ADDR 1578 +#define S_APS_M_IIRmem2_ADDR_END 1580 +#define S_APS_M_IIRmem2_sizeof 3 +#define S_APS_C_IIRmem2_ADDR 1581 +#define S_APS_C_IIRmem2_ADDR_END 1583 +#define S_APS_C_IIRmem2_sizeof 3 +#define S_APS_DL1_OutSamples_ADDR 1584 +#define S_APS_DL1_OutSamples_ADDR_END 1585 +#define S_APS_DL1_OutSamples_sizeof 2 +#define S_APS_DL1_COIL_OutSamples_ADDR 1586 +#define S_APS_DL1_COIL_OutSamples_ADDR_END 1587 +#define S_APS_DL1_COIL_OutSamples_sizeof 2 +#define S_APS_DL2_L_OutSamples_ADDR 1588 +#define S_APS_DL2_L_OutSamples_ADDR_END 1589 +#define S_APS_DL2_L_OutSamples_sizeof 2 +#define S_APS_DL2_L_COIL_OutSamples_ADDR 1590 +#define S_APS_DL2_L_COIL_OutSamples_ADDR_END 1591 +#define S_APS_DL2_L_COIL_OutSamples_sizeof 2 +#define S_APS_DL2_R_OutSamples_ADDR 1592 +#define S_APS_DL2_R_OutSamples_ADDR_END 1593 +#define S_APS_DL2_R_OutSamples_sizeof 2 +#define S_APS_DL2_R_COIL_OutSamples_ADDR 1594 +#define S_APS_DL2_R_COIL_OutSamples_ADDR_END 1595 +#define S_APS_DL2_R_COIL_OutSamples_sizeof 2 +#define S_XinASRC_ECHO_REF_ADDR 1596 +#define S_XinASRC_ECHO_REF_ADDR_END 1635 +#define S_XinASRC_ECHO_REF_sizeof 40 +#define S_ECHO_REF_16K_ADDR 1636 +#define S_ECHO_REF_16K_ADDR_END 1640 +#define S_ECHO_REF_16K_sizeof 5 +#define S_ECHO_REF_8K_ADDR 1641 +#define S_ECHO_REF_8K_ADDR_END 1643 +#define S_ECHO_REF_8K_sizeof 3 +#define S_DL1_EQ_ADDR 1644 +#define S_DL1_EQ_ADDR_END 1655 +#define S_DL1_EQ_sizeof 12 +#define S_DL2_EQ_ADDR 1656 +#define S_DL2_EQ_ADDR_END 1667 +#define S_DL2_EQ_sizeof 12 +#define S_DL1_GAIN_out_ADDR 1668 +#define S_DL1_GAIN_out_ADDR_END 1679 +#define S_DL1_GAIN_out_sizeof 12 +#define S_DL2_GAIN_out_ADDR 1680 +#define S_DL2_GAIN_out_ADDR_END 1691 +#define S_DL2_GAIN_out_sizeof 12 +#define S_APS_DL2_L_IIRmem1_ADDR 1692 +#define S_APS_DL2_L_IIRmem1_ADDR_END 1700 +#define S_APS_DL2_L_IIRmem1_sizeof 9 +#define S_APS_DL2_R_IIRmem1_ADDR 1701 +#define S_APS_DL2_R_IIRmem1_ADDR_END 1709 +#define S_APS_DL2_R_IIRmem1_sizeof 9 +#define S_APS_DL2_L_M_IIRmem2_ADDR 1710 +#define S_APS_DL2_L_M_IIRmem2_ADDR_END 1712 +#define S_APS_DL2_L_M_IIRmem2_sizeof 3 +#define S_APS_DL2_R_M_IIRmem2_ADDR 1713 +#define S_APS_DL2_R_M_IIRmem2_ADDR_END 1715 +#define S_APS_DL2_R_M_IIRmem2_sizeof 3 +#define S_APS_DL2_L_C_IIRmem2_ADDR 1716 +#define S_APS_DL2_L_C_IIRmem2_ADDR_END 1718 +#define S_APS_DL2_L_C_IIRmem2_sizeof 3 +#define S_APS_DL2_R_C_IIRmem2_ADDR 1719 +#define S_APS_DL2_R_C_IIRmem2_ADDR_END 1721 +#define S_APS_DL2_R_C_IIRmem2_sizeof 3 +#define S_DL1_APS_ADDR 1722 +#define S_DL1_APS_ADDR_END 1733 +#define S_DL1_APS_sizeof 12 +#define S_DL2_L_APS_ADDR 1734 +#define S_DL2_L_APS_ADDR_END 1745 +#define S_DL2_L_APS_sizeof 12 +#define S_DL2_R_APS_ADDR 1746 +#define S_DL2_R_APS_ADDR_END 1757 +#define S_DL2_R_APS_sizeof 12 +#define S_APS_DL1_EQ_data_ADDR 1758 +#define S_APS_DL1_EQ_data_ADDR_END 1766 +#define S_APS_DL1_EQ_data_sizeof 9 +#define S_APS_DL2_EQ_data_ADDR 1767 +#define S_APS_DL2_EQ_data_ADDR_END 1775 +#define S_APS_DL2_EQ_data_sizeof 9 +#define S_DC_DCvalue_ADDR 1776 +#define S_DC_DCvalue_ADDR_END 1776 +#define S_DC_DCvalue_sizeof 1 +#define S_VIBRA_ADDR 1777 +#define S_VIBRA_ADDR_END 1782 +#define S_VIBRA_sizeof 6 +#define S_Vibra2_in_ADDR 1783 +#define S_Vibra2_in_ADDR_END 1788 +#define S_Vibra2_in_sizeof 6 +#define S_Vibra2_addr_ADDR 1789 +#define S_Vibra2_addr_ADDR_END 1789 +#define S_Vibra2_addr_sizeof 1 +#define S_VibraCtrl_forRightSM_ADDR 1790 +#define S_VibraCtrl_forRightSM_ADDR_END 1813 +#define S_VibraCtrl_forRightSM_sizeof 24 +#define S_Rnoise_mem_ADDR 1814 +#define S_Rnoise_mem_ADDR_END 1814 +#define S_Rnoise_mem_sizeof 1 +#define S_Ctrl_ADDR 1815 +#define S_Ctrl_ADDR_END 1832 +#define S_Ctrl_sizeof 18 +#define S_Vibra1_in_ADDR 1833 +#define S_Vibra1_in_ADDR_END 1838 +#define S_Vibra1_in_sizeof 6 +#define S_Vibra1_temp_ADDR 1839 +#define S_Vibra1_temp_ADDR_END 1862 +#define S_Vibra1_temp_sizeof 24 +#define S_VibraCtrl_forLeftSM_ADDR 1863 +#define S_VibraCtrl_forLeftSM_ADDR_END 1886 +#define S_VibraCtrl_forLeftSM_sizeof 24 +#define S_Vibra1_mem_ADDR 1887 +#define S_Vibra1_mem_ADDR_END 1897 +#define S_Vibra1_mem_sizeof 11 +#define S_VibraCtrl_Stereo_ADDR 1898 +#define S_VibraCtrl_Stereo_ADDR_END 1921 +#define S_VibraCtrl_Stereo_sizeof 24 +#define S_AMIC_96_48_data_ADDR 1922 +#define S_AMIC_96_48_data_ADDR_END 1940 +#define S_AMIC_96_48_data_sizeof 19 +#define S_DMIC0_96_48_data_ADDR 1941 +#define S_DMIC0_96_48_data_ADDR_END 1959 +#define S_DMIC0_96_48_data_sizeof 19 +#define S_DMIC1_96_48_data_ADDR 1960 +#define S_DMIC1_96_48_data_ADDR_END 1978 +#define S_DMIC1_96_48_data_sizeof 19 +#define S_DMIC2_96_48_data_ADDR 1979 +#define S_DMIC2_96_48_data_ADDR_END 1997 +#define S_DMIC2_96_48_data_sizeof 19 +#define S_DBG_8K_PATTERN_ADDR 1998 +#define S_DBG_8K_PATTERN_ADDR_END 1999 +#define S_DBG_8K_PATTERN_sizeof 2 +#define S_DBG_16K_PATTERN_ADDR 2000 +#define S_DBG_16K_PATTERN_ADDR_END 2003 +#define S_DBG_16K_PATTERN_sizeof 4 +#define S_DBG_24K_PATTERN_ADDR 2004 +#define S_DBG_24K_PATTERN_ADDR_END 2009 +#define S_DBG_24K_PATTERN_sizeof 6 +#define S_DBG_48K_PATTERN_ADDR 2010 +#define S_DBG_48K_PATTERN_ADDR_END 2021 +#define S_DBG_48K_PATTERN_sizeof 12 +#define S_DBG_96K_PATTERN_ADDR 2022 +#define S_DBG_96K_PATTERN_ADDR_END 2045 +#define S_DBG_96K_PATTERN_sizeof 24 +#define S_MM_EXT_IN_ADDR 2046 +#define S_MM_EXT_IN_ADDR_END 2057 +#define S_MM_EXT_IN_sizeof 12 +#define S_MM_EXT_IN_L_ADDR 2058 +#define S_MM_EXT_IN_L_ADDR_END 2069 +#define S_MM_EXT_IN_L_sizeof 12 +#define S_MM_EXT_IN_R_ADDR 2070 +#define S_MM_EXT_IN_R_ADDR_END 2081 +#define S_MM_EXT_IN_R_sizeof 12 +#define S_MIC4_ADDR 2082 +#define S_MIC4_ADDR_END 2093 +#define S_MIC4_sizeof 12 +#define S_MIC4_L_ADDR 2094 +#define S_MIC4_L_ADDR_END 2105 +#define S_MIC4_L_sizeof 12 +#define S_MIC4_R_ADDR 2106 +#define S_MIC4_R_ADDR_END 2117 +#define S_MIC4_R_sizeof 12 +#define S_HW_TEST_ADDR 2118 +#define S_HW_TEST_ADDR_END 2118 +#define S_HW_TEST_sizeof 1 +#define S_XinASRC_BT_UL_ADDR 2119 +#define S_XinASRC_BT_UL_ADDR_END 2158 +#define S_XinASRC_BT_UL_sizeof 40 +#define S_XinASRC_BT_DL_ADDR 2159 +#define S_XinASRC_BT_DL_ADDR_END 2198 +#define S_XinASRC_BT_DL_sizeof 40 +#define S_BT_DL_8k_TEMP_ADDR 2199 +#define S_BT_DL_8k_TEMP_ADDR_END 2200 +#define S_BT_DL_8k_TEMP_sizeof 2 +#define S_BT_DL_16k_TEMP_ADDR 2201 +#define S_BT_DL_16k_TEMP_ADDR_END 2204 +#define S_BT_DL_16k_TEMP_sizeof 4 +#endif/* _ABESM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_taskid.h b/sound/soc/omap/abe/abe_taskid.h new file mode 100644 index 00000000000..a384e1ab70b --- /dev/null +++ b/sound/soc/omap/abe/abe_taskid.h @@ -0,0 +1,148 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_TASKID_H_ +#define _ABE_TASKID_H_ +#define C_ABE_FW_TASK_DL1_APS_CORE 0 +#define C_ABE_FW_TASK_DL1_APS_COIL_CORE 1 +#define C_ABE_FW_TASK_DL2_L_APS_CORE 2 +#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE 3 +#define C_ABE_FW_TASK_DL2_R_APS_CORE 4 +#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE 5 +#define C_ABE_FW_TASK_ASRC_VX_DL_8 6 +#define C_ABE_FW_TASK_ASRC_VX_DL_16 7 +#define C_ABE_FW_TASK_ASRC_MM_EXT_IN 8 +#define C_ABE_FW_TASK_ASRC_VX_UL_8 9 +#define C_ABE_FW_TASK_ASRC_VX_UL_16 10 +#define C_ABE_FW_TASK_VX_UL_48_8_DEC 11 +#define C_ABE_FW_TASK_VX_UL_48_16_DEC 12 +#define C_ABE_FW_TASK_BT_DL_48_8_DEC 13 +#define C_ABE_FW_TASK_BT_DL_48_16_DEC 14 +#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC 15 +#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC 16 +#define C_ABE_FW_TASK_DL2_EQ 17 +#define C_ABE_FW_TASK_DL2_L_APS_IIR 18 +#define C_ABE_FW_TASK_DL2_R_APS_IIR 19 +#define C_ABE_FW_TASK_DL2_APS_EQ 20 +#define C_ABE_FW_TASK_ECHO_REF_48_16 21 +#define C_ABE_FW_TASK_ECHO_REF_48_8 22 +#define C_ABE_FW_TASK_GAIN_UPDATE 23 +#define C_ABE_FW_TASK_SideTone 24 +#define C_ABE_FW_TASK_VX_DL_8_48_LP 25 +#define C_ABE_FW_TASK_VX_DL_8_48_HP 26 +#define C_ABE_FW_TASK_VX_DL_16_48_LP 27 +#define C_ABE_FW_TASK_VX_DL_16_48_HP 28 +#define C_ABE_FW_TASK_VX_UL_48_8_LP 29 +#define C_ABE_FW_TASK_VX_UL_48_8_HP 30 +#define C_ABE_FW_TASK_VX_UL_48_16_LP 31 +#define C_ABE_FW_TASK_VX_UL_48_16_HP 32 +#define C_ABE_FW_TASK_BT_UL_8_48_LP 33 +#define C_ABE_FW_TASK_BT_UL_8_48_HP 34 +#define C_ABE_FW_TASK_BT_UL_16_48_LP 35 +#define C_ABE_FW_TASK_BT_UL_16_48_HP 36 +#define C_ABE_FW_TASK_BT_DL_48_8_LP 37 +#define C_ABE_FW_TASK_BT_DL_48_8_HP 38 +#define C_ABE_FW_TASK_BT_DL_48_16_LP 39 +#define C_ABE_FW_TASK_BT_DL_48_16_HP 40 +#define C_ABE_FW_TASK_ECHO_REF_48_8_LP 41 +#define C_ABE_FW_TASK_ECHO_REF_48_8_HP 42 +#define C_ABE_FW_TASK_ECHO_REF_48_16_LP 43 +#define C_ABE_FW_TASK_ECHO_REF_48_16_HP 44 +#define C_ABE_FW_TASK_DL1_EQ 45 +#define C_ABE_FW_TASK_DL1_APS_IIR 46 +#define C_ABE_FW_TASK_DL1_APS_EQ 47 +#define C_ABE_FW_TASK_IHF_48_96_LP 48 +#define C_ABE_FW_TASK_EARP_48_96_LP 49 +#define C_ABE_FW_TASK_DL1_GAIN 50 +#define C_ABE_FW_TASK_DL2_GAIN 51 +#define C_ABE_FW_TASK_IO_PING_PONG 52 +#define C_ABE_FW_TASK_IO_DMIC 53 +#define C_ABE_FW_TASK_IO_PDM_UL 54 +#define C_ABE_FW_TASK_IO_BT_VX_UL 55 +#define C_ABE_FW_TASK_IO_MM_UL 56 +#define C_ABE_FW_TASK_IO_MM_UL2 57 +#define C_ABE_FW_TASK_IO_VX_UL 58 +#define C_ABE_FW_TASK_IO_MM_DL 59 +#define C_ABE_FW_TASK_IO_VX_DL 60 +#define C_ABE_FW_TASK_IO_TONES_DL 61 +#define C_ABE_FW_TASK_IO_VIB_DL 62 +#define C_ABE_FW_TASK_IO_BT_VX_DL 63 +#define C_ABE_FW_TASK_IO_PDM_DL 64 +#define C_ABE_FW_TASK_IO_MM_EXT_OUT 65 +#define C_ABE_FW_TASK_IO_MM_EXT_IN 66 +#define C_ABE_FW_TASK_IO_TDM_OUT 67 +#define C_ABE_FW_TASK_IO_TDM_IN 68 +#define C_ABE_FW_TASK_DEBUG_IRQFIFO 69 +#define C_ABE_FW_TASK_EchoMixer 70 +#define C_ABE_FW_TASK_SDTMixer 71 +#define C_ABE_FW_TASK_DL1Mixer 72 +#define C_ABE_FW_TASK_DL2Mixer 73 +#define C_ABE_FW_TASK_VXRECMixer 74 +#define C_ABE_FW_TASK_ULMixer 75 +#define C_ABE_FW_TASK_VIBRA_PACK 76 +#define C_ABE_FW_TASK_VX_DL_8_48_0SR 77 +#define C_ABE_FW_TASK_VX_DL_16_48_0SR 78 +#define C_ABE_FW_TASK_BT_UL_8_48_0SR 79 +#define C_ABE_FW_TASK_BT_UL_16_48_0SR 80 +#define C_ABE_FW_TASK_IHF_48_96_0SR 81 +#define C_ABE_FW_TASK_EARP_48_96_0SR 82 +#define C_ABE_FW_TASK_AMIC_SPLIT 83 +#define C_ABE_FW_TASK_DMIC1_SPLIT 84 +#define C_ABE_FW_TASK_DMIC2_SPLIT 85 +#define C_ABE_FW_TASK_DMIC3_SPLIT 86 +#define C_ABE_FW_TASK_VXREC_SPLIT 87 +#define C_ABE_FW_TASK_BT_UL_SPLIT 88 +#define C_ABE_FW_TASK_MM_SPLIT 89 +#define C_ABE_FW_TASK_DL2_APS_SPLIT 90 +#define C_ABE_FW_TASK_VIBRA_SPLIT 91 +#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT 92 +#define C_ABE_FW_TASK_ECHO_REF_SPLIT 93 +#define C_ABE_FW_TASK_MIC4_SPLIT 94 +#define C_ABE_FW_TASK_VX_UL_ROUTING 95 +#define C_ABE_FW_TASK_MM_UL2_ROUTING 96 +#define C_ABE_FW_TASK_VIBRA1 97 +#define C_ABE_FW_TASK_VIBRA2 98 +#define C_ABE_FW_TASK_BT_UL_16_48 99 +#define C_ABE_FW_TASK_BT_UL_8_48 100 +#define C_ABE_FW_TASK_BT_DL_48_16 101 +#define C_ABE_FW_TASK_BT_DL_48_8 102 +#define C_ABE_FW_TASK_VX_DL_16_48 103 +#define C_ABE_FW_TASK_VX_DL_8_48 104 +#define C_ABE_FW_TASK_VX_UL_48_16 105 +#define C_ABE_FW_TASK_VX_UL_48_8 106 +#define C_ABE_FW_TASK_DBG_SYNC 107 +#define C_ABE_FW_TASK_APS_DL1_IRQs 108 +#define C_ABE_FW_TASK_APS_DL2_L_IRQs 109 +#define C_ABE_FW_TASK_APS_DL2_R_IRQs 110 +#define C_ABE_FW_TASK_AMIC_96_48_LP 111 +#define C_ABE_FW_TASK_DMIC1_96_48_LP 112 +#define C_ABE_FW_TASK_DMIC2_96_48_LP 113 +#define C_ABE_FW_TASK_DMIC3_96_48_LP 114 +#define C_ABE_FW_TASK_INIT_FW_MEMORY 115 +#define C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs 116 +#define C_ABE_FW_TASK_ASRC_BT_UL_8 117 +#define C_ABE_FW_TASK_ASRC_BT_UL_16 118 +#define C_ABE_FW_TASK_ASRC_BT_DL_8 119 +#define C_ABE_FW_TASK_ASRC_BT_DL_16 120 +#define C_ABE_FW_TASK_BT_DL_48_8_HP_OPP100 121 +#define C_ABE_FW_TASK_BT_DL_48_16_HP_OPP100 122 +#define C_ABE_FW_TASK_BT_DL_48_8_OPP100 123 +#define C_ABE_FW_TASK_BT_DL_48_16_OPP100 124 +#endif/* _ABE_TASKID_H_ */ diff --git a/sound/soc/omap/abe/abe_typ.h b/sound/soc/omap/abe/abe_typ.h new file mode 100644 index 00000000000..801b0423857 --- /dev/null +++ b/sound/soc/omap/abe/abe_typ.h @@ -0,0 +1,679 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#include "abe_def.h" +#include "abe_initxxx_labels.h" +#ifndef ABETYP +#define ABETYP +/* + * BASIC TYPES + */ +#define MAX_UINT8 ((((1L << 7) -1)<<1) +1) +#define MAX_UINT16 ((((1L << 15) -1)<<1) +1) +#define MAX_UINT32 ((((1L << 31) -1)<<1) +1) +#define s8 char +#define u8 unsigned char +#define s16 short +#define u16 unsigned short +#define s32 int +#define u32 unsigned int +/* returned status from HAL APIs */ +#define abehal_status u32 +/* 4 bytes Bit field indicating the type of informations to be traced */ +typedef u32 abe_dbg_mask_t; +/* scheduling task loops (250us / 272us with respectively 48kHz / + 44.1kHz on Phoenix). */ +typedef u32 abe_dbg_t; +/* Index to the table of sequences */ +typedef u32 abe_seq_code_t; +/* Index to the table of subroutines called in the sequence */ +typedef u32 abe_sub_code_t; +/* subroutine with no parameter */ +typedef void (*abe_subroutine0) (void); +/* subroutine with one parameter */ +typedef void (*abe_subroutine1) (u32); +typedef void (*abe_subroutine2) (u32, u32); +typedef void (*abe_subroutine3) (u32, u32, u32); +typedef void (*abe_subroutine4) (u32, u32, u32, u32); +/* + * CODE PORTABILITY - FUTURE PATCHES + * + * 32bits field for having the code compatible with future revisions of + * the hardware (audio integration) or evolution of the software + * partitionning. Used for the highest level APIs (launch_sequences) + */ +typedef u32 abe_patch_rev; +/* + * ENUMS + */ +/* + * MEMORY CONFIG TYPE + * + * 0: Ultra Lowest power consumption audio player + * 1: OPP 25% (simple multimedia features) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (multimedia complex use-cases) + */ +#define ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE 1 +#define ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER 2 +#define ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL 3 +#define ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT 4 +#define ABE_MULTIMEDIA_AUDIO_RECORDER 5 +#define ABE_VIBRATOR_OR_HAPTICS 6 +#define ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER 7 +#define ABE_RINGER_TONES 8 +#define ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER 9 +#define ABE_LAST_USE_CASE 10 +/* + * OPP TYPE + * + * 0: Ultra Lowest power consumption audio player + * 1: OPP 25% (simple multimedia features) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (multimedia complex use-cases) + */ +#define ABE_OPP0 0 +#define ABE_OPP25 1 +#define ABE_OPP50 2 +#define ABE_OPP100 3 +/* + * DMIC DECIMATION RATIO + * + */ +#define ABE_DEC16 16 +#define ABE_DEC25 25 +#define ABE_DEC32 32 +#define ABE_DEC40 40 +/* + * SAMPLES TYPE + * + * mono 16bits sample LSB aligned, 16 MSB bits are unused + * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP + * TX purpose. + * mono sample MSB aligned (16/24/32bits) + * two successive mono samples in one 32bits container + * Two L/R 16bits samples in a 32bits container, + * Two channels defined with two MSB aligned samples + * Three channels defined with three MSB aligned samples (MIC) + * Four channels defined with four MSB aligned samples (MIC) + . . . + * Eight channels defined with eight MSB aligned samples (MIC) + */ +#define MONO_MSB 1 +#define MONO_RSHIFTED_16 2 +#define STEREO_RSHIFTED_16 3 +#define STEREO_16_16 4 +#define STEREO_MSB 5 +#define THREE_MSB 6 +#define FOUR_MSB 7 +#define FIVE_MSB 8 +#define SIX_MSB 9 +#define SEVEN_MSB 10 +#define EIGHT_MSB 11 +#define NINE_MSB 12 +#define TEN_MSB 13 +/* + * PORT PROTOCOL TYPE - abe_port_protocol_switch_id + */ +#define SLIMBUS_PORT_PROT 1 +#define SERIAL_PORT_PROT 2 +#define TDM_SERIAL_PORT_PROT 3 +#define DMIC_PORT_PROT 4 +#define MCPDMDL_PORT_PROT 5 +#define MCPDMUL_PORT_PROT 6 +#define PINGPONG_PORT_PROT 7 +#define DMAREQ_PORT_PROT 8 +/* + * PORT IDs, this list is aligned with the FW data mapping + */ +#define DMIC_PORT 0 +#define PDM_UL_PORT 1 +#define BT_VX_UL_PORT 2 +#define MM_UL_PORT 3 +#define MM_UL2_PORT 4 +#define VX_UL_PORT 5 +#define MM_DL_PORT 6 +#define VX_DL_PORT 7 +#define TONES_DL_PORT 8 +#define VIB_DL_PORT 9 +#define BT_VX_DL_PORT 10 +#define PDM_DL_PORT 11 +#define MM_EXT_OUT_PORT 12 +#define MM_EXT_IN_PORT 13 +#define TDM_DL_PORT 14 +#define TDM_UL_PORT 15 +#define DEBUG_PORT 16 +#define LAST_PORT_ID 17 +/* definitions for the compatibility with HAL05xx */ +#define PDM_DL1_PORT 18 +#define PDM_DL2_PORT 19 +#define PDM_VIB_PORT 20 +/* There is only one DMIC port, always used with 6 samples + per 96kHz periods */ +#define DMIC_PORT1 DMIC_PORT +#define DMIC_PORT2 DMIC_PORT +#define DMIC_PORT3 DMIC_PORT +/* + * ABE_DL_SRC_ID source of samples + */ +#define SRC_DL1_MIXER_OUTPUT DL1_M_labelID +#define SRC_SDT_MIXER_OUTPUT SDT_M_labelID +#define SRC_DL1_GAIN_OUTPUT DL1_GAIN_out_labelID +#define SRC_DL1_EQ_OUTPUT DL1_EQ_labelID +#define SRC_DL2_GAIN_OUTPUT DL2_GAIN_out_labelID +#define SRC_DL2_EQ_OUTPUT DL2_EQ_labelID +#define SRC_MM_DL MM_DL_labelID +#define SRC_TONES_DL Tones_labelID +#define SRC_VX_DL VX_DL_labelID +#define SRC_VX_UL VX_UL_labelID +#define SRC_MM_UL2 MM_UL2_labelID +#define SRC_MM_UL MM_UL_labelID +/* + * abe_patched_pattern_id selection of the audio engine signal to + * replace by a precomputed pattern + */ +#define DBG_PATCH_AMIC 1 +#define DBG_PATCH_DMIC1 2 +#define DBG_PATCH_DMIC2 3 +#define DBG_PATCH_DMIC3 4 +#define DBG_PATCH_VX_REC 5 +#define DBG_PATCH_BT_UL 6 +#define DBG_PATCH_MM_DL 7 +#define DBG_PATCH_DL2_EQ 8 +#define DBG_PATCH_VIBRA 9 +#define DBG_PATCH_MM_EXT_IN 10 +#define DBG_PATCH_EANC_FBK_Out 11 +#define DBG_PATCH_MIC4 12 +#define DBG_PATCH_MM_DL_MIXDL1 13 +#define DBG_PATCH_MM_DL_MIXDL2 14 +/* + * Signal processing module names - EQ APS MIX ROUT + */ +/* equalizer downlink path headset + earphone */ +#define FEAT_EQ1 1 +/* equalizer downlink path integrated handsfree LEFT */ +#define FEAT_EQ2L (FEAT_EQ1+1) +/* equalizer downlink path integrated handsfree RIGHT */ +#define FEAT_EQ2R (FEAT_EQ2L+1) +/* equalizer downlink path side-tone */ +#define FEAT_EQSDT (FEAT_EQ2R+1) +/* equalizer uplink path AMIC */ +#define FEAT_EQAMIC (FEAT_EQSDT+1) +/* equalizer uplink path DMIC */ +#define FEAT_EQDMIC (FEAT_EQAMIC+1) +/* Acoustic protection for headset */ +#define FEAT_APS1 (FEAT_EQDMIC+1) +/* acoustic protection high-pass filter for handsfree "Left" */ +#define FEAT_APS2 (FEAT_APS1+1) +/* acoustic protection high-pass filter for handsfree "Right" */ +#define FEAT_APS3 (FEAT_APS2+1) +/* asynchronous sample-rate-converter for the downlink voice path */ +#define FEAT_ASRC1 (FEAT_APS3+1) +/* asynchronous sample-rate-converter for the uplink voice path */ +#define FEAT_ASRC2 (FEAT_ASRC1+1) +/* asynchronous sample-rate-converter for the multimedia player */ +#define FEAT_ASRC3 (FEAT_ASRC2+1) +/* asynchronous sample-rate-converter for the echo reference */ +#define FEAT_ASRC4 (FEAT_ASRC3+1) +/* mixer of the headset and earphone path */ +#define FEAT_MIXDL1 (FEAT_ASRC4+1) +/* mixer of the hands-free path */ +#define FEAT_MIXDL2 (FEAT_MIXDL1+1) +/* mixer for audio being sent on the voice_ul path */ +#define FEAT_MIXAUDUL (FEAT_MIXDL2+1) +/* mixer for voice communication recording */ +#define FEAT_MIXVXREC (FEAT_MIXAUDUL+1) +/* mixer for side-tone */ +#define FEAT_MIXSDT (FEAT_MIXVXREC+1) +/* mixer for echo reference */ +#define FEAT_MIXECHO (FEAT_MIXSDT+1) +/* router of the uplink path */ +#define FEAT_UPROUTE (FEAT_MIXECHO+1) +/* all gains */ +#define FEAT_GAINS (FEAT_UPROUTE+1) +#define FEAT_GAINS_DMIC1 (FEAT_GAINS+1) +#define FEAT_GAINS_DMIC2 (FEAT_GAINS_DMIC1+1) +#define FEAT_GAINS_DMIC3 (FEAT_GAINS_DMIC2+1) +#define FEAT_GAINS_AMIC (FEAT_GAINS_DMIC3+1) +#define FEAT_GAINS_SPLIT (FEAT_GAINS_AMIC+1) +#define FEAT_GAINS_DL1 (FEAT_GAINS_SPLIT+1) +#define FEAT_GAINS_DL2 (FEAT_GAINS_DL1+1) +#define FEAT_GAIN_EANC (FEAT_GAINS_DL2+1) +/* sequencing queue of micro tasks */ +#define FEAT_SEQ (FEAT_GAIN_EANC+1) +/* Phoenix control queue through McPDM */ +#define FEAT_CTL (FEAT_SEQ+1) +/* list of features of the firmware -------------------------------*/ +#define MAXNBFEATURE FEAT_CTL +/* abe_equ_id */ +/* equalizer downlink path headset + earphone */ +#define EQ1 FEAT_EQ1 +/* equalizer downlink path integrated handsfree LEFT */ +#define EQ2L FEAT_EQ2L +#define EQ2R FEAT_EQ2R +/* equalizer downlink path side-tone */ +#define EQSDT FEAT_EQSDT +#define EQAMIC FEAT_EQAMIC +#define EQDMIC FEAT_EQDMIC +/* abe_aps_id */ +/* Acoustic protection for headset */ +#define APS1 FEAT_APS1 +#define APS2L FEAT_APS2 +#define APS2R FEAT_APS3 +/* abe_asrc_id */ +/* asynchronous sample-rate-converter for the downlink voice path */ +#define ASRC1 FEAT_ASRC1 +/* asynchronous sample-rate-converter for the uplink voice path */ +#define ASRC2 FEAT_ASRC2 +/* asynchronous sample-rate-converter for the multimedia player */ +#define ASRC3 FEAT_ASRC3 +/* asynchronous sample-rate-converter for the voice uplink echo_reference */ +#define ASRC4 FEAT_ASRC4 +/* abe_mixer_id */ +#define MIXDL1 FEAT_MIXDL1 +#define MIXDL2 FEAT_MIXDL2 +#define MIXSDT FEAT_MIXSDT +#define MIXECHO FEAT_MIXECHO +#define MIXEANC FEAT_GAIN_EANC +#define MIXAUDUL FEAT_MIXAUDUL +#define MIXVXREC FEAT_MIXVXREC +/* abe_router_id */ +/* there is only one router up to now */ +#define UPROUTE FEAT_UPROUTE +/* + * GAIN IDs + */ +#define GAINS_DMIC1 FEAT_GAINS_DMIC1 +#define GAINS_DMIC2 FEAT_GAINS_DMIC2 +#define GAINS_DMIC3 FEAT_GAINS_DMIC3 +#define GAINS_AMIC FEAT_GAINS_AMIC +#define GAINS_SPLIT FEAT_GAINS_SPLIT +#define GAINS_DL1 FEAT_GAINS_DL1 +#define GAINS_DL2 FEAT_GAINS_DL2 +#define GAINS_EANC FEAT_GAIN_EANC +/* + * EVENT GENERATORS - abe_event_id + */ +#define EVENT_TIMER 0 +#define EVENT_44100 1 +/* + * SERIAL PORTS IDs - abe_mcbsp_id + */ +#define MCBSP1_TX MCBSP1_DMA_TX +#define MCBSP1_RX MCBSP1_DMA_RX +#define MCBSP2_TX MCBSP2_DMA_TX +#define MCBSP2_RX MCBSP2_DMA_RX +#define MCBSP3_TX MCBSP3_DMA_TX +#define MCBSP3_RX MCBSP3_DMA_RX +/* + * SERIAL PORTS IDs - abe_slimbus_id; + */ +#define SLIMBUS1_TX0 SLIMBUS1_DMA_TX0 +#define SLIMBUS1_TX1 SLIMBUS1_DMA_TX1 +#define SLIMBUS1_TX2 SLIMBUS1_DMA_TX2 +#define SLIMBUS1_TX3 SLIMBUS1_DMA_TX3 +#define SLIMBUS1_TX4 SLIMBUS1_DMA_TX4 +#define SLIMBUS1_TX5 SLIMBUS1_DMA_TX5 +#define SLIMBUS1_TX6 SLIMBUS1_DMA_TX6 +#define SLIMBUS1_TX7 SLIMBUS1_DMA_TX7 +#define SLIMBUS1_RX0 SLIMBUS1_DMA_RX0 +#define SLIMBUS1_RX1 SLIMBUS1_DMA_RX1 +#define SLIMBUS1_RX2 SLIMBUS1_DMA_RX2 +#define SLIMBUS1_RX3 SLIMBUS1_DMA_RX3 +#define SLIMBUS1_RX4 SLIMBUS1_DMA_RX4 +#define SLIMBUS1_RX5 SLIMBUS1_DMA_RX5 +#define SLIMBUS1_RX6 SLIMBUS1_DMA_RX6 +#define SLIMBUS1_RX7 SLIMBUS1_DMA_RX7 +#define SLIMBUS_UNUSED _DUMMY_FIFO_ +/* + * --------------------------------- TYPES USED FOR APIS --------------- + */ +/* + * HARDWARE CONFIG TYPE + */ +typedef struct { + /* EVENT_GENERATOR_COUNTER_DEFAULT gives about 96kHz */ + u32 AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE; + /* 0: DMAreq, 1:Counter */ + u32 AESS_EVENT_SOURCE_SELECTION__SELECTION; + /* 5bits DMAreq selection */ + u32 AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION; + u32 HAL_EVENT_SELECTION; + /* 0: 96kHz 1:192kHz */ + u32 MCPDM_CTRL__DIV_SEL; + /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */ + u32 MCPDM_CTRL__CMD_INT; + /* 0:MSB aligned 1:LSB aligned */ + u32 MCPDM_CTRL__PDMOUTFORMAT; + u32 MCPDM_CTRL__PDM_DN5_EN; + u32 MCPDM_CTRL__PDM_DN4_EN; + u32 MCPDM_CTRL__PDM_DN3_EN; + u32 MCPDM_CTRL__PDM_DN2_EN; + u32 MCPDM_CTRL__PDM_DN1_EN; + u32 MCPDM_CTRL__PDM_UP3_EN; + u32 MCPDM_CTRL__PDM_UP2_EN; + u32 MCPDM_CTRL__PDM_UP1_EN; + u32 MCPDM_FIFO_CTRL_DN__DN_TRESH; + u32 MCPDM_FIFO_CTRL_UP__UP_TRESH; + /* 0:2.4MHz 1:3.84MHz */ + u32 DMIC_CTRL__DMIC_CLK_DIV; + /* 0:MSB aligned 1:LSB aligned */ + u32 DMIC_CTRL__DMICOUTFORMAT; + u32 DMIC_CTRL__DMIC_UP3_EN; + u32 DMIC_CTRL__DMIC_UP2_EN; + u32 DMIC_CTRL__DMIC_UP1_EN; + /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ + u32 DMIC_FIFO_CTRL__DMIC_TRESH; + /* 1:MSB 2:LSB aligned */ + u32 MCBSP_SPCR1_REG__RJUST; + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + u32 MCBSP_THRSH2_REG_REG__XTHRESHOLD; + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + u32 MCBSP_THRSH1_REG_REG__RTHRESHOLD; + u32 SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD; +} abe_hw_config_init_t; +/* + * EQU_T + * + * coefficients of the equalizer + */ +typedef struct { + /* type of filter */ + u32 equ_type; + /* filter length */ + u32 equ_length; + union { + /* parameters are the direct and recursive coefficients in */ + /* Q6.26 integer fixed-point format. */ + s32 type1[NBEQ1]; + struct { + /* center frequency of the band [Hz] */ + s32 freq[NBEQ2]; + /* gain of each band. [dB] */ + s32 gain[NBEQ2]; + /* Q factor of this band [dB] */ + s32 q[NBEQ2]; + } type2; + } coef; + s32 equ_param3; +} abe_equ_t; +/* + * APS_T + * + * coefficients of the Acoustics Protection and Safety + */ +typedef struct { + s32 coef1[NBAPS1]; + s32 coef2[NBAPS2]; +} abe_aps_t; +typedef struct { + /* structure of two energy_t estimation for coil and membrane */ + u32 e1; + u32 e2; +} abe_aps_energy_t; +/* + * ROUTER_T + * + * table of indexes in unsigned bytes + */ +typedef u16 abe_router_t; +/* + * DATA_FORMAT_T + * + * used in port declaration + */ +typedef struct { + /* Sampling frequency of the stream */ + u32 f; + /* Sample format type */ + u32 samp_format; +} abe_data_format_t; +/* + * PORT_PROTOCOL_T + * + * port declaration + */ +typedef struct { + /* Direction=0 means input from AESS point of view */ + u32 direction; + /* Protocol type (switch) during the data transfers */ + u32 protocol_switch; + union { + /* Slimbus peripheral connected to ATC */ + struct { + /* Address of ATC Slimbus descriptor's index */ + u32 desc_addr1; + /* DMEM address 1 in bytes */ + u32 buf_addr1; + /* DMEM buffer size size in bytes */ + u32 buf_size; + /* ITERation on each DMAreq signals */ + u32 iter; + /* Second ATC index for SlimBus reception (or NULL) */ + u32 desc_addr2; + /* DMEM address 2 in bytes */ + u32 buf_addr2; + } prot_slimbus; + /* McBSP/McASP peripheral connected to ATC */ + struct { + u32 desc_addr; + /* Address of ATC McBSP/McASP descriptor's in bytes */ + u32 buf_addr; + /* DMEM address in bytes */ + u32 buf_size; + /* ITERation on each DMAreq signals */ + u32 iter; + } prot_serial; + /* DMIC peripheral connected to ATC */ + struct { + /* DMEM address in bytes */ + u32 buf_addr; + /* DMEM buffer size in bytes */ + u32 buf_size; + /* Number of activated DMIC */ + u32 nbchan; + } prot_dmic; + /* McPDMDL peripheral connected to ATC */ + struct { + /* DMEM address in bytes */ + u32 buf_addr; + /* DMEM size in bytes */ + u32 buf_size; + /* Control allowed on McPDM DL */ + u32 control; + } prot_mcpdmdl; + /* McPDMUL peripheral connected to ATC */ + struct { + /* DMEM address size in bytes */ + u32 buf_addr; + /* DMEM buffer size size in bytes */ + u32 buf_size; + } prot_mcpdmul; + /* Ping-Pong interface to the Host using cache-flush */ + struct { + /* Address of ATC descriptor's */ + u32 desc_addr; + /* DMEM buffer base address in bytes */ + u32 buf_addr; + /* DMEM size in bytes for each ping and pong buffers */ + u32 buf_size; + /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */ + u32 irq_addr; + /* IRQ data content loaded in the AESS IRQ register */ + u32 irq_data; + /* Call-back function upon IRQ reception */ + u32 callback; + } prot_pingpong; + /* DMAreq line to CBPr */ + struct { + /* Address of ATC descriptor's */ + u32 desc_addr; + /* DMEM buffer address in bytes */ + u32 buf_addr; + /* DMEM buffer size size in bytes */ + u32 buf_size; + /* ITERation on each DMAreq signals */ + u32 iter; + /* DMAreq address */ + u32 dma_addr; + /* DMA/AESS = 1 << #DMA */ + u32 dma_data; + } prot_dmareq; + /* Circular buffer - direct addressing to DMEM */ + struct { + /* DMEM buffer base address in bytes */ + u32 buf_addr; + /* DMEM buffer size in bytes */ + u32 buf_size; + /* DMAreq address */ + u32 dma_addr; + /* DMA/AESS = 1 << #DMA */ + u32 dma_data; + } prot_circular_buffer; + } p; +} abe_port_protocol_t; +/* + * DMA_T + * + * dma structure for easing programming + */ +typedef struct { + /* OCP L3 pointer to the first address of the */ + void *data; + /* destination buffer (either DMA or Ping-Pong read/write pointers). */ + /* address L3 when addressing the DMEM buffer instead of CBPr */ + void *l3_dmem; + /* address L3 translated to L4 the ARM memory space */ + void *l4_dmem; + /* number of iterations for the DMA data moves. */ + u32 iter; +} abe_dma_t; +typedef struct { + /* Offset to the first address of the */ + u32 data; + /* number of iterations for the DMA data moves. */ + u32 iter; +} abe_dma_t_offset; +/* + * SEQ_T + * + * struct { + * micros_t time; Waiting time before executing next line + * seq_code_t code Subroutine index interpreted in the HAL and + * translated to + * FW subroutine codes in case of ABE tasks + * int32 param[2] Two parameters + * } seq_t + * + */ +typedef struct { + u32 delta_time; + u32 code; + u32 param[4]; + u8 tag; +} abe_seq_t; +typedef struct { + u32 mask; + abe_seq_t seq1; + abe_seq_t seq2; +} abe_sequence_t; +/* + * DRIFT_T abe_drift_t = s32 + * + * ASRC drift parameter in [ppm] value + */ +/* + * --------------------------------- INTERNAL DATA TYPES --------------------- + */ +/* + * ABE_IRQ_DATA_T + * + * IRQ FIFO content declaration + * APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], + * loopCounter to [15:0] + * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], + * loopCounter to [15:0] + * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], + * loopCounter to [15:0] + */ +typedef struct { + unsigned int counter:16; + unsigned int data:12; + unsigned int tag:4; +} abe_irq_data_t; +/* + * ABE_PORT_T status / format / sampling / protocol(call_back) / features / + * gain / name .. + * + */ +typedef struct { + /* running / idled */ + u16 status; + /* Sample format type */ + abe_data_format_t format; + /* API : for ASRC */ + s32 drift; + /* optionnal call-back index for errors and ack */ + u16 callback; + /* IO tasks buffers */ + u16 smem_buffer1; + u16 smem_buffer2; + abe_port_protocol_t protocol; + /* pointer and iteration counter of the xDMA */ + abe_dma_t_offset dma; + /* list of features associated to a port (EQ, APS, ... , ends with 0) */ + u16 feature_index[MAXFEATUREPORT]; + char name[NBCHARPORTNAME]; +} abe_port_t; +/* + * ABE_SUBROUTINE_T + * + */ +typedef struct { + u32 sub_id; + s32 param[4]; +} abe_subroutine_t; +/* + * ABE_PORT_INFO_T OPP, subroutines to call on reset + * + */ +typedef struct { + u32 min_opp; + abe_subroutine_t sub1; + abe_subroutine_t sub2; +} abe_port_info_t; +/* + * ABE_FEATURE_T + * + */ +typedef struct { + u16 enable_with_default_data; + u16 disable_feature; + u16 read_parameter; + u16 write_parameter; + u16 running_status; + u16 fw_input_buffer_address; + u16 fw_output_buffer_address; + u16 fw_scheduler_slot_position; + u16 fw_scheduler_subslot_position; + u32 min_opp; + char name[NBCHARFEATURENAME]; +} abe_feature_t; +#endif/* ifndef ABETYP */ diff --git a/sound/soc/omap/abe/abe_typedef.h b/sound/soc/omap/abe/abe_typedef.h new file mode 100644 index 00000000000..37c1146fdf1 --- /dev/null +++ b/sound/soc/omap/abe/abe_typedef.h @@ -0,0 +1,199 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ +#ifndef _ABE_TYPEDEF_H_ +#define _ABE_TYPEDEF_H_ +#include "abe_define.h" +/* + * Basic types definition + */ +typedef unsigned char ABE_uchar; +typedef char ABE_char; +typedef unsigned short ABE_uint16; +typedef short ABE_int16; +typedef long ABE_int32; +typedef unsigned long ABE_uint32; +typedef ABE_uchar *pABE_uchar; +typedef ABE_char *pABE_char; +typedef ABE_uint16 *pABE_uint16; +typedef ABE_int16 *pABE_int16; +typedef ABE_int32 *pABE_int32; +typedef ABE_uint32 *pABE_uint32; +/* + * Commonly used structures + */ +typedef struct abetaskTag { + /* 0 ... Index of called function */ + ABE_uint16 iF; + /* 2 ... for INITPTR of A0 */ + ABE_uint16 A0; + /* 4 ... for INITPTR of A1 */ + ABE_uint16 A1; + /* 6 ... for INITPTR of A2 & A3 */ + ABE_uint16 A2_3; + /* 8 ... for INITPTR of A4 & A5 */ + ABE_uint16 A4_5; + /* 10 ... for INITREG of R0, R1, R2, R3 */ + ABE_uint16 R; + /* 12 */ + ABE_uint16 misc0; + /* 14 */ + ABE_uint16 misc1; +} ABE_STask; +typedef ABE_STask *pABE_STask; +typedef ABE_STask **ppABE_STask; +typedef struct { + /* 0 */ + ABE_uint16 drift_ASRC; + /* 2 */ + ABE_uint16 drift_io; + /* 4 "Function index" of XLS sheet "Functions" */ + ABE_uchar io_type_idx; + /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */ + ABE_uchar samp_size; + /* 6 drift "issues" for ASRC */ + ABE_int16 flow_counter; + /* 8 address for IRQ or DMArequests */ + ABE_uint16 hw_ctrl_addr; + /* 10 DMA request bit-field or IRQ (DSP/MCU) */ + ABE_uchar atc_irq_data; + /* 11 0 = Read, 3 = Write */ + ABE_uchar direction_rw; + /* 12 */ + ABE_uchar repeat_last_samp; + /* 13 12 at 48kHz, ... */ + ABE_uchar nsamp; + /* 14 nsamp x samp_size */ + ABE_uchar x_io; + /* 15 ON = 0x80, OFF = 0x00 */ + ABE_uchar on_off; + /* 16 For Slimbus and TDM purpose */ + ABE_uint16 split_addr1; + /* 18 */ + ABE_uint16 split_addr2; + /* 20 */ + ABE_uint16 split_addr3; + /* 22 */ + ABE_uchar before_f_index; + /* 23 */ + ABE_uchar after_f_index; + /* 24 SM/CM INITPTR field */ + ABE_uint16 smem_addr1; + /* 26 in bytes */ + ABE_uint16 atc_address1; + /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */ + ABE_uint16 atc_pointer_saved1; + /* 30 samp_size (except in TDM or Slimbus) */ + ABE_uchar data_size1; + /* 31 "Function index" of XLS sheet "Functions" */ + ABE_uchar copy_f_index1; + /* 32 For Slimbus and TDM purpose */ + ABE_uint16 smem_addr2; + /* 34 */ + ABE_uint16 atc_address2; + /* 36 */ + ABE_uint16 atc_pointer_saved2; + /* 38 */ + ABE_uchar data_size2; + /* 39 */ + ABE_uchar copy_f_index2; +} ABE_SIODescriptor; +/* [w] asrc output used for the next asrc call (+/- 1 / 0) */ +#define drift_asrc_ 0 +/* [w] asrc output used for controlling the number of samples to be + exchanged (+/- 1 / 0) */ +#define drift_io_ 2 +/* address of the IO subroutine */ +#define io_type_idx_ 4 +#define samp_size_ 5 +/* flow error counter */ +#define flow_counter_ 6 +/* dmareq address or host irq buffer address (atc address) */ +#define hw_ctrl_addr_ 8 +/* data content to be loaded to "hw_ctrl_addr" */ +#define atc_irq_data_ 10 +/* read dmem =0, write dmem =3 (atc offset of the access pointer) */ +#define direction_rw_ 11 +/* flag set to allow repeating the last sample on downlink paths */ +#define repeat_last_samp_ 12 +/* number of samples (either mono stereo...) */ +#define nsamp_ 13 +/* x number of raw DMEM data moved */ +#define x_io_ 14 +#define on_off_ 15 +/* internal smem buffer initptr pointer index */ +#define split_addr1_ 16 +/* internal smem buffer initptr pointer index */ +#define split_addr2_ 18 +/* internal smem buffer initptr pointer index */ +#define split_addr3_ 20 +/* index of the copy subroutine */ +#define before_f_index_ 22 +/* index of the copy subroutine */ +#define after_f_index_ 23 +#define minidesc1_ 24 +/* internal smem buffer initptr pointer index */ +#define rel_smem_ 0 +/* atc descriptor address (byte address x4) */ +#define rel_atc_ 2 +/* location of the saved ATC pointer (+debug info) */ +#define rel_atc_saved 4 +/* size of each sample (1:mono/1616 2:stereo ... ) */ +#define rel_size_ 6 +/* index of the copy subroutine */ +#define rel_f_ 7 +#define s_mem_mm_ul 24 +#define s_mm_ul_size 30 +#define minidesc2_ 32 +#define Struct_Size 40 +typedef struct { + /* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0) */ + ABE_uint16 drift_ASRC; + /* 2: [W] asrc output used for controlling the number of + samples to be exchanged (+/- 1 / 0) */ + ABE_uint16 drift_io; + /* 4: DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */ + ABE_uint16 hw_ctrl_addr; + /* 6: index of the copy subroutine */ + ABE_uchar copy_func_index; + /* 7: X number of SMEM samples to move */ + ABE_uchar x_io; + /* 8: 0 for mono data, 1 for stereo data */ + ABE_uchar data_size; + /* 9: internal SMEM buffer INITPTR pointer index */ + ABE_uchar smem_addr; + /* 10: data content to be loaded to "hw_ctrl_addr" */ + ABE_uchar atc_irq_data; + /* 11: ping/pong buffer flag */ + ABE_uchar counter; + /* 12: current Base address of the working buffer */ + ABE_uint16 workbuff_BaseAddr; + /* 14: samples left in the working buffer */ + ABE_uint16 workbuff_Samples; + /* 16: Base address of the ping/pong buffer 0 */ + ABE_uint16 nextbuff0_BaseAddr; + /* 18: samples available in the ping/pong buffer 0 */ + ABE_uint16 nextbuff0_Samples; + /* 20: Base address of the ping/pong buffer 1 */ + ABE_uint16 nextbuff1_BaseAddr; + /* 22: samples available in the ping/pong buffer 1 */ + ABE_uint16 nextbuff1_Samples; +} ABE_SPingPongDescriptor; +#endif/* _ABE_TYPEDEF_H_ */ diff --git a/sound/soc/omap/mcpdm.c b/sound/soc/omap/mcpdm.c deleted file mode 100644 index 928f0370745..00000000000 --- a/sound/soc/omap/mcpdm.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * mcpdm.c -- McPDM interface driver - * - * Author: Jorge Eduardo Candelaria <x0107209@ti.com> - * Copyright (C) 2009 - Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/wait.h> -#include <linux/slab.h> -#include <linux/interrupt.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/irq.h> - -#include "mcpdm.h" - -static struct omap_mcpdm *mcpdm; - -static inline void omap_mcpdm_write(u16 reg, u32 val) -{ - __raw_writel(val, mcpdm->io_base + reg); -} - -static inline int omap_mcpdm_read(u16 reg) -{ - return __raw_readl(mcpdm->io_base + reg); -} - -static void omap_mcpdm_reg_dump(void) -{ - dev_dbg(mcpdm->dev, "***********************\n"); - dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", - omap_mcpdm_read(MCPDM_IRQSTATUS_RAW)); - dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", - omap_mcpdm_read(MCPDM_IRQSTATUS)); - dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", - omap_mcpdm_read(MCPDM_IRQENABLE_SET)); - dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", - omap_mcpdm_read(MCPDM_IRQENABLE_CLR)); - dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", - omap_mcpdm_read(MCPDM_IRQWAKE_EN)); - dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", - omap_mcpdm_read(MCPDM_DMAENABLE_SET)); - dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", - omap_mcpdm_read(MCPDM_DMAENABLE_CLR)); - dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", - omap_mcpdm_read(MCPDM_DMAWAKEEN)); - dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", - omap_mcpdm_read(MCPDM_CTRL)); - dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", - omap_mcpdm_read(MCPDM_DN_DATA)); - dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", - omap_mcpdm_read(MCPDM_UP_DATA)); - dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", - omap_mcpdm_read(MCPDM_FIFO_CTRL_DN)); - dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", - omap_mcpdm_read(MCPDM_FIFO_CTRL_UP)); - dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n", - omap_mcpdm_read(MCPDM_DN_OFFSET)); - dev_dbg(mcpdm->dev, "***********************\n"); -} - -/* - * Takes the McPDM module in and out of reset state. - * Uplink and downlink can be reset individually. - */ -static void omap_mcpdm_reset_capture(int reset) -{ - int ctrl = omap_mcpdm_read(MCPDM_CTRL); - - if (reset) - ctrl |= SW_UP_RST; - else - ctrl &= ~SW_UP_RST; - - omap_mcpdm_write(MCPDM_CTRL, ctrl); -} - -static void omap_mcpdm_reset_playback(int reset) -{ - int ctrl = omap_mcpdm_read(MCPDM_CTRL); - - if (reset) - ctrl |= SW_DN_RST; - else - ctrl &= ~SW_DN_RST; - - omap_mcpdm_write(MCPDM_CTRL, ctrl); -} - -/* - * Enables the transfer through the PDM interface to/from the Phoenix - * codec by enabling the corresponding UP or DN channels. - */ -void omap_mcpdm_start(int stream) -{ - int ctrl = omap_mcpdm_read(MCPDM_CTRL); - - if (stream) - ctrl |= mcpdm->up_channels; - else - ctrl |= mcpdm->dn_channels; - - omap_mcpdm_write(MCPDM_CTRL, ctrl); -} - -/* - * Disables the transfer through the PDM interface to/from the Phoenix - * codec by disabling the corresponding UP or DN channels. - */ -void omap_mcpdm_stop(int stream) -{ - int ctrl = omap_mcpdm_read(MCPDM_CTRL); - - if (stream) - ctrl &= ~mcpdm->up_channels; - else - ctrl &= ~mcpdm->dn_channels; - - omap_mcpdm_write(MCPDM_CTRL, ctrl); -} - -/* - * Configures McPDM uplink for audio recording. - * This function should be called before omap_mcpdm_start. - */ -int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink) -{ - int irq_mask = 0; - int ctrl; - - if (!uplink) - return -EINVAL; - - mcpdm->uplink = uplink; - - /* Enable irq request generation */ - irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; - omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask); - - /* Configure uplink threshold */ - if (uplink->threshold > UP_THRES_MAX) - uplink->threshold = UP_THRES_MAX; - - omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold); - - /* Configure DMA controller */ - omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE); - - /* Set pdm out format */ - ctrl = omap_mcpdm_read(MCPDM_CTRL); - ctrl &= ~PDMOUTFORMAT; - ctrl |= uplink->format & PDMOUTFORMAT; - - /* Uplink channels */ - mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK); - - omap_mcpdm_write(MCPDM_CTRL, ctrl); - - return 0; -} - -/* - * Configures McPDM downlink for audio playback. - * This function should be called before omap_mcpdm_start. - */ -int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink) -{ - int irq_mask = 0; - int ctrl; - - if (!downlink) - return -EINVAL; - - mcpdm->downlink = downlink; - - /* Enable irq request generation */ - irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; - omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask); - - /* Configure uplink threshold */ - if (downlink->threshold > DN_THRES_MAX) - downlink->threshold = DN_THRES_MAX; - - omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold); - - /* Enable DMA request generation */ - omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE); - - /* Set pdm out format */ - ctrl = omap_mcpdm_read(MCPDM_CTRL); - ctrl &= ~PDMOUTFORMAT; - ctrl |= downlink->format & PDMOUTFORMAT; - - /* Downlink channels */ - mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK); - - omap_mcpdm_write(MCPDM_CTRL, ctrl); - - return 0; -} - -/* - * Cleans McPDM uplink configuration. - * This function should be called when the stream is closed. - */ -int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink) -{ - int irq_mask = 0; - - if (!uplink) - return -EINVAL; - - /* Disable irq request generation */ - irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; - omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask); - - /* Disable DMA request generation */ - omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE); - - /* Clear Downlink channels */ - mcpdm->up_channels = 0; - - mcpdm->uplink = NULL; - - return 0; -} - -/* - * Cleans McPDM downlink configuration. - * This function should be called when the stream is closed. - */ -int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink) -{ - int irq_mask = 0; - - if (!downlink) - return -EINVAL; - - /* Disable irq request generation */ - irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; - omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask); - - /* Disable DMA request generation */ - omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE); - - /* clear Downlink channels */ - mcpdm->dn_channels = 0; - - mcpdm->downlink = NULL; - - return 0; -} - -static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) -{ - struct omap_mcpdm *mcpdm_irq = dev_id; - int irq_status; - - irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS); - - /* Acknowledge irq event */ - omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status); - - if (irq & MCPDM_DN_IRQ_FULL) { - dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status); - omap_mcpdm_reset_playback(1); - omap_mcpdm_playback_open(mcpdm_irq->downlink); - omap_mcpdm_reset_playback(0); - } - - if (irq & MCPDM_DN_IRQ_EMPTY) { - dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status); - omap_mcpdm_reset_playback(1); - omap_mcpdm_playback_open(mcpdm_irq->downlink); - omap_mcpdm_reset_playback(0); - } - - if (irq & MCPDM_DN_IRQ) { - dev_dbg(mcpdm_irq->dev, "DN write request\n"); - } - - if (irq & MCPDM_UP_IRQ_FULL) { - dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status); - omap_mcpdm_reset_capture(1); - omap_mcpdm_capture_open(mcpdm_irq->uplink); - omap_mcpdm_reset_capture(0); - } - - if (irq & MCPDM_UP_IRQ_EMPTY) { - dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status); - omap_mcpdm_reset_capture(1); - omap_mcpdm_capture_open(mcpdm_irq->uplink); - omap_mcpdm_reset_capture(0); - } - - if (irq & MCPDM_UP_IRQ) { - dev_dbg(mcpdm_irq->dev, "UP write request\n"); - } - - return IRQ_HANDLED; -} - -int omap_mcpdm_request(void) -{ - int ret; - - clk_enable(mcpdm->clk); - - spin_lock(&mcpdm->lock); - - if (!mcpdm->free) { - dev_err(mcpdm->dev, "McPDM interface is in use\n"); - spin_unlock(&mcpdm->lock); - ret = -EBUSY; - goto err; - } - mcpdm->free = 0; - - spin_unlock(&mcpdm->lock); - - /* Disable lines while request is ongoing */ - omap_mcpdm_write(MCPDM_CTRL, 0x00); - - ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, - 0, "McPDM", (void *)mcpdm); - if (ret) { - dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n"); - goto err; - } - - return 0; - -err: - clk_disable(mcpdm->clk); - return ret; -} - -void omap_mcpdm_free(void) -{ - spin_lock(&mcpdm->lock); - if (mcpdm->free) { - dev_err(mcpdm->dev, "McPDM interface is already free\n"); - spin_unlock(&mcpdm->lock); - return; - } - mcpdm->free = 1; - spin_unlock(&mcpdm->lock); - - clk_disable(mcpdm->clk); - - free_irq(mcpdm->irq, (void *)mcpdm); -} - -/* Enable/disable DC offset cancelation for the analog - * headset path (PDM channels 1 and 2). - */ -int omap_mcpdm_set_offset(int offset1, int offset2) -{ - int offset; - - if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX)) - return -EINVAL; - - offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2); - - /* offset cancellation for channel 1 */ - if (offset1) - offset |= DN_OFST_RX1_EN; - else - offset &= ~DN_OFST_RX1_EN; - - /* offset cancellation for channel 2 */ - if (offset2) - offset |= DN_OFST_RX2_EN; - else - offset &= ~DN_OFST_RX2_EN; - - omap_mcpdm_write(MCPDM_DN_OFFSET, offset); - - return 0; -} - -int __devinit omap_mcpdm_probe(struct platform_device *pdev) -{ - struct resource *res; - int ret = 0; - - mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL); - if (!mcpdm) { - ret = -ENOMEM; - goto exit; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no resource\n"); - goto err_resource; - } - - spin_lock_init(&mcpdm->lock); - mcpdm->free = 1; - mcpdm->io_base = ioremap(res->start, resource_size(res)); - if (!mcpdm->io_base) { - ret = -ENOMEM; - goto err_resource; - } - - mcpdm->irq = platform_get_irq(pdev, 0); - - mcpdm->clk = clk_get(&pdev->dev, "pdm_ck"); - if (IS_ERR(mcpdm->clk)) { - ret = PTR_ERR(mcpdm->clk); - dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret); - goto err_clk; - } - - mcpdm->dev = &pdev->dev; - platform_set_drvdata(pdev, mcpdm); - - return 0; - -err_clk: - iounmap(mcpdm->io_base); -err_resource: - kfree(mcpdm); -exit: - return ret; -} - -int __devexit omap_mcpdm_remove(struct platform_device *pdev) -{ - struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev); - - platform_set_drvdata(pdev, NULL); - - clk_put(mcpdm_ptr->clk); - - iounmap(mcpdm_ptr->io_base); - - mcpdm_ptr->clk = NULL; - mcpdm_ptr->free = 0; - mcpdm_ptr->dev = NULL; - - kfree(mcpdm_ptr); - - return 0; -} - diff --git a/sound/soc/omap/mcpdm.h b/sound/soc/omap/mcpdm.h deleted file mode 100644 index df3e16fb51f..00000000000 --- a/sound/soc/omap/mcpdm.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * mcpdm.h -- Defines for McPDM driver - * - * Author: Jorge Eduardo Candelaria <x0107209@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -/* McPDM registers */ - -#define MCPDM_REVISION 0x00 -#define MCPDM_SYSCONFIG 0x10 -#define MCPDM_IRQSTATUS_RAW 0x24 -#define MCPDM_IRQSTATUS 0x28 -#define MCPDM_IRQENABLE_SET 0x2C -#define MCPDM_IRQENABLE_CLR 0x30 -#define MCPDM_IRQWAKE_EN 0x34 -#define MCPDM_DMAENABLE_SET 0x38 -#define MCPDM_DMAENABLE_CLR 0x3C -#define MCPDM_DMAWAKEEN 0x40 -#define MCPDM_CTRL 0x44 -#define MCPDM_DN_DATA 0x48 -#define MCPDM_UP_DATA 0x4C -#define MCPDM_FIFO_CTRL_DN 0x50 -#define MCPDM_FIFO_CTRL_UP 0x54 -#define MCPDM_DN_OFFSET 0x58 - -/* - * MCPDM_IRQ bit fields - * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR - */ - -#define MCPDM_DN_IRQ (1 << 0) -#define MCPDM_DN_IRQ_EMPTY (1 << 1) -#define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) -#define MCPDM_DN_IRQ_FULL (1 << 3) - -#define MCPDM_UP_IRQ (1 << 8) -#define MCPDM_UP_IRQ_EMPTY (1 << 9) -#define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) -#define MCPDM_UP_IRQ_FULL (1 << 11) - -#define MCPDM_DOWNLINK_IRQ_MASK 0x00F -#define MCPDM_UPLINK_IRQ_MASK 0xF00 - -/* - * MCPDM_DMAENABLE bit fields - */ - -#define DMA_DN_ENABLE 0x1 -#define DMA_UP_ENABLE 0x2 - -/* - * MCPDM_CTRL bit fields - */ - -#define PDM_UP1_EN 0x0001 -#define PDM_UP2_EN 0x0002 -#define PDM_UP3_EN 0x0004 -#define PDM_DN1_EN 0x0008 -#define PDM_DN2_EN 0x0010 -#define PDM_DN3_EN 0x0020 -#define PDM_DN4_EN 0x0040 -#define PDM_DN5_EN 0x0080 -#define PDMOUTFORMAT 0x0100 -#define CMD_INT 0x0200 -#define STATUS_INT 0x0400 -#define SW_UP_RST 0x0800 -#define SW_DN_RST 0x1000 -#define PDM_UP_MASK 0x007 -#define PDM_DN_MASK 0x0F8 -#define PDM_CMD_MASK 0x200 -#define PDM_STATUS_MASK 0x400 - - -#define PDMOUTFORMAT_LJUST (0 << 8) -#define PDMOUTFORMAT_RJUST (1 << 8) - -/* - * MCPDM_FIFO_CTRL bit fields - */ - -#define UP_THRES_MAX 0xF -#define DN_THRES_MAX 0xF - -/* - * MCPDM_DN_OFFSET bit fields - */ - -#define DN_OFST_RX1_EN 0x0001 -#define DN_OFST_RX2_EN 0x0100 - -#define DN_OFST_RX1 1 -#define DN_OFST_RX2 9 -#define DN_OFST_MAX 0x1F - -#define MCPDM_UPLINK 1 -#define MCPDM_DOWNLINK 2 - -struct omap_mcpdm_link { - int irq_mask; - int threshold; - int format; - int channels; -}; - -struct omap_mcpdm_platform_data { - unsigned long phys_base; - u16 irq; -}; - -struct omap_mcpdm { - struct device *dev; - unsigned long phys_base; - void __iomem *io_base; - u8 free; - int irq; - - spinlock_t lock; - struct omap_mcpdm_platform_data *pdata; - struct clk *clk; - struct omap_mcpdm_link *downlink; - struct omap_mcpdm_link *uplink; - struct completion irq_completion; - - int dn_channels; - int up_channels; -}; - -extern void omap_mcpdm_start(int stream); -extern void omap_mcpdm_stop(int stream); -extern int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink); -extern int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink); -extern int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink); -extern int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink); -extern int omap_mcpdm_request(void); -extern void omap_mcpdm_free(void); -extern int omap_mcpdm_set_offset(int offset1, int offset2); -int __devinit omap_mcpdm_probe(struct platform_device *pdev); -int __devexit omap_mcpdm_remove(struct platform_device *pdev); diff --git a/sound/soc/omap/omap-abe-coef.h b/sound/soc/omap/omap-abe-coef.h new file mode 100644 index 00000000000..6a169805b2e --- /dev/null +++ b/sound/soc/omap/omap-abe-coef.h @@ -0,0 +1,200 @@ +/* + * omap-abe-coef.h + * + * Copyright (C) 2010 Texas Instruments + * + * Contact: Ricardo Neri <ricardo.neri@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __OMAP_ABE_COEFFICIENTS_H__ +#define __OMAP_ABE_COEFFICIENTS_H__ + +/* + * ABE CONST AREA FOR EQUALIZER COEFFICIENTS + * + * TODO: These coefficents are for demonstration purposes. Set of + * coefficients can be computed for specific needs. + */ + +#define NBDL1EQ_PROFILES 4 /* Number of supported DL1EQ profiles */ +#define NBDL1COEFFS 25 /* Number of coefficients for DL1EQ profiles */ +#define NBDL20EQ_PROFILES 4 /* Number of supported DL2EQ_L profiles */ +#define NBDL21EQ_PROFILES 4 /* Number of supported DL2EQ_R profiles */ +#define NBDL2COEFFS 25 /* Number of coefficients of DL2EQ profiles */ +#define NBAMICEQ_PROFILES 3 /* Number of supported AMICEQ profiles */ +#define NBAMICCOEFFS 19 /* Number of coefficients of AMICEQ profiles */ +#define NBSDTEQ_PROFILES 4 /* Number of supported SDTEQ profiles */ +#define NBSDTCOEFFS 9 /* Number of coefficients for SDTEQ profiles */ +#define NBDMICEQ_PROFILES 3 /* Number of supported DMICEQ profiles */ +#define NBDMICCOEFFS 19 /* Number of coefficients of DMICEQ profiles */ + +/* + * Coefficients for DL1EQ + */ +const s32 dl1_equ_coeffs[NBDL1EQ_PROFILES][NBDL1COEFFS] = { +/* Flat response with Gain = 0dB */ + {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0x040002, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0}, + +/* 800Hz cut-off frequency and Gain = 0dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -7554223, + 708210, -708206, 7554225, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -12dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -3777112, + 5665669, -5665667, 3777112, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -20dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -1510844, + 4532536, -4532536, 1510844, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, +}; + +/* + * Coefficients for DL2EQ_L + */ +const s32 dl20_equ_coeffs[NBDL20EQ_PROFILES][NBDL2COEFFS] = { +/* Flat response with Gain = 0dB */ + {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0x040002, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0}, + +/* 800Hz cut-off frequency and Gain = 0dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -7554223, + 708210, -708206, 7554225, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -12dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -3777112, + 5665669, -5665667, 3777112, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -20dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -1510844, + 4532536, -4532536, 1510844, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, +}; + +/* + * Coefficients for DL2_EQ_R + */ +const s32 dl21_equ_coeffs[NBDL20EQ_PROFILES][NBDL2COEFFS] = { +/* Flat response with Gain = 0dB */ + {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0x040002, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0}, + +/* 800Hz cut-off frequency and Gain = 0dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -7554223, + 708210, -708206, 7554225, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/*800Hz cut-off frequency and Gain = -12dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -3777112, + 5665669, -5665667, 3777112, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -20dB */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, -1510844, + 4532536, -4532536, 1510844, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 6802833, -682266, 731554}, +}; + +/* + * Coefficients for DMICEQ + */ +const u32 dmic_equ_coeffs[NBDMICEQ_PROFILES][NBDMICCOEFFS] = { +/* 20kHz cut-off frequency and Gain = 0dB */ + {-4119413, -192384, -341428, -348088, + -151380, 151380, 348088, 341428, 192384, + 4119419, 1938156, -6935719, 775202, + -1801934, 2997698, -3692214, 3406822, + -2280190, 1042982}, + +/* 20kHz cut-off frequency and Gain = -12dB */ + {-1029873, -3078121, -5462817, -5569389, + -2422069, 2422071, 5569391, 5462819, + 3078123, 1029875, 1938188, -6935811, + 775210, -1801950, 2997722, -3692238, + 3406838, -2280198, 1042982}, + +/* 20kHz cut-off frequency and Gain = -18dB */ + {-514937, -1539061, -2731409, -2784693, + -1211033, 1211035, 2784695, 2731411, + 1539063, 514939, 1938188, -6935811, + 775210, -1801950, 2997722, -3692238, + 3406838, -2280198, 1042982}, +}; + +/* + * Coefficients for AMICEQ + */ +const u32 amic_equ_coeffs[NBAMICEQ_PROFILES][NBAMICCOEFFS] = { +/* 20kHz cut-off frequency and Gain = 0dB */ + {-4119413, -192384, -341428, -348088, + -151380, 151380, 348088, 341428, 192384, + 4119419, 1938156, -6935719, 775202, + -1801934, 2997698, -3692214, 3406822, + -2280190, 1042982}, + +/* 20kHz cut-off frequency and Gain = -12dB */ + {-1029873, -3078121, -5462817, -5569389, + -2422069, 2422071, 5569391, 5462819, + 3078123, 1029875, 1938188, -6935811, + 775210, -1801950, 2997722, -3692238, + 3406838, -2280198, 1042982}, + +/* 20kHz cut-off frequency and Gain = -18dB */ + {-514937, -1539061, -2731409, -2784693, + -1211033, 1211035, 2784695, 2731411, + 1539063, 514939, 1938188, -6935811, + 775210, -1801950, 2997722, -3692238, + 3406838, -2280198, 1042982}, +}; + + +/* + * Coefficients for SDTEQ + */ +const u32 sdt_equ_coeffs[NBSDTEQ_PROFILES][NBSDTCOEFFS] = { +/* Flat response with Gain = 0dB */ + {0, 0, 0, 0, 0x040002, 0, 0, 0, 0}, + +/* 800Hz cut-off frequency and Gain = 0dB */ + {0, -7554223, 708210, -708206, 7554225, + 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -12dB */ + {0, -3777112, 5665669, -5665667, 3777112, + 0, 6802833, -682266, 731554}, + +/* 800Hz cut-off frequency and Gain = -20dB */ + {0, -1510844, 4532536, -4532536, 1510844, + 0, 6802833, -682266, 731554} +}; + +#endif /* End of __OMAP_ABE_COEFFICIENTS_H__ */ diff --git a/sound/soc/omap/omap-abe-dsp.c b/sound/soc/omap/omap-abe-dsp.c new file mode 100644 index 00000000000..8ebc71f6fa3 --- /dev/null +++ b/sound/soc/omap/omap-abe-dsp.c @@ -0,0 +1,2163 @@ +/* + * omap-abe-dsp.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * Copyright (C) 2010 Texas Instruments Inc. + * + * Author : Liam Girdwood <lrg@slimlogic.co.uk> + * + */ + +#undef DEBUG + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include <linux/i2c/twl.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> +#include <linux/dma-mapping.h> + +#include <plat/omap_hwmod.h> +#include <plat/omap_device.h> +#include <plat/dma.h> +#include <plat/omap-pm.h> +#include <plat/prcm.h> +#include "../../../arch/arm/mach-omap2/powerdomain.h" +#include "../../../arch/arm/mach-omap2/pm.h" + + +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> +#include <sound/omap-abe-dsp.h> + +#include "omap-abe-dsp.h" +#include "omap-abe-coef.h" +#include "omap-abe.h" +#include "abe/abe_main.h" + +// TODO: change to S16 and use ARM SIMD to re-format to S32 +#define ABE_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +// TODO: make all these into virtual registers or similar - split out by type */ +#define ABE_NUM_MIXERS 22 +#define ABE_NUM_MUXES 12 +#define ABE_NUM_WIDGETS 46 /* TODO - refine this val */ +#define ABE_NUM_DAPM_REG \ + (ABE_NUM_MIXERS + ABE_NUM_MUXES + ABE_NUM_WIDGETS) +#define ABE_WIDGET_START (ABE_NUM_MIXERS + ABE_NUM_MUXES) +#define ABE_WIDGET_END (ABE_WIDGET_START + ABE_NUM_WIDGETS) +#define ABE_BE_START (ABE_WIDGET_START + 7) +#define ABE_BE_END (ABE_BE_START + 10) +#define ABE_MUX_BASE ABE_NUM_MIXERS + +/* Uplink MUX path identifiers from ROUTE_UL */ +#define ABE_MM_UL1(x) (x + ABE_NUM_MIXERS) +#define ABE_MM_UL2(x) (x + ABE_NUM_MIXERS + 8) +#define ABE_VX_UL(x) (x + ABE_NUM_MIXERS + 10) +#define ABE_WIDGET(x) (x + ABE_NUM_MIXERS + ABE_NUM_MUXES) +//#define ABE_BE_WIDGET(x) (x + ABE_NUM_MIXERS + ABE_NUM_MUXES) + +#define VIRT_SWITCH 0 + +// TODO: OPP bitmask - Use HAL version after update +#define ABE_OPP_25 0 +#define ABE_OPP_50 1 +#define ABE_OPP_100 2 + +#define ABE_ROUTES_UL 14 + +/* TODO: fine tune for ping pong - buffer is 2 periods of 12k each*/ +static const struct snd_pcm_hardware omap_abe_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .period_bytes_min = 4 * 1024, + .period_bytes_max = 24 * 1024, + .periods_min = 2, + .periods_max = 2, + .buffer_bytes_max = 24 * 1024 * 2, +}; + +/* + * ABE driver + * + * TODO: tasks 1,2,3,4,5,6,7,8 below + * + * This driver is responsible for :- + * 1) ABE init - including loading ABE firmware + * 2) ABE coefficient mgmt - inc user space re-calcs + * 8) Process ABE platform data + * + */ + +/* ABE private data */ +struct abe_data { + struct omap4_abe_dsp_pdata *abe_pdata; + struct platform_device *pdev; + struct snd_soc_platform *platform; + + struct delayed_work delayed_work; + struct mutex mutex; + struct mutex opp_mutex; + + struct clk *clk; + + void __iomem *io_base; + int irq; + int opp; + + int fe_id; + + unsigned int dl1_equ_profile; + unsigned int dl20_equ_profile; + unsigned int dl21_equ_profile; + unsigned int sdt_equ_profile; + unsigned int amic_equ_profile; + unsigned int dmic_equ_profile; + + int active; + + /* DAPM mixer config - TODO: some of this can be replaced with HAL update */ + u32 dapm[ABE_NUM_DAPM_REG]; + + u16 router[16]; + + int loss_count; + + int first_irq; + + struct snd_pcm_substream *psubs; + +}; + +static struct abe_data *abe; + +static struct powerdomain *abe_pwrdm; + +// TODO: map to the new version of HAL +static unsigned int abe_dsp_read(struct snd_soc_platform *platform, + unsigned int reg) +{ + struct abe_data *priv = snd_soc_platform_get_drvdata(platform); + return priv->dapm[reg]; +} + +static int abe_dsp_write(struct snd_soc_platform *platform, unsigned int reg, + unsigned int val) +{ + struct abe_data *priv = snd_soc_platform_get_drvdata(platform); + priv->dapm[reg] = val; + + //dev_dbg(platform->dev, "fe: %d widget %d %s\n", abe->fe_id, + // reg - ABE_WIDGET_START, val ? "on" : "off"); + return 0; +} + +static void abe_irq_pingpong_subroutine(void) +{ + u32 dst, n_bytes; + + abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); + + /* Do not call ALSA function for first IRQ */ + if (abe->first_irq) { + abe->first_irq = 0; + } else { + if (abe->psubs) + snd_pcm_period_elapsed(abe->psubs); + } +} + +static irqreturn_t abe_irq_handler(int irq, void *dev_id) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + /* TODO: handle underruns/overruns/errors */ + pm_runtime_get_sync(&pdev->dev); + abe_clear_irq(); + abe_irq_processing(); + pm_runtime_put_sync(&pdev->dev); + + return IRQ_HANDLED; +} + +static int abe_init_engine(struct snd_soc_platform *platform) +{ + struct abe_data *priv = snd_soc_platform_get_drvdata(platform); +#ifndef CONFIG_PM_RUNTIME + struct omap4_abe_dsp_pdata *pdata = priv->abe_pdata; +#endif + struct platform_device *pdev = priv->pdev; + abe_equ_t dl2_eq; + int ret = 0; + + abe_init_mem(abe->io_base); + + /* aess_clk has to be enabled to access hal register. + * Disable the clk after it has been used. + */ + pm_runtime_get_sync(&pdev->dev); + + ret = request_threaded_irq(abe->irq, NULL, abe_irq_handler, + IRQF_ONESHOT, "ABE", (void *)abe); + if (ret) { + dev_err(platform->dev, "request for ABE IRQ %d failed %d\n", + abe->irq, ret); + return ret; + } + + abe_reset_hal(); + + abe_load_fw(); // TODO: use fw API here + + /* Config OPP 100 for now */ + mutex_lock(&abe->opp_mutex); + abe_set_opp_processing(ABE_OPP100); + abe->opp = 100; + mutex_unlock(&abe->opp_mutex); + + /* "tick" of the audio engine */ + abe_write_event_generator(EVENT_TIMER); + + dl2_eq.equ_length = NBDL2COEFFS; + + /* build the coefficient parameter for the equalizer api */ + memcpy(dl2_eq.coef.type1, dl20_equ_coeffs[1], + sizeof(dl20_equ_coeffs[1])); + + /* load the high-pass coefficient of IHF-Right */ + abe_write_equalizer(EQ2L, &dl2_eq); + abe->dl20_equ_profile = 1; + + /* build the coefficient parameter for the equalizer api */ + memcpy(dl2_eq.coef.type1, dl21_equ_coeffs[1], + sizeof(dl21_equ_coeffs[1])); + + /* load the high-pass coefficient of IHF-Left */ + abe_write_equalizer(EQ2R, &dl2_eq); + abe->dl21_equ_profile = 1; + + pm_runtime_put_sync(&pdev->dev); + + /* set initial state to all-pass with gain=1 coefficients */ + abe->amic_equ_profile = 0; + abe->dmic_equ_profile = 0; + abe->dl1_equ_profile = 0; + abe->sdt_equ_profile = 0; + + + return ret; +} + +void abe_dsp_pm_get(void) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); +} + +void abe_dsp_pm_put(void) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_put_sync(&pdev->dev); +} + +void abe_dsp_shutdown(void) +{ + if (!abe->active && !abe_check_activity()) { + abe_set_opp_processing(ABE_OPP25); + abe->opp = 25; + abe_stop_event_generator(); + udelay(250); + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 0); + } +} + +void abe_dsp_mcpdm_shutdown(void) +{ + mutex_lock(&abe->mutex); + + abe_dsp_shutdown(); + + mutex_unlock(&abe->mutex); + + return; +} + +/* + * These TLV settings will need fine tuned for each individual control + */ + +/* Media DL1 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(mm_dl1_tlv, -12000, 100, 3000); + +/* Media DL1 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(tones_dl1_tlv, -12000, 100, 3000); + +/* Media DL1 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(voice_dl1_tlv, -12000, 100, 3000); + +/* Media DL1 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(capture_dl1_tlv, -12000, 100, 3000); + +/* Media DL2 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(mm_dl2_tlv, -12000, 100, 3000); + +/* Media DL2 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(tones_dl2_tlv, -12000, 100, 3000); + +/* Media DL2 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(voice_dl2_tlv, -12000, 100, 3000); + +/* Media DL2 volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(capture_dl2_tlv, -12000, 100, 3000); + +/* SDT volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(sdt_ul_tlv, -12000, 100, 3000); + +/* SDT volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(sdt_dl_tlv, -12000, 100, 3000); + +/* AUDUL volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(audul_mm_tlv, -12000, 100, 3000); + +/* AUDUL volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(audul_tones_tlv, -12000, 100, 3000); + +/* AUDUL volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(audul_vx_ul_tlv, -12000, 100, 3000); + +/* AUDUL volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(audul_vx_dl_tlv, -12000, 100, 3000); + +/* VXREC volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(vxrec_mm_dl_tlv, -12000, 100, 3000); + +/* VXREC volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(vxrec_tones_tlv, -12000, 100, 3000); + +/* VXREC volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(vxrec_vx_dl_tlv, -12000, 100, 3000); + +/* VXREC volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(vxrec_vx_ul_tlv, -12000, 100, 3000); + +/* DMIC volume control from -120 to 30 dB in 1 dB steps */ +static DECLARE_TLV_DB_SCALE(dmic_tlv, -12000, 100, 3000); + +//TODO: we have to use the shift value atm to represent register id due to current HAL +static int dl1_put_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + abe_enable_gain(MIXDL1, mc->reg); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + abe_disable_gain(MIXDL1, mc->reg); + } + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int dl2_put_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + abe_enable_gain(MIXDL2, mc->reg); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + abe_disable_gain(MIXDL2, mc->reg); + } + + pm_runtime_put_sync(&pdev->dev); + return 1; +} + +static int audio_ul_put_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + abe_enable_gain(MIXAUDUL, mc->reg); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + abe_disable_gain(MIXAUDUL, mc->reg); + } + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int vxrec_put_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + abe_enable_gain(MIXVXREC, mc->reg); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + abe_disable_gain(MIXVXREC, mc->reg); + } + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int sdt_put_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + abe_enable_gain(MIXSDT, mc->reg); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + abe_disable_gain(MIXSDT, mc->reg); + } + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int abe_get_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + ucontrol->value.integer.value[0] = abe->dapm[mc->shift]; + + return 0; +} + +/* router IDs that match our mixer strings */ +static const abe_router_t router[] = { + ZERO_labelID, /* strangely this is not 0 */ + DMIC1_L_labelID, DMIC1_R_labelID, + DMIC2_L_labelID, DMIC2_R_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, + BT_UL_L_labelID, BT_UL_R_labelID, + AMIC_L_labelID, AMIC_R_labelID, + VX_REC_L_labelID, VX_REC_R_labelID, +}; + +static int ul_mux_put_route(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + int mux = ucontrol->value.enumerated.item[0]; + int reg = e->reg - ABE_MUX_BASE, i; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (mux >= ABE_ROUTES_UL) + return 0; + + if (reg < 8) { + /* 0 .. 9 = MM_UL */ + abe->router[reg] = router[mux]; + } else if (reg < 12) { + /* 10 .. 11 = MM_UL2 */ + /* 12 .. 13 = VX_UL */ + abe->router[reg + 2] = router[mux]; + } + + /* there is a 2 slot gap in the table, making it ABE_ROUTES_UL + 2 in size */ + for (i = 0; i < ABE_ROUTES_UL + 2; i++) + dev_dbg(widget->dapm->dev, "router table [%d] = %d\n", i, abe->router[i]); + + /* 2nd arg here is unused */ + abe_set_router_configuration(UPROUTE, 0, (u32 *)abe->router); + + abe->dapm[e->reg] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mux_update_power(widget, kcontrol, abe->dapm[e->reg], mux, e); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int ul_mux_get_route(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_enum *e = + (struct soc_enum *)kcontrol->private_value; + + // TODO: get mux via HAL + + ucontrol->value.integer.value[0] = abe->dapm[e->reg]; + return 0; +} + + +static int abe_put_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + if (ucontrol->value.integer.value[0]) { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 1); + } else { + abe->dapm[mc->shift] = ucontrol->value.integer.value[0]; + snd_soc_dapm_mixer_update_power(widget, kcontrol, 0); + } + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + + +static int volume_put_sdt_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + + abe_write_mixer(MIXSDT, -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_0MS, mc->reg); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_put_audul_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_write_mixer(MIXAUDUL, -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_0MS, mc->reg); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_put_vxrec_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_write_mixer(MIXVXREC, -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_0MS, mc->reg); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_put_dl1_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_write_mixer(MIXDL1, -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_0MS, mc->reg); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_put_dl2_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_write_mixer(MIXDL2, -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_0MS, mc->reg); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_put_dmic(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_write_gain(mc->reg, + -12000 + (ucontrol->value.integer.value[0] * 100), + RAMP_20MS, mc->shift); + abe_write_gain(mc->reg, + -12000 + (ucontrol->value.integer.value[1] * 100), + RAMP_20MS, mc->rshift); + pm_runtime_put_sync(&pdev->dev); + + return 1; +} + +static int volume_get_dl1_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + u32 val; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + pm_runtime_get_sync(&pdev->dev); + abe_read_mixer(MIXDL1, &val, mc->reg); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int volume_get_dl2_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + u32 val; + + pm_runtime_get_sync(&pdev->dev); + abe_read_mixer(MIXDL2, &val, mc->reg); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int volume_get_audul_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + u32 val; + + pm_runtime_get_sync(&pdev->dev); + abe_read_mixer(MIXAUDUL, &val, mc->reg); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int volume_get_vxrec_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + u32 val; + + pm_runtime_get_sync(&pdev->dev); + abe_read_mixer(MIXVXREC, &val, mc->reg); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int volume_get_sdt_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + u32 val; + + pm_runtime_get_sync(&pdev->dev); + abe_read_mixer(MIXSDT, &val, mc->reg); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int volume_get_dmic(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + u32 val; + + pm_runtime_get_sync(&pdev->dev); + abe_read_gain(mc->reg, &val, mc->shift); + ucontrol->value.integer.value[0] = (val + 12000) / 100; + abe_read_gain(mc->reg, &val, mc->rshift); + ucontrol->value.integer.value[1] = (val + 12000) / 100; + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int abe_get_equalizer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_enum *eqc = (struct soc_enum *)kcontrol->private_value; + switch (eqc->reg) { + case EQ1: + ucontrol->value.integer.value[0] = abe->dl1_equ_profile; + break; + case EQ2L: + ucontrol->value.integer.value[0] = abe->dl20_equ_profile; + break; + case EQ2R: + ucontrol->value.integer.value[0] = abe->dl21_equ_profile; + break; + case EQAMIC: + ucontrol->value.integer.value[0] = abe->amic_equ_profile; + break; + case EQDMIC: + ucontrol->value.integer.value[0] = abe->dmic_equ_profile; + break; + case EQSDT: + ucontrol->value.integer.value[0] = abe->sdt_equ_profile; + break; + default: + break; + } + + return 0; +} + +static void abe_dsp_set_equalizer(unsigned int id, unsigned int profile) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + abe_equ_t equ_params; + + switch (id) { + case EQ1: + equ_params.equ_length = NBDL1COEFFS; + memcpy(equ_params.coef.type1, dl1_equ_coeffs[profile], + sizeof(dl1_equ_coeffs[profile])); + abe->dl1_equ_profile = profile; + break; + case EQ2L: + equ_params.equ_length = NBDL2COEFFS; + memcpy(equ_params.coef.type1, dl20_equ_coeffs[profile], + sizeof(dl20_equ_coeffs[profile])); + abe->dl20_equ_profile = profile; + break; + case EQ2R: + equ_params.equ_length = NBDL2COEFFS; + memcpy(equ_params.coef.type1, dl21_equ_coeffs[profile], + sizeof(dl21_equ_coeffs[profile])); + abe->dl21_equ_profile = profile; + break; + case EQAMIC: + equ_params.equ_length = NBAMICCOEFFS; + memcpy(equ_params.coef.type1, amic_equ_coeffs[profile], + sizeof(amic_equ_coeffs[profile])); + abe->amic_equ_profile = profile; + break; + case EQDMIC: + equ_params.equ_length = NBDMICCOEFFS; + memcpy(equ_params.coef.type1, dmic_equ_coeffs[profile], + sizeof(dmic_equ_coeffs[profile])); + abe->dmic_equ_profile = profile; + break; + case EQSDT: + equ_params.equ_length = NBSDTCOEFFS; + memcpy(equ_params.coef.type1, sdt_equ_coeffs[profile], + sizeof(sdt_equ_coeffs[profile])); + abe->sdt_equ_profile = profile; + break; + default: + return; + } + + pm_runtime_get_sync(&pdev->dev); + abe_write_equalizer(id, &equ_params); + pm_runtime_put_sync(&pdev->dev); +} + +static int abe_put_equalizer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_enum *eqc = (struct soc_enum *)kcontrol->private_value; + u16 val = ucontrol->value.enumerated.item[0]; + + abe_dsp_set_equalizer(eqc->reg, val); + + return 1; +} + +static const char *dl1_equ_texts[] = { + "Flat response", + "High-pass 0dB", + "High-pass -12dB", + "High-pass -20dB", +}; + +static const char *dl20_equ_texts[] = { + "Flat response", + "High-pass 0dB", + "High-pass -12dB", + "High-pass -20dB", +}; + +static const char *dl21_equ_texts[] = { + "Flat response", + "High-pass 0dB", + "High-pass -12dB", + "High-pass -20dB", +}; + +static const char *amic_equ_texts[] = { + "High-pass 0dB", + "High-pass -12dB", + "High-pass -18dB", +}; + +static const char *dmic_equ_texts[] = { + "High-pass 0dB", + "High-pass -12dB", + "High-pass -18dB", +}; + +static const char *sdt_equ_texts[] = { + "Flat response", + "High-pass 0dB", + "High-pass -12dB", + "High-pass -20dB", +}; + +static const struct soc_enum dl1_equalizer_enum = + SOC_ENUM_SINGLE(EQ1, 0, NBDL1EQ_PROFILES, dl1_equ_texts); + +static const struct soc_enum dl20_equalizer_enum = + SOC_ENUM_SINGLE(EQ2L, 0, NBDL20EQ_PROFILES, dl20_equ_texts); + +static const struct soc_enum dl21_equalizer_enum = + SOC_ENUM_SINGLE(EQ2R, 0, NBDL21EQ_PROFILES, dl21_equ_texts); + +static const struct soc_enum amic_equalizer_enum = + SOC_ENUM_SINGLE(EQAMIC, 0, NBAMICEQ_PROFILES, amic_equ_texts); + +static const struct soc_enum dmic_equalizer_enum = + SOC_ENUM_SINGLE(EQDMIC, 0, NBDMICEQ_PROFILES, dmic_equ_texts); + +static const struct soc_enum sdt_equalizer_enum = + SOC_ENUM_SINGLE(EQSDT, 0, NBSDTEQ_PROFILES, sdt_equ_texts); + +static const char *route_ul_texts[] = + {"None", "DMic0L", "DMic0R", "DMic1L", "DMic1R", "DMic2L", "DMic2R", + "BT Left", "BT Right", "AMic0", "AMic1", "VX Left", "VX Right"}; + +/* ROUTE_UL Mux table */ +static const struct soc_enum abe_enum[] = { + SOC_ENUM_SINGLE(ABE_MM_UL1(0), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(1), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(2), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(3), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(4), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(5), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(6), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL1(7), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL2(0), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_MM_UL2(1), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_VX_UL(0), 0, 13, route_ul_texts), + SOC_ENUM_SINGLE(ABE_VX_UL(1), 0, 13, route_ul_texts), +}; + +static const struct snd_kcontrol_new mm_ul00_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[0], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul01_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[1], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul02_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[2], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul03_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[3], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul04_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[4], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul05_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[5], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul06_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[6], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul07_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[7], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul10_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[8], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_ul11_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[9], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_vx0_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[10], + ul_mux_get_route, ul_mux_put_route); + +static const struct snd_kcontrol_new mm_vx1_control = + SOC_DAPM_ENUM_EXT("Route", abe_enum[11], + ul_mux_get_route, ul_mux_put_route); + +/* DL1 mixer paths */ +static const struct snd_kcontrol_new dl1_mixer_controls[] = { + SOC_SINGLE_EXT("Tones", MIX_DL1_INPUT_TONES, 0, 1, 0, + abe_get_mixer, dl1_put_mixer), + SOC_SINGLE_EXT("Voice", MIX_DL1_INPUT_VX_DL, 1, 1, 0, + abe_get_mixer, dl1_put_mixer), + SOC_SINGLE_EXT("Capture", MIX_DL1_INPUT_MM_UL2, 2, 1, 0, + abe_get_mixer, dl1_put_mixer), + SOC_SINGLE_EXT("Multimedia", MIX_DL1_INPUT_MM_DL, 3, 1, 0, + abe_get_mixer, dl1_put_mixer), +}; + +/* DL2 mixer paths */ +static const struct snd_kcontrol_new dl2_mixer_controls[] = { + SOC_SINGLE_EXT("Tones", MIX_DL2_INPUT_TONES, 4, 1, 0, + abe_get_mixer, dl2_put_mixer), + SOC_SINGLE_EXT("Voice", MIX_DL2_INPUT_VX_DL, 5, 1, 0, + abe_get_mixer, dl2_put_mixer), + SOC_SINGLE_EXT("Capture", MIX_DL2_INPUT_MM_UL2, 6, 1, 0, + abe_get_mixer, dl2_put_mixer), + SOC_SINGLE_EXT("Multimedia", MIX_DL2_INPUT_MM_DL, 7, 1, 0, + abe_get_mixer, dl2_put_mixer), +}; + +/* AUDUL ("Voice Capture Mixer") mixer paths */ +static const struct snd_kcontrol_new audio_ul_mixer_controls[] = { + SOC_SINGLE_EXT("Tones Playback", MIX_AUDUL_INPUT_TONES, 8, 1, 0, + abe_get_mixer, audio_ul_put_mixer), + SOC_SINGLE_EXT("Media Playback", MIX_AUDUL_INPUT_MM_DL, 9, 1, 0, + abe_get_mixer, audio_ul_put_mixer), + SOC_SINGLE_EXT("Capture", MIX_AUDUL_INPUT_UPLINK, 10, 1, 0, + abe_get_mixer, audio_ul_put_mixer), +}; + +/* VXREC ("Capture Mixer") mixer paths */ +static const struct snd_kcontrol_new vx_rec_mixer_controls[] = { + SOC_SINGLE_EXT("Tones", MIX_VXREC_INPUT_TONES, 11, 1, 0, + abe_get_mixer, vxrec_put_mixer), + SOC_SINGLE_EXT("Voice Playback", MIX_VXREC_INPUT_VX_DL, 12, 1, 0, + abe_get_mixer, vxrec_put_mixer), + SOC_SINGLE_EXT("Voice Capture", MIX_VXREC_INPUT_VX_UL, 13, 1, 0, + abe_get_mixer, vxrec_put_mixer), + SOC_SINGLE_EXT("Media Playback", MIX_VXREC_INPUT_MM_DL, 14, 1, 0, + abe_get_mixer, vxrec_put_mixer), +}; + +/* SDT ("Sidetone Mixer") mixer paths */ +static const struct snd_kcontrol_new sdt_mixer_controls[] = { + SOC_SINGLE_EXT("Capture", MIX_SDT_INPUT_UP_MIXER, 15, 1, 0, + abe_get_mixer, sdt_put_mixer), + SOC_SINGLE_EXT("Playback", MIX_SDT_INPUT_DL1_MIXER, 16, 1, 0, + abe_get_mixer, sdt_put_mixer), +}; + +/* Virtual PDM_DL Switch */ +static const struct snd_kcontrol_new pdm_dl1_switch_controls = + SOC_SINGLE_EXT("Switch", VIRT_SWITCH, 17, 1, 0, + abe_get_mixer, abe_put_switch); + +/* Virtual BT_VX_DL Switch */ +static const struct snd_kcontrol_new bt_vx_dl_switch_controls = + SOC_SINGLE_EXT("Switch", VIRT_SWITCH, 18, 1, 0, + abe_get_mixer, abe_put_switch); + +/* Virtual MM_EXT_DL Switch */ +static const struct snd_kcontrol_new mm_ext_dl_switch_controls = + SOC_SINGLE_EXT("Switch", VIRT_SWITCH, 19, 1, 0, + abe_get_mixer, abe_put_switch); + +/* Virtual MM_EXT_UL Switch */ +static const struct snd_kcontrol_new mm_ext_ul_switch_controls = + SOC_SINGLE_EXT("Switch", VIRT_SWITCH, 20, 1, 0, + abe_get_mixer, abe_put_switch); + +/* Virtual PDM_UL Switch */ +static const struct snd_kcontrol_new pdm_ul1_switch_controls = + SOC_SINGLE_EXT("Switch", VIRT_SWITCH, 21, 1, 0, + abe_get_mixer, abe_put_switch); + +static const struct snd_kcontrol_new abe_controls[] = { + /* DL1 mixer gains */ + SOC_SINGLE_EXT_TLV("DL1 Media Playback Volume", + MIX_DL1_INPUT_MM_DL, 0, 149, 0, + volume_get_dl1_mixer, volume_put_dl1_mixer, mm_dl1_tlv), + SOC_SINGLE_EXT_TLV("DL1 Tones Playback Volume", + MIX_DL1_INPUT_TONES, 0, 149, 0, + volume_get_dl1_mixer, volume_put_dl1_mixer, tones_dl1_tlv), + SOC_SINGLE_EXT_TLV("DL1 Voice Playback Volume", + MIX_DL1_INPUT_VX_DL, 0, 149, 0, + volume_get_dl1_mixer, volume_put_dl1_mixer, voice_dl1_tlv), + SOC_SINGLE_EXT_TLV("DL1 Capture Playback Volume", + MIX_DL1_INPUT_MM_UL2, 0, 149, 0, + volume_get_dl1_mixer, volume_put_dl1_mixer, capture_dl1_tlv), + + /* DL2 mixer gains */ + SOC_SINGLE_EXT_TLV("DL2 Media Playback Volume", + MIX_DL2_INPUT_MM_DL, 0, 149, 0, + volume_get_dl2_mixer, volume_put_dl2_mixer, mm_dl2_tlv), + SOC_SINGLE_EXT_TLV("DL2 Tones Playback Volume", + MIX_DL2_INPUT_TONES, 0, 149, 0, + volume_get_dl2_mixer, volume_put_dl2_mixer, tones_dl2_tlv), + SOC_SINGLE_EXT_TLV("DL2 Voice Playback Volume", + MIX_DL2_INPUT_VX_DL, 0, 149, 0, + volume_get_dl2_mixer, volume_put_dl2_mixer, voice_dl2_tlv), + SOC_SINGLE_EXT_TLV("DL2 Capture Playback Volume", + MIX_DL2_INPUT_MM_UL2, 0, 149, 0, + volume_get_dl2_mixer, volume_put_dl2_mixer, capture_dl2_tlv), + + /* VXREC mixer gains */ + SOC_SINGLE_EXT_TLV("VXREC Media Volume", + MIX_VXREC_INPUT_MM_DL, 0, 149, 0, + volume_get_vxrec_mixer, volume_put_vxrec_mixer, vxrec_mm_dl_tlv), + SOC_SINGLE_EXT_TLV("VXREC Tones Volume", + MIX_VXREC_INPUT_TONES, 0, 149, 0, + volume_get_vxrec_mixer, volume_put_vxrec_mixer, vxrec_tones_tlv), + SOC_SINGLE_EXT_TLV("VXREC Voice DL Volume", + MIX_VXREC_INPUT_VX_UL, 0, 149, 0, + volume_get_vxrec_mixer, volume_put_vxrec_mixer, vxrec_vx_dl_tlv), + SOC_SINGLE_EXT_TLV("VXREC Voice UL Volume", + MIX_VXREC_INPUT_VX_DL, 0, 149, 0, + volume_get_vxrec_mixer, volume_put_vxrec_mixer, vxrec_vx_ul_tlv), + + /* AUDUL mixer gains */ + SOC_SINGLE_EXT_TLV("AUDUL Media Volume", + MIX_AUDUL_INPUT_MM_DL, 0, 149, 0, + volume_get_audul_mixer, volume_put_audul_mixer, audul_mm_tlv), + SOC_SINGLE_EXT_TLV("AUDUL Tones Volume", + MIX_AUDUL_INPUT_TONES, 0, 149, 0, + volume_get_audul_mixer, volume_put_audul_mixer, audul_tones_tlv), + SOC_SINGLE_EXT_TLV("AUDUL Voice UL Volume", + MIX_AUDUL_INPUT_UPLINK, 0, 149, 0, + volume_get_audul_mixer, volume_put_audul_mixer, audul_vx_ul_tlv), + SOC_SINGLE_EXT_TLV("AUDUL Voice DL Volume", + MIX_AUDUL_INPUT_VX_DL, 0, 149, 0, + volume_get_audul_mixer, volume_put_audul_mixer, audul_vx_dl_tlv), + + /* SDT mixer gains */ + SOC_SINGLE_EXT_TLV("SDT UL Volume", + MIX_SDT_INPUT_UP_MIXER, 0, 149, 0, + volume_get_sdt_mixer, volume_put_sdt_mixer, sdt_ul_tlv), + SOC_SINGLE_EXT_TLV("SDT DL Volume", + MIX_SDT_INPUT_DL1_MIXER, 0, 149, 0, + volume_get_sdt_mixer, volume_put_sdt_mixer, sdt_dl_tlv), + + /* DMIC gains */ + SOC_DOUBLE_EXT_TLV("DMIC1 UL Volume", + GAINS_DMIC1, GAIN_LEFT_OFFSET, GAIN_RIGHT_OFFSET, 149, 0, + volume_get_dmic, volume_put_dmic, dmic_tlv), + + SOC_DOUBLE_EXT_TLV("DMIC2 UL Volume", + GAINS_DMIC2, GAIN_LEFT_OFFSET, GAIN_RIGHT_OFFSET, 149, 0, + volume_get_dmic, volume_put_dmic, dmic_tlv), + + SOC_DOUBLE_EXT_TLV("DMIC3 UL Volume", + GAINS_DMIC3, GAIN_LEFT_OFFSET, GAIN_RIGHT_OFFSET, 149, 0, + volume_get_dmic, volume_put_dmic, dmic_tlv), + + SOC_ENUM_EXT("DL1 Equalizer", + dl1_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), + + SOC_ENUM_EXT("DL2 Left Equalizer", + dl20_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), + + SOC_ENUM_EXT("DL2 Right Equalizer", + dl21_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), + + SOC_ENUM_EXT("AMIC Equalizer", + amic_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), + + SOC_ENUM_EXT("DMIC Equalizer", + dmic_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), + + SOC_ENUM_EXT("Sidetone Equalizer", + sdt_equalizer_enum , + abe_get_equalizer, abe_put_equalizer), +}; + +static const struct snd_soc_dapm_widget abe_dapm_widgets[] = { + + /* Frontend AIFs */ + SND_SOC_DAPM_AIF_IN("TONES_DL", "Tones Playback", 0, + ABE_WIDGET(0), ABE_OPP_25, 0), + SND_SOC_DAPM_AIF_IN("VX_DL", "Voice Playback", 0, + ABE_WIDGET(1), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_OUT("VX_UL", "Voice Capture", 0, + ABE_WIDGET(2), ABE_OPP_50, 0), + /* the MM_UL mapping is intentional */ + SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, + ABE_WIDGET(3), ABE_OPP_100, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, + ABE_WIDGET(4), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_IN("MM_DL", " MultiMedia1 Playback", 0, + ABE_WIDGET(5), ABE_OPP_25, 0), + SND_SOC_DAPM_AIF_IN("MM_DL_LP", " MultiMedia1 LP Playback", 0, + ABE_WIDGET(5), ABE_OPP_25, 0), + SND_SOC_DAPM_AIF_IN("VIB_DL", "Vibra Playback", 0, + ABE_WIDGET(6), ABE_OPP_100, 0), + SND_SOC_DAPM_AIF_IN("MODEM_DL", "MODEM Playback", 0, + ABE_WIDGET(7), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_OUT("MODEM_UL", "MODEM Capture", 0, + ABE_WIDGET(8), ABE_OPP_50, 0), + + /* Backend DAIs */ + // FIXME: must match BE order in abe_dai.h + SND_SOC_DAPM_AIF_IN("PDM_UL1", "Analog Capture", 0, + ABE_WIDGET(9), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_OUT("PDM_DL1", "HS Playback", 0, + ABE_WIDGET(10), ABE_OPP_25, 0), + SND_SOC_DAPM_AIF_OUT("PDM_DL2", "HF Playback", 0, + ABE_WIDGET(11), ABE_OPP_100, 0), + SND_SOC_DAPM_AIF_OUT("PDM_VIB", "Vibra Playback", 0, + ABE_WIDGET(12), ABE_OPP_100, 0), + SND_SOC_DAPM_AIF_IN("BT_VX_UL", "BT Capture", 0, + ABE_WIDGET(13), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_OUT("BT_VX_DL", "BT Playback", 0, + ABE_WIDGET(14), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_IN("MM_EXT_UL", "FM Capture", 0, + ABE_WIDGET(15), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_OUT("MM_EXT_DL", "FM Playback", 0, + ABE_WIDGET(16), ABE_OPP_25, 0), + SND_SOC_DAPM_AIF_IN("DMIC0", "DMIC0 Capture", 0, + ABE_WIDGET(17), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_IN("DMIC1", "DMIC1 Capture", 0, + ABE_WIDGET(18), ABE_OPP_50, 0), + SND_SOC_DAPM_AIF_IN("DMIC2", "DMIC2 Capture", 0, + ABE_WIDGET(19), ABE_OPP_50, 0), + + /* ROUTE_UL Capture Muxes */ + SND_SOC_DAPM_MUX("MUX_UL00", + ABE_WIDGET(20), ABE_OPP_50, 0, &mm_ul00_control), + SND_SOC_DAPM_MUX("MUX_UL01", + ABE_WIDGET(21), ABE_OPP_50, 0, &mm_ul01_control), + SND_SOC_DAPM_MUX("MUX_UL02", + ABE_WIDGET(22), ABE_OPP_50, 0, &mm_ul02_control), + SND_SOC_DAPM_MUX("MUX_UL03", + ABE_WIDGET(23), ABE_OPP_50, 0, &mm_ul03_control), + SND_SOC_DAPM_MUX("MUX_UL04", + ABE_WIDGET(24), ABE_OPP_50, 0, &mm_ul04_control), + SND_SOC_DAPM_MUX("MUX_UL05", + ABE_WIDGET(25), ABE_OPP_50, 0, &mm_ul05_control), + SND_SOC_DAPM_MUX("MUX_UL06", + ABE_WIDGET(26), ABE_OPP_50, 0, &mm_ul06_control), + SND_SOC_DAPM_MUX("MUX_UL07", + ABE_WIDGET(27), ABE_OPP_50, 0, &mm_ul07_control), + SND_SOC_DAPM_MUX("MUX_UL10", + ABE_WIDGET(28), ABE_OPP_50, 0, &mm_ul10_control), + SND_SOC_DAPM_MUX("MUX_UL11", + ABE_WIDGET(29), ABE_OPP_50, 0, &mm_ul11_control), + SND_SOC_DAPM_MUX("MUX_VX0", + ABE_WIDGET(30), ABE_OPP_50, 0, &mm_vx0_control), + SND_SOC_DAPM_MUX("MUX_VX1", + ABE_WIDGET(31), ABE_OPP_50, 0, &mm_vx1_control), + + /* DL1 & DL2 Playback Mixers */ + SND_SOC_DAPM_MIXER("DL1 Mixer", + ABE_WIDGET(32), ABE_OPP_25, 0, dl1_mixer_controls, + ARRAY_SIZE(dl1_mixer_controls)), + SND_SOC_DAPM_MIXER("DL2 Mixer", + ABE_WIDGET(33), ABE_OPP_100, 0, dl2_mixer_controls, + ARRAY_SIZE(dl2_mixer_controls)), + + /* DL1 Mixer Input volumes ?????*/ + SND_SOC_DAPM_PGA("DL1 Media Volume", + ABE_WIDGET(34), 0, 0, NULL, 0), + + /* AUDIO_UL_MIXER */ + SND_SOC_DAPM_MIXER("Voice Capture Mixer", + ABE_WIDGET(35), ABE_OPP_50, 0, audio_ul_mixer_controls, + ARRAY_SIZE(audio_ul_mixer_controls)), + + /* VX_REC_MIXER */ + SND_SOC_DAPM_MIXER("Capture Mixer", + ABE_WIDGET(36), ABE_OPP_50, 0, vx_rec_mixer_controls, + ARRAY_SIZE(vx_rec_mixer_controls)), + + /* SDT_MIXER */ + SND_SOC_DAPM_MIXER("Sidetone Mixer", + ABE_WIDGET(37), ABE_OPP_25, 0, sdt_mixer_controls, + ARRAY_SIZE(sdt_mixer_controls)), + + /* + * The Following three are virtual switches to select the output port + * after DL1 Gain - HAL V0.6x + */ + + /* Virtual PDM_DL1 Switch */ + SND_SOC_DAPM_MIXER("DL1 PDM", + ABE_WIDGET(38), ABE_OPP_25, 0, &pdm_dl1_switch_controls, 1), + + /* Virtual BT_VX_DL Switch */ + SND_SOC_DAPM_MIXER("DL1 BT_VX", + ABE_WIDGET(39), ABE_OPP_50, 0, &bt_vx_dl_switch_controls, 1), + + /* Virtual MM_EXT_DL Switch TODO: confrm OPP level here */ + SND_SOC_DAPM_MIXER("DL1 MM_EXT", + ABE_WIDGET(40), ABE_OPP_50, 0, &mm_ext_dl_switch_controls, 1), + + /* + * The Following three are virtual switches to select the input port + * before AMIC_UL enters ROUTE_UL - HAL V0.6x + */ + + /* Virtual MM_EXT_UL Switch */ + SND_SOC_DAPM_MIXER("AMIC_UL MM_EXT", + ABE_WIDGET(41), ABE_OPP_50, 0, &mm_ext_ul_switch_controls, 1), + + /* Virtual PDM_UL1 Switch */ + SND_SOC_DAPM_MIXER("AMIC_UL PDM", + ABE_WIDGET(42), ABE_OPP_50, 0, &pdm_ul1_switch_controls, 1), + + /* Virtual to join MM_EXT and PDM+UL1 switches */ + SND_SOC_DAPM_MIXER("AMIC_UL", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Virtuals to join our capture sources */ + SND_SOC_DAPM_MIXER("Sidetone Capture VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("Voice Capture VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("DL1 Capture VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("DL2 Capture VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Join our MM_DL and MM_DL_LP playback */ + SND_SOC_DAPM_MIXER("MM_DL VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Virtual MODEM and VX_UL mixer */ + SND_SOC_DAPM_MIXER("VX UL VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("VX DL VMixer", SND_SOC_NOPM, 0, 0, NULL, 0), + + /* Virtual Pins to force backends ON atm */ + SND_SOC_DAPM_OUTPUT("BE_OUT"), + SND_SOC_DAPM_INPUT("BE_IN"), +}; + +static const struct snd_soc_dapm_route intercon[] = { + + /* MUX_UL00 - ROUTE_UL - Chan 0 */ + {"MUX_UL00", "DMic0L", "DMIC0"}, + {"MUX_UL00", "DMic0R", "DMIC0"}, + {"MUX_UL00", "DMic1L", "DMIC1"}, + {"MUX_UL00", "DMic1R", "DMIC1"}, + {"MUX_UL00", "DMic2L", "DMIC2"}, + {"MUX_UL00", "DMic2R", "DMIC2"}, + {"MUX_UL00", "BT Left", "BT_VX_UL"}, + {"MUX_UL00", "BT Right", "BT_VX_UL"}, + {"MUX_UL00", "AMic0", "AMIC_UL"}, + {"MUX_UL00", "AMic1", "AMIC_UL"}, + {"MUX_UL00", "VX Left", "Capture Mixer"}, + {"MUX_UL00", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL00"}, + + /* MUX_UL01 - ROUTE_UL - Chan 1 */ + {"MUX_UL01", "DMic0L", "DMIC0"}, + {"MUX_UL01", "DMic0R", "DMIC0"}, + {"MUX_UL01", "DMic1L", "DMIC1"}, + {"MUX_UL01", "DMic1R", "DMIC1"}, + {"MUX_UL01", "DMic2L", "DMIC2"}, + {"MUX_UL01", "DMic2R", "DMIC2"}, + {"MUX_UL01", "BT Left", "BT_VX_UL"}, + {"MUX_UL01", "BT Right", "BT_VX_UL"}, + {"MUX_UL01", "AMic0", "AMIC_UL"}, + {"MUX_UL01", "AMic1", "AMIC_UL"}, + {"MUX_UL01", "VX Left", "Capture Mixer"}, + {"MUX_UL01", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL01"}, + + /* MUX_UL02 - ROUTE_UL - Chan 2 */ + {"MUX_UL02", "DMic0L", "DMIC0"}, + {"MUX_UL02", "DMic0R", "DMIC0"}, + {"MUX_UL02", "DMic1L", "DMIC1"}, + {"MUX_UL02", "DMic1R", "DMIC1"}, + {"MUX_UL02", "DMic2L", "DMIC2"}, + {"MUX_UL02", "DMic2R", "DMIC2"}, + {"MUX_UL02", "BT Left", "BT_VX_UL"}, + {"MUX_UL02", "BT Right", "BT_VX_UL"}, + {"MUX_UL02", "AMic0", "AMIC_UL"}, + {"MUX_UL02", "AMic1", "AMIC_UL"}, + {"MUX_UL02", "VX Left", "Capture Mixer"}, + {"MUX_UL02", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL02"}, + + /* MUX_UL03 - ROUTE_UL - Chan 3 */ + {"MUX_UL03", "DMic0L", "DMIC0"}, + {"MUX_UL03", "DMic0R", "DMIC0"}, + {"MUX_UL03", "DMic1L", "DMIC1"}, + {"MUX_UL03", "DMic1R", "DMIC1"}, + {"MUX_UL03", "DMic2L", "DMIC2"}, + {"MUX_UL03", "DMic2R", "DMIC2"}, + {"MUX_UL03", "BT Left", "BT_VX_UL"}, + {"MUX_UL03", "BT Right", "BT_VX_UL"}, + {"MUX_UL03", "AMic0", "AMIC_UL"}, + {"MUX_UL03", "AMic1", "AMIC_UL"}, + {"MUX_UL03", "VX Left", "Capture Mixer"}, + {"MUX_UL03", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL03"}, + + /* MUX_UL04 - ROUTE_UL - Chan 4 */ + {"MUX_UL04", "DMic0L", "DMIC0"}, + {"MUX_UL04", "DMic0R", "DMIC0"}, + {"MUX_UL04", "DMic1L", "DMIC1"}, + {"MUX_UL04", "DMic1R", "DMIC1"}, + {"MUX_UL04", "DMic2L", "DMIC2"}, + {"MUX_UL04", "DMic2R", "DMIC2"}, + {"MUX_UL04", "BT Left", "BT_VX_UL"}, + {"MUX_UL04", "BT Right", "BT_VX_UL"}, + {"MUX_UL04", "AMic0", "AMIC_UL"}, + {"MUX_UL04", "AMic1", "AMIC_UL"}, + {"MUX_UL04", "VX Left", "Capture Mixer"}, + {"MUX_UL04", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL04"}, + + /* MUX_UL05 - ROUTE_UL - Chan 5 */ + {"MUX_UL05", "DMic0L", "DMIC0"}, + {"MUX_UL05", "DMic0R", "DMIC0"}, + {"MUX_UL05", "DMic1L", "DMIC1"}, + {"MUX_UL05", "DMic1R", "DMIC1"}, + {"MUX_UL05", "DMic2L", "DMIC2"}, + {"MUX_UL05", "DMic2R", "DMIC2"}, + {"MUX_UL05", "BT Left", "BT_VX_UL"}, + {"MUX_UL05", "BT Right", "BT_VX_UL"}, + {"MUX_UL05", "AMic0", "AMIC_UL"}, + {"MUX_UL05", "AMic1", "AMIC_UL"}, + {"MUX_UL05", "VX Left", "Capture Mixer"}, + {"MUX_UL05", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL05"}, + + /* MUX_UL06 - ROUTE_UL - Chan 6 */ + {"MUX_UL06", "DMic0L", "DMIC0"}, + {"MUX_UL06", "DMic0R", "DMIC0"}, + {"MUX_UL06", "DMic1L", "DMIC1"}, + {"MUX_UL06", "DMic1R", "DMIC1"}, + {"MUX_UL06", "DMic2L", "DMIC2"}, + {"MUX_UL06", "DMic2R", "DMIC2"}, + {"MUX_UL06", "BT Left", "BT_VX_UL"}, + {"MUX_UL06", "BT Right", "BT_VX_UL"}, + {"MUX_UL06", "AMic0", "AMIC_UL"}, + {"MUX_UL06", "AMic1", "AMIC_UL"}, + {"MUX_UL06", "VX Left", "Capture Mixer"}, + {"MUX_UL06", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL06"}, + + /* MUX_UL07 - ROUTE_UL - Chan 7 */ + {"MUX_UL07", "DMic0L", "DMIC0"}, + {"MUX_UL07", "DMic0R", "DMIC0"}, + {"MUX_UL07", "DMic1L", "DMIC1"}, + {"MUX_UL07", "DMic1R", "DMIC1"}, + {"MUX_UL07", "DMic2L", "DMIC2"}, + {"MUX_UL07", "DMic2R", "DMIC2"}, + {"MUX_UL07", "BT Left", "BT_VX_UL"}, + {"MUX_UL07", "BT Right", "BT_VX_UL"}, + {"MUX_UL07", "AMic0", "AMIC_UL"}, + {"MUX_UL07", "AMic1", "AMIC_UL"}, + {"MUX_UL07", "VX Left", "Capture Mixer"}, + {"MUX_UL07", "VX Right", "Capture Mixer"}, + {"MM_UL1", NULL, "MUX_UL07"}, + + /* MUX_UL10 - ROUTE_UL - Chan 10 */ + {"MUX_UL10", "DMic0L", "DMIC0"}, + {"MUX_UL10", "DMic0R", "DMIC0"}, + {"MUX_UL10", "DMic1L", "DMIC1"}, + {"MUX_UL10", "DMic1R", "DMIC1"}, + {"MUX_UL10", "DMic2L", "DMIC2"}, + {"MUX_UL10", "DMic2R", "DMIC2"}, + {"MUX_UL10", "BT Left", "BT_VX_UL"}, + {"MUX_UL10", "BT Right", "BT_VX_UL"}, + {"MUX_UL10", "AMic0", "AMIC_UL"}, + {"MUX_UL10", "AMic1", "AMIC_UL"}, + {"MUX_UL10", "VX Left", "Capture Mixer"}, + {"MUX_UL10", "VX Right", "Capture Mixer"}, + {"MM_UL2", NULL, "MUX_UL10"}, + + /* MUX_UL11 - ROUTE_UL - Chan 11 */ + {"MUX_UL11", "DMic0L", "DMIC0"}, + {"MUX_UL11", "DMic0R", "DMIC0"}, + {"MUX_UL11", "DMic1L", "DMIC1"}, + {"MUX_UL11", "DMic1R", "DMIC1"}, + {"MUX_UL11", "DMic2L", "DMIC2"}, + {"MUX_UL11", "DMic2R", "DMIC2"}, + {"MUX_UL11", "BT Left", "BT_VX_UL"}, + {"MUX_UL11", "BT Right", "BT_VX_UL"}, + {"MUX_UL11", "AMic0", "AMIC_UL"}, + {"MUX_UL11", "AMic1", "AMIC_UL"}, + {"MUX_UL11", "VX Left", "Capture Mixer"}, + {"MUX_UL11", "VX Right", "Capture Mixer"}, + {"MM_UL2", NULL, "MUX_UL11"}, + + /* MUX_VX0 - ROUTE_UL - Chan 20 */ + {"MUX_VX0", "DMic0L", "DMIC0"}, + {"MUX_VX0", "DMic0R", "DMIC0"}, + {"MUX_VX0", "DMic1L", "DMIC1"}, + {"MUX_VX0", "DMic1R", "DMIC1"}, + {"MUX_VX0", "DMic2L", "DMIC2"}, + {"MUX_VX0", "DMic2R", "DMIC2"}, + {"MUX_VX0", "BT Left", "BT_VX_UL"}, + {"MUX_VX0", "BT Right", "BT_VX_UL"}, + {"MUX_VX0", "AMic0", "AMIC_UL"}, + {"MUX_VX0", "AMic1", "AMIC_UL"}, + {"MUX_VX0", "VX Left", "Capture Mixer"}, + {"MUX_VX0", "VX Right", "Capture Mixer"}, + + /* MUX_VX1 - ROUTE_UL - Chan 20 */ + {"MUX_VX1", "DMic0L", "DMIC0"}, + {"MUX_VX1", "DMic0R", "DMIC0"}, + {"MUX_VX1", "DMic1L", "DMIC1"}, + {"MUX_VX1", "DMic1R", "DMIC1"}, + {"MUX_VX1", "DMic2L", "DMIC2"}, + {"MUX_VX1", "DMic2R", "DMIC2"}, + {"MUX_VX1", "BT Left", "BT_VX_UL"}, + {"MUX_VX1", "BT Right", "BT_VX_UL"}, + {"MUX_VX1", "AMic0", "AMIC_UL"}, + {"MUX_VX1", "AMic1", "AMIC_UL"}, + {"MUX_VX1", "VX Left", "Capture Mixer"}, + {"MUX_VX1", "VX Right", "Capture Mixer"}, + + /* Capture Input Selection for AMIC_UL */ + {"AMIC_UL MM_EXT", "Switch", "MM_EXT_UL"}, + {"AMIC_UL PDM", "Switch", "PDM_UL1"}, + {"AMIC_UL", NULL, "AMIC_UL MM_EXT"}, + {"AMIC_UL", NULL, "AMIC_UL PDM"}, + + /* Headset (DL1) playback path */ + {"DL1 Mixer", "Tones", "TONES_DL"}, + {"DL1 Mixer", "Voice", "VX DL VMixer"}, + {"DL1 Mixer", "Capture", "DL1 Capture VMixer"}, + {"DL1 Capture VMixer", NULL, "MUX_UL10"}, + {"DL1 Capture VMixer", NULL, "MUX_UL11"}, + {"DL1 Mixer", "Multimedia", "MM_DL VMixer"}, + {"MM_DL VMixer", NULL, "MM_DL"}, + {"MM_DL VMixer", NULL, "MM_DL_LP"}, + + /* Sidetone Mixer */ + {"Sidetone Mixer", "Playback", "DL1 Mixer"}, + {"Sidetone Mixer", "Capture", "Sidetone Capture VMixer"}, + {"Sidetone Capture VMixer", NULL, "MUX_VX0"}, + {"Sidetone Capture VMixer", NULL, "MUX_VX1"}, + + /* Playback Output selection after DL1 Gain */ + {"DL1 BT_VX", "Switch", "Sidetone Mixer"}, + {"DL1 MM_EXT", "Switch", "Sidetone Mixer"}, + {"DL1 PDM", "Switch", "Sidetone Mixer"}, + {"PDM_DL1", NULL, "DL1 PDM"}, + {"BT_VX_DL", NULL, "DL1 BT_VX"}, + {"MM_EXT_DL", NULL, "DL1 MM_EXT"}, + + /* Handsfree (DL2) playback path */ + {"DL2 Mixer", "Tones", "TONES_DL"}, + {"DL2 Mixer", "Voice", "VX DL VMixer"}, + {"DL2 Mixer", "Capture", "DL2 Capture VMixer"}, + {"DL2 Capture VMixer", NULL, "MUX_UL10"}, + {"DL2 Capture VMixer", NULL, "MUX_UL11"}, + {"DL2 Mixer", "Multimedia", "MM_DL VMixer"}, + {"MM_DL VMixer", NULL, "MM_DL"}, + {"MM_DL VMixer", NULL, "MM_DL_LP"}, + {"PDM_DL2", NULL, "DL2 Mixer"}, + + /* VxREC Mixer */ + {"Capture Mixer", "Tones", "TONES_DL"}, + {"Capture Mixer", "Voice Playback", "VX DL VMixer"}, + {"Capture Mixer", "Voice Capture", "VX UL VMixer"}, + {"Capture Mixer", "Media Playback", "MM_DL VMixer"}, + {"MM_DL VMixer", NULL, "MM_DL"}, + {"MM_DL VMixer", NULL, "MM_DL_LP"}, + + /* Audio UL mixer */ + {"Voice Capture Mixer", "Tones Playback", "TONES_DL"}, + {"Voice Capture Mixer", "Media Playback", "MM_DL VMixer"}, + {"MM_DL VMixer", NULL, "MM_DL"}, + {"MM_DL VMixer", NULL, "MM_DL_LP"}, + {"Voice Capture Mixer", "Capture", "Voice Capture VMixer"}, + {"Voice Capture VMixer", NULL, "MUX_VX0"}, + {"Voice Capture VMixer", NULL, "MUX_VX1"}, + + /* BT */ + {"VX UL VMixer", NULL, "Voice Capture Mixer"}, + + /* Vibra */ + {"PDM_VIB", NULL, "VIB_DL"}, + + /* VX and MODEM */ + {"VX_UL", NULL, "VX UL VMixer"}, + {"MODEM_UL", NULL, "VX UL VMixer"}, + {"VX DL VMixer", NULL, "VX_DL"}, + {"VX DL VMixer", NULL, "MODEM_DL"}, + + /* Backend Enablement - TODO: maybe re-work*/ + {"BE_OUT", NULL, "PDM_DL1"}, + {"BE_OUT", NULL, "PDM_DL2"}, + {"BE_OUT", NULL, "PDM_VIB"}, + {"BE_OUT", NULL, "MM_EXT_DL"}, + {"BE_OUT", NULL, "BT_VX_DL"}, + {"PDM_UL1", NULL, "BE_IN"}, + {"BT_VX_UL", NULL, "BE_IN"}, + {"MM_EXT_UL", NULL, "BE_IN"}, + {"DMIC0", NULL, "BE_IN"}, + {"DMIC1", NULL, "BE_IN"}, + {"DMIC2", NULL, "BE_IN"}, +}; + +static int abe_add_widgets(struct snd_soc_platform *platform) +{ + snd_soc_add_platform_controls(platform, abe_controls, + ARRAY_SIZE(abe_controls)); + + snd_soc_dapm_new_controls(&platform->dapm, abe_dapm_widgets, + ARRAY_SIZE(abe_dapm_widgets)); + + snd_soc_dapm_add_routes(&platform->dapm, intercon, ARRAY_SIZE(intercon)); + + snd_soc_dapm_new_widgets(&platform->dapm); + + return 0; +} + +static int aess_set_opp_mode(void) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + int i, opp = 0; + + pm_runtime_get_sync(&pdev->dev); + + mutex_lock(&abe->opp_mutex); + + /* now calculate OPP level based upon DAPM widget status */ + for (i = ABE_WIDGET_START; i < ABE_WIDGET_END; i++) + opp |= abe->dapm[i]; + + opp = (1 << (fls(opp) - 1)) * 25; + + if (abe->opp > opp) { + /* Decrease OPP mode - no need of OPP100% */ + switch (opp) { + case 25: + abe_set_opp_processing(ABE_OPP25); + udelay(250); + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 98000000); + break; + case 50: + default: + abe_set_opp_processing(ABE_OPP50); + udelay(250); + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 98000000); + break; + } + } else if (abe->opp < opp) { + /* Increase OPP mode */ + switch (opp) { + case 25: + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 98000000); + abe_set_opp_processing(ABE_OPP25); + break; + case 50: + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 98000000); + abe_set_opp_processing(ABE_OPP50); + break; + case 100: + default: + /* FIXME: Dependency on PM framework */ + //omap_device_set_rate(&pdev->dev, &pdev->dev, 196000000); + abe_set_opp_processing(ABE_OPP100); + break; + } + } + abe->opp = opp; + + mutex_unlock(&abe->opp_mutex); + + pm_runtime_put_sync(&pdev->dev); + + return 0; +} + +static int abe_probe(struct snd_soc_platform *platform) +{ + abe_init_engine(platform); + abe_add_widgets(platform); + abe->platform = platform; + return 0; +} + +static int abe_remove(struct snd_soc_platform *platform) +{ + return 0; +} + +static int aess_save_context(struct abe_data *abe) +{ + struct platform_device *pdev = abe->pdev; + struct omap4_abe_dsp_pdata *pdata = pdev->dev.platform_data; + + /* TODO: Find a better way to save/retore gains after OFF mode */ + abe_mute_gain(MIXSDT, MIX_SDT_INPUT_UP_MIXER); + abe_mute_gain(MIXSDT, MIX_SDT_INPUT_DL1_MIXER); + abe_mute_gain(MIXAUDUL, MIX_AUDUL_INPUT_MM_DL); + abe_mute_gain(MIXAUDUL, MIX_AUDUL_INPUT_TONES); + abe_mute_gain(MIXAUDUL, MIX_AUDUL_INPUT_UPLINK); + abe_mute_gain(MIXAUDUL, MIX_AUDUL_INPUT_VX_DL); + abe_mute_gain(MIXVXREC, MIX_VXREC_INPUT_TONES); + abe_mute_gain(MIXVXREC, MIX_VXREC_INPUT_VX_DL); + abe_mute_gain(MIXVXREC, MIX_VXREC_INPUT_MM_DL); + abe_mute_gain(MIXVXREC, MIX_VXREC_INPUT_VX_UL); + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_MM_DL); + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_MM_UL2); + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_VX_DL); + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_TONES); + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_TONES); + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_VX_DL); + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_MM_DL); + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_MM_UL2); + abe_mute_gain(MIXECHO, MIX_ECHO_DL1); + abe_mute_gain(MIXECHO, MIX_ECHO_DL2); + abe_mute_gain(GAINS_DMIC1, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC1, GAIN_RIGHT_OFFSET); + abe_mute_gain(GAINS_DMIC2, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC2, GAIN_RIGHT_OFFSET); + abe_mute_gain(GAINS_DMIC3, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC3, GAIN_RIGHT_OFFSET); + abe_mute_gain(GAINS_AMIC, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_AMIC, GAIN_RIGHT_OFFSET); + + if (pdata->get_context_loss_count) + abe->loss_count = pdata->get_context_loss_count(&pdev->dev); + + return 0; +} + +static int aess_restore_context(struct abe_data *abe) +{ + struct platform_device *pdev = abe->pdev; + struct omap4_abe_dsp_pdata *pdata = pdev->dev.platform_data; + int loss_count = 0; +/* FIXME: Dependency on PM framework */ +// omap_device_set_rate(&pdev->dev, &pdev->dev, 98000000); + + if (pdata->get_context_loss_count) + loss_count = pdata->get_context_loss_count(&pdev->dev); + + if (loss_count != abe->loss_count) + abe_reload_fw(); + + /* TODO: Find a better way to save/retore gains after dor OFF mode */ + abe_unmute_gain(MIXSDT, MIX_SDT_INPUT_UP_MIXER); + abe_unmute_gain(MIXSDT, MIX_SDT_INPUT_DL1_MIXER); + abe_unmute_gain(MIXAUDUL, MIX_AUDUL_INPUT_MM_DL); + abe_unmute_gain(MIXAUDUL, MIX_AUDUL_INPUT_TONES); + abe_unmute_gain(MIXAUDUL, MIX_AUDUL_INPUT_UPLINK); + abe_unmute_gain(MIXAUDUL, MIX_AUDUL_INPUT_VX_DL); + abe_unmute_gain(MIXVXREC, MIX_VXREC_INPUT_TONES); + abe_unmute_gain(MIXVXREC, MIX_VXREC_INPUT_VX_DL); + abe_unmute_gain(MIXVXREC, MIX_VXREC_INPUT_MM_DL); + abe_unmute_gain(MIXVXREC, MIX_VXREC_INPUT_VX_UL); + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_MM_DL); + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_MM_UL2); + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_VX_DL); + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_TONES); + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_TONES); + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_VX_DL); + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_MM_DL); + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_MM_UL2); + abe_unmute_gain(MIXECHO, MIX_ECHO_DL1); + abe_unmute_gain(MIXECHO, MIX_ECHO_DL2); + abe_unmute_gain(GAINS_DMIC1, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC1, GAIN_RIGHT_OFFSET); + abe_unmute_gain(GAINS_DMIC2, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC2, GAIN_RIGHT_OFFSET); + abe_unmute_gain(GAINS_DMIC3, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC3, GAIN_RIGHT_OFFSET); + abe_unmute_gain(GAINS_AMIC, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_AMIC, GAIN_RIGHT_OFFSET); + + abe_dsp_set_equalizer(EQ1, abe->dl1_equ_profile); + abe_dsp_set_equalizer(EQ2L, abe->dl20_equ_profile); + abe_dsp_set_equalizer(EQ2R, abe->dl21_equ_profile); + abe_dsp_set_equalizer(EQAMIC, abe->amic_equ_profile); + abe_dsp_set_equalizer(EQDMIC, abe->dmic_equ_profile); + abe_dsp_set_equalizer(EQSDT, abe->sdt_equ_profile); + + abe_set_router_configuration(UPROUTE, 0, (u32 *)abe->router); + + return 0; +} + +static int aess_open(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *dai = rtd->cpu_dai; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + int ret = 0; + + mutex_lock(&abe->mutex); + + abe->fe_id = dai->id; + dev_dbg(&rtd->dev, "%s ID %d\n", __func__, dai->id); + + pm_runtime_get_sync(&pdev->dev); + + if (!abe->active++) { + abe->opp = 0; + aess_restore_context(abe); + aess_set_opp_mode(); + abe_wakeup(); + } + + switch (dai->id) { + case ABE_FRONTEND_DAI_MODEM: + break; + case ABE_FRONTEND_DAI_LP_MEDIA: + snd_soc_set_runtime_hwparams(substream, &omap_abe_hardware); + ret = snd_pcm_hw_constraint_step(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1024); + break; + default: + break; + } + + mutex_unlock(&abe->mutex); + return ret; +} + +static int abe_ping_pong_init(struct snd_pcm_hw_params *params, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + abe_data_format_t format; + size_t period_size; + u32 dst; + + /*Storing substream pointer for irq*/ + abe->psubs = substream; + + format.f = params_rate(params); + format.samp_format = STEREO_16_16; + + if (format.f == 44100) + abe_write_event_generator(EVENT_44100); + + period_size = params_period_bytes(params); + + /* Adding ping pong buffer subroutine */ + abe_plug_subroutine(&abe_irq_pingpong_player_id, + (abe_subroutine2) abe_irq_pingpong_subroutine, + SUB_0_PARAM, (u32 *)0); + + /* Connect a Ping-Pong cache-flush protocol to MM_DL port */ + abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, + abe_irq_pingpong_player_id, + period_size, &dst, + PING_PONG_WITH_MCU_IRQ); + + /* Memory mapping for hw params */ + runtime->dma_area = abe->io_base + ABE_DMEM_BASE_OFFSET_MPU + dst; + runtime->dma_addr = 0; + runtime->dma_bytes = period_size * 2; + + /* Need to set the first buffer in order to get interrupt */ + abe_set_ping_pong_buffer(MM_DL_PORT, period_size); + abe->first_irq = 1; + + return 0; +} + +static int aess_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *dai = rtd->cpu_dai; + int ret = 0; + + dev_dbg(&rtd->dev, "%s ID %d\n", __func__, dai->id); + + switch (dai->id) { + case ABE_FRONTEND_DAI_MODEM: + break; + case ABE_FRONTEND_DAI_LP_MEDIA: + ret = abe_ping_pong_init(params, substream); + if (ret < 0) + return ret; + break; + default: + break; + } + + return 0; +} + +static int aess_prepare(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + + mutex_lock(&abe->mutex); + + dev_dbg(&rtd->dev, "%s ID %d\n", __func__, rtd->cpu_dai->id); + + aess_set_opp_mode(); + + mutex_unlock(&abe->mutex); + return 0; +} + +static int aess_close(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *dai = rtd->cpu_dai; + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + mutex_lock(&abe->mutex); + + abe->fe_id = dai->id; + dev_dbg(&rtd->dev, "%s ID %d\n", __func__, dai->id); + + if (!--abe->active) { + abe_disable_irq(); + aess_save_context(abe); + abe_dsp_shutdown(); + } + pm_runtime_put_sync(&pdev->dev); + + mutex_unlock(&abe->mutex); + return 0; +} + +static int aess_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma) +{ + int offset, size, err; + + /* TODO: we may need to check for underrun. */ + vma->vm_flags |= VM_IO | VM_RESERVED; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + size = vma->vm_end - vma->vm_start; + offset = vma->vm_pgoff << PAGE_SHIFT; + + err = io_remap_pfn_range(vma, vma->vm_start, + (ABE_DMEM_BASE_ADDRESS_MPU + + ABE_DMEM_BASE_OFFSET_PING_PONG + offset) >> PAGE_SHIFT, + size, vma->vm_page_prot); + + if (err) + return -EAGAIN; + + return 0; +} + +static snd_pcm_uframes_t aess_pointer(struct snd_pcm_substream *substream) +{ + snd_pcm_uframes_t offset; + u32 pingpong; + + abe_read_offset_from_ping_buffer(MM_DL_PORT, &pingpong); + offset = (snd_pcm_uframes_t)pingpong; +/* + if (offset >= runtime->buffer_size) + offset = 0; +*/ + return offset; +} + + +static struct snd_pcm_ops omap_aess_pcm_ops = { + .open = aess_open, + .hw_params = aess_hw_params, + .prepare = aess_prepare, + .close = aess_close, + .pointer = aess_pointer, + .mmap = aess_mmap, +}; + +static int aess_stream_event(struct snd_soc_dapm_context *dapm) +{ + /* TODO: do not use abe global structure to assign pdev */ + struct platform_device *pdev = abe->pdev; + + if (abe->active) { + pm_runtime_get_sync(&pdev->dev); + aess_set_opp_mode(); + pm_runtime_put_sync(&pdev->dev); + } + + return 0; +} + +static struct snd_soc_platform_driver omap_aess_platform = { + .ops = &omap_aess_pcm_ops, + .probe = abe_probe, + .remove = abe_remove, + .read = abe_dsp_read, + .write = abe_dsp_write, + .stream_event = aess_stream_event, +}; + +/* FIXME: Dependency on PM framework */ +#if 0// +defined(CONFIG_PM) +static int omap_pm_abe_get_dev_context_loss_count(struct device *dev) +{ + + int ret; + + ret = prm_read_mod_reg(abe_pwrdm->prcm_offs, + abe_pwrdm->context_offset); + + if ((ret & 0x0001) == 0x0001) { + prm_write_mod_reg(0x0001, abe_pwrdm->prcm_offs, + abe_pwrdm->context_offset); + ret &= ~0x0001; + } + + if ((ret & 0x0100) == 0x0100) + prm_write_mod_reg(0x0100, abe_pwrdm->prcm_offs, + abe_pwrdm->context_offset); + + return ret; +} + +#else +#define omap_pm_abe_get_dev_context_loss_count NULL +#endif + +static int __devinit abe_engine_probe(struct platform_device *pdev) +{ + struct omap4_abe_dsp_pdata *pdata = pdev->dev.platform_data; + struct resource *res; + int ret = -EINVAL, i; + + abe = kzalloc(sizeof(struct abe_data), GFP_KERNEL); + if (abe == NULL) + return -ENOMEM; + dev_set_drvdata(&pdev->dev, abe); + + /* ZERO_labelID should really be 0 */ + for (i = 0; i < ABE_ROUTES_UL + 2; i++) + abe->router[i] = ZERO_labelID; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no resource\n"); + goto err; + } + + abe->io_base = ioremap(res->start, resource_size(res)); + if (!abe->io_base) { + ret = -ENOMEM; + goto err; + } + + abe->irq = platform_get_irq(pdev, 0); + if (abe->irq < 0) { + ret = abe->irq; + goto err_irq; + } + +#if defined(CONFIG_PM) + abe_pwrdm = pwrdm_lookup("abe_pwrdm"); + if (!abe_pwrdm) + return -ENODEV; + + pdata->get_context_loss_count = omap_pm_abe_get_dev_context_loss_count; +#endif + + pm_runtime_enable(&pdev->dev); + + abe->abe_pdata = pdata; + abe->pdev = pdev; + + mutex_init(&abe->mutex); + mutex_init(&abe->opp_mutex); + + ret = snd_soc_register_platform(&pdev->dev, + &omap_aess_platform); + if (ret == 0) + return 0; + +err_irq: + iounmap(abe->io_base); +err: + kfree(abe); + return ret; +} + +static int __devexit abe_engine_remove(struct platform_device *pdev) +{ + struct abe_data *priv = dev_get_drvdata(&pdev->dev); + + snd_soc_unregister_platform(&pdev->dev); + iounmap(priv->io_base); + kfree(priv); + return 0; +} + +static struct platform_driver omap_aess_driver = { + .driver = { + .name = "omap-aess-audio", + .owner = THIS_MODULE, + }, + .probe = abe_engine_probe, + .remove = __devexit_p(abe_engine_remove), +}; + +static int __init abe_engine_init(void) +{ + return platform_driver_register(&omap_aess_driver); +} +module_init(abe_engine_init); + +static void __exit abe_engine_exit(void) +{ + platform_driver_unregister(&omap_aess_driver); +} +module_exit(abe_engine_exit); + +MODULE_DESCRIPTION("ASoC OMAP4 ABE"); +MODULE_AUTHOR("Liam Girdwood <lrg@slimlogic.co.uk>"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/omap-abe-dsp.h b/sound/soc/omap/omap-abe-dsp.h new file mode 100644 index 00000000000..212ef3bf30f --- /dev/null +++ b/sound/soc/omap/omap-abe-dsp.h @@ -0,0 +1,34 @@ +/* + * omap-abe-dsp.h + * + * Copyright (C) 2010 Texas Instruments + * + * Contact: Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __OMAP_ABE_DSP_H__ +#define __OMAP_ABE_DSP_H__ + +/* Ping pong buffer DMEM offset */ +#define ABE_DMEM_BASE_OFFSET_PING_PONG 0x4000 + +void abe_dsp_mcpdm_shutdown(void); +void abe_dsp_pm_get(void); +void abe_dsp_pm_put(void); + +#endif /* End of __OMAP_ABE_DSP_H__ */ diff --git a/sound/soc/omap/omap-abe.c b/sound/soc/omap/omap-abe.c new file mode 100644 index 00000000000..ded9194efd8 --- /dev/null +++ b/sound/soc/omap/omap-abe.c @@ -0,0 +1,1669 @@ +/* + * omap-abe.c -- OMAP ALSA SoC DAI driver using Audio Backend + * + * Copyright (C) 2010 Texas Instruments + * + * Contact: Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#undef DEBUG + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include <linux/delay.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/control.h> + +#include <plat/dma-44xx.h> +#include <plat/dma.h> +#include "omap-mcpdm.h" +#include "omap-pcm.h" +#include "omap-abe.h" +#include "omap-abe-dsp.h" +#include "abe/abe_main.h" + +#define OMAP_ABE_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +/* + * This is the AESS frontend driver. i.e. the part that Tx and Rx PCM + * data via the OMAP sDMA and ALSA userspace PCMs. + * + * TODO: + * + * 1) Get DAI params from HAL and pass onto DAI drivers ? + * (are params static ??, i.e. can I just use a table) + */ + +#define NUM_ABE_FRONTENDS 7 +#define NUM_ABE_BACKENDS 11 + +/* logical -> physical DAI status */ +enum dai_status { + DAI_STOPPED = 0, + DAI_STARTED, +}; + +struct omap_abe_data { + int be_active[NUM_ABE_BACKENDS][2]; + + struct clk *clk; + struct workqueue_struct *workqueue; + + /* hwmod platform device */ + struct platform_device *pdev; + + /* MODEM FE*/ + struct snd_pcm_substream *modem_substream[2]; + struct snd_soc_dai *modem_dai; + + /* reference counting and port status - HAL should really do this */ + enum dai_status dmic_status[3]; + enum dai_status pdm_dl_status[3]; + enum dai_status pdm_ul_status; + +}; + +static struct omap_abe_data abe_data; +static void capture_trigger(struct snd_pcm_substream *substream, int cmd); +static void playback_trigger(struct snd_pcm_substream *substream, int cmd); + +/* frontend mutex */ +static DEFINE_MUTEX(fe_mutex); + +/* + * Stream DMA parameters + */ +static struct omap_pcm_dma_data omap_abe_dai_dma_params[7][2] = { +{ + { + .name = "Media Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_0, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, + { + .name = "Media Capture1", + .dma_req = OMAP44XX_DMA_ABE_REQ_3, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, +}, +{ + {}, + { + .name = "Media Capture2", + .dma_req = OMAP44XX_DMA_ABE_REQ_4, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, +}, +{ + { + .name = "Voice Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_1, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, + { + .name = "Voice Capture", + .dma_req = OMAP44XX_DMA_ABE_REQ_2, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, +}, +{ + { + .name = "Tones Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_5, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + },{}, +}, +{ + { + .name = "Vibra Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_6, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + },{}, +}, +{ + { + .name = "MODEM Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_1, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, + { + .name = "MODEM Capture", + .dma_req = OMAP44XX_DMA_ABE_REQ_2, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + }, +}, +{ + { + .name = "Low Power Playback", + .dma_req = OMAP44XX_DMA_ABE_REQ_0, + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + },{}, +},}; + +/* + * Caller holds lock for be_active calls. + */ +static inline int be_get_active(struct snd_soc_pcm_runtime *be_rtd, int stream) +{ + return abe_data.be_active[be_rtd->dai_link->be_id][stream]; +} + +static inline void be_inc_active(struct snd_soc_pcm_runtime *be_rtd, int stream) +{ + abe_data.be_active[be_rtd->dai_link->be_id][stream]++; +} + +static inline void be_dec_active(struct snd_soc_pcm_runtime *be_rtd, int stream) +{ + abe_data.be_active[be_rtd->dai_link->be_id][stream]--; +} + +/* iff the BE has one user can we start and stop the port */ +static inline int be_is_pending(struct snd_soc_pcm_runtime *be_rtd, int stream) +{ + return abe_data.be_active[be_rtd->dai_link->be_id][stream] == 1 ? 1 : 0; +} + +/* + * consolidate our 3 PDM and DMICs. + */ +static inline int pdm_ready(struct omap_abe_data *abe) +{ + int i; + + /* check the 3 DL DAIs */ + for (i = 0; i < 3; i++) { + if (abe->pdm_dl_status[i] == DAI_STARTED) + return 0; + } + + return 1; +} + +static inline int dmic_ready(struct omap_abe_data *abe) +{ + int i; + + /* check the 3 DMIC DAIs */ + for (i = 0; i < 3; i++) { + if (abe->dmic_status[i] == DAI_STARTED) + return 0; + } + + return 1; +} + +static int modem_get_dai(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *modem_rtd; + + abe_data.modem_substream[substream->stream] = + snd_soc_get_dai_substream(rtd->card, + OMAP_ABE_BE_MM_EXT1, substream->stream); + if (abe_data.modem_substream[substream->stream] == NULL) + return -ENODEV; + + modem_rtd = abe_data.modem_substream[substream->stream]->private_data; + abe_data.modem_dai = modem_rtd->cpu_dai; + return 0; +} + +/* Frontend PCM Operations */ + +static int abe_fe_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret = 0; + + /* TODO: complete HW pcm for backends */ +#if 0 + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + priv->sysclk_constraints); +#endif + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + + ret = modem_get_dai(substream); + if (ret < 0) { + dev_err(dai->dev, "failed to get MODEM DAI\n"); + return ret; + } + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d\n", + __func__, substream->stream); + + ret = snd_soc_dai_startup(abe_data.modem_substream[substream->stream], + abe_data.modem_dai); + if (ret < 0) { + dev_err(abe_data.modem_dai->dev, "failed to open DAI %d\n", ret); + return ret; + } + } + + return ret; +} + +static int abe_fe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + abe_data_format_t format; + abe_dma_t dma_sink; + abe_dma_t dma_params; + int ret; + + switch (params_channels(params)) { + case 1: + if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE) + format.samp_format = MONO_RSHIFTED_16; + else + format.samp_format = MONO_MSB; + break; + case 2: + if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE) + format.samp_format = STEREO_16_16; + else + format.samp_format = STEREO_MSB; + break; + case 3: + format.samp_format = THREE_MSB; + break; + case 4: + format.samp_format = FOUR_MSB; + break; + case 5: + format.samp_format = FIVE_MSB; + break; + case 6 : + format.samp_format = SIX_MSB; + break; + case 7 : + format.samp_format = SEVEN_MSB; + break; + case 8: + format.samp_format = EIGHT_MSB; + break; + default: + dev_err(dai->dev, "%d channels not supported", + params_channels(params)); + return -EINVAL; + } + + format.f = params_rate(params); + + switch (dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, + &dma_sink); + abe_read_port_address(MM_DL_PORT, &dma_params); + } else { + abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, + &dma_sink); + abe_read_port_address(MM_UL_PORT, &dma_params); + } + break; + case ABE_FRONTEND_DAI_LP_MEDIA: + return 0; + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + return -EINVAL; + else { + abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, + &dma_sink); + abe_read_port_address(MM_UL2_PORT, &dma_params); + } + break; + case ABE_FRONTEND_DAI_VOICE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, + &dma_sink); + abe_read_port_address(VX_DL_PORT, &dma_params); + } else { + abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, + &dma_sink); + abe_read_port_address(VX_UL_PORT, &dma_params); + } + break; + case ABE_FRONTEND_DAI_TONES: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, + &dma_sink); + abe_read_port_address(TONES_DL_PORT, &dma_params); + } else + return -EINVAL; + break; + case ABE_FRONTEND_DAI_VIBRA: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, + &dma_sink); + abe_read_port_address(VIB_DL_PORT, &dma_params); + } else + return -EINVAL; + break; + case ABE_FRONTEND_DAI_MODEM: + /* MODEM is special case where data IO is performed by McBSP2 + * directly onto VX_DL and VX_UL (instead of SDMA). + */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* Vx_DL connection to McBSP 2 ports */ + format.samp_format = STEREO_RSHIFTED_16; + abe_connect_serial_port(VX_DL_PORT, &format, MCBSP2_RX); + abe_read_port_address(VX_DL_PORT, &dma_params); + } else { + /* Vx_UL connection to McBSP 2 ports */ + format.samp_format = STEREO_RSHIFTED_16; + abe_connect_serial_port(VX_UL_PORT, &format, MCBSP2_TX); + abe_read_port_address(VX_UL_PORT, &dma_params); + } + break; + } + + /* configure frontend SDMA data */ + omap_abe_dai_dma_params[dai->id][substream->stream].port_addr = + (unsigned long)dma_params.data; + omap_abe_dai_dma_params[dai->id][substream->stream].packet_size = + dma_params.iter; + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + /* call hw_params on McBSP with correct DMA data */ + snd_soc_dai_set_dma_data(abe_data.modem_dai, substream, + &omap_abe_dai_dma_params[dai->id][substream->stream]); + + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d\n", + __func__, substream->stream); + + ret = snd_soc_dai_hw_params(abe_data.modem_substream[substream->stream], + params, abe_data.modem_dai); + if (ret < 0) + dev_err(abe_data.modem_dai->dev, "MODEM hw_params failed\n"); + return ret; + } + + snd_soc_dai_set_dma_data(dai, substream, + &omap_abe_dai_dma_params[dai->id][substream->stream]); + + return 0; +} + +static int abe_fe_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret = 0; + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + ret = snd_soc_dai_prepare(abe_data.modem_substream[substream->stream], + abe_data.modem_dai); + + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d\n", + __func__, substream->stream); + + if (ret < 0) { + dev_err(abe_data.modem_dai->dev, "MODEM prepare failed\n"); + return ret; + } + } + return ret; +} + +static int abe_fe_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + int ret = 0; + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d cmd %d\n", + __func__, substream->stream, cmd); + + ret = snd_soc_dai_trigger(abe_data.modem_substream[substream->stream], + cmd, abe_data.modem_dai); + if (ret < 0) { + dev_err(abe_data.modem_dai->dev, "MODEM trigger failed\n"); + return ret; + } + } + return ret; +} + +static int abe_fe_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int ret = 0; + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d\n", + __func__, substream->stream); + + ret = snd_soc_dai_hw_free(abe_data.modem_substream[substream->stream], + abe_data.modem_dai); + if (ret < 0) { + dev_err(abe_data.modem_dai->dev, "MODEM hw_free failed\n"); + return ret; + } + } + return ret; +} + +static void abe_fe_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + + if (dai->id == ABE_FRONTEND_DAI_MODEM) { + dev_dbg(abe_data.modem_dai->dev, "%s: MODEM stream %d\n", + __func__, substream->stream); + + snd_soc_dai_shutdown(abe_data.modem_substream[substream->stream], + abe_data.modem_dai); + } + //TODO: Do we need to do reset this stuff i.e. :- + //abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, + // &dma_sink); +} + +static void abe_be_dapm(struct snd_soc_pcm_runtime *rtd, + int id, int stream, int cmd) +{ + dev_dbg(&rtd->dev, "%s: id %d stream %d cmd %d\n", + __func__, id, stream, cmd); + + switch (id) { + case ABE_FRONTEND_DAI_MEDIA: + case ABE_FRONTEND_DAI_LP_MEDIA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, stream, "Multimedia Playback",cmd); + else + snd_soc_dapm_stream_event(rtd, stream, "Multimedia Capture1",cmd); + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + snd_soc_dapm_stream_event(rtd, stream, "Multimedia Capture2",cmd); + break; + case ABE_FRONTEND_DAI_VOICE: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, stream, "Voice Playback",cmd); + else + snd_soc_dapm_stream_event(rtd, stream, "Voice Capture",cmd); + break; + case ABE_FRONTEND_DAI_TONES: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, stream, "Tones Playback",cmd); + break; + case ABE_FRONTEND_DAI_VIBRA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, stream, "Vibra Playback",cmd); + break; + case ABE_FRONTEND_DAI_MODEM: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, stream, "MODEM Playback",cmd); + else + snd_soc_dapm_stream_event(rtd, stream, "MODEM Capture",cmd); + break; + } +} + +/* Frontend --> Backend ALSA PCM OPS */ + +static int omap_abe_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int stream = substream->stream, ret = 0, i; + + dev_dbg(dai->dev, "%s: frontend %s %d\n", __func__, + rtd->dai_link->name, dai->id); + + /* ABE needs a step of 24 * 4 data bytes */ + ret = snd_pcm_hw_constraint_step(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 96); + if (ret < 0) + return ret; + + mutex_lock(&fe_mutex); + + /* only startup BE DAIs that are either sinks or sources to this FE DAI */ + for (i = 0; i < rtd->num_be[stream]; i++) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + /* update BE ref counts */ + be_inc_active(rtd->be_rtd[i][stream], stream); + + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + ret = snd_soc_pcm_open(be_substream); + if (ret < 0) + goto unwind; + dev_dbg(&rtd->dev, "%s: open %s:%d at %d act %d\n", __func__, + rtd->be_rtd[i][stream]->dai_link->name, + rtd->be_rtd[i][stream]->dai_link->be_id, i, + abe_data.be_active[rtd->be_rtd[i][stream]->dai_link->be_id][stream]); + } + } + + /* start the ABE frontend */ + ret = abe_fe_startup(substream, dai); + if (ret < 0) { + dev_err(dai->dev,"%s: failed to start FE %d\n", __func__, ret); + goto unwind; + } + + dev_dbg(dai->dev,"%s: frontend finished %s %d\n", __func__, + rtd->dai_link->name, dai->id); + mutex_unlock(&fe_mutex); + return 0; + +unwind: + /* disable any enabled and non active backends */ + for (--i; i >= 0; i--) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + snd_soc_pcm_close(be_substream); + + dev_dbg(&rtd->dev, "%s: open-err-close %s:%d at %d act %d\n", __func__, + rtd->be_rtd[i][stream]->dai_link->name, + rtd->be_rtd[i][stream]->dai_link->be_id, i, + abe_data.be_active[rtd->be_rtd[i][stream]->dai_link->be_id][stream]); + } + + be_dec_active(rtd->be_rtd[i][stream], stream); + } + + mutex_unlock(&fe_mutex); + return ret; +} + +static void omap_abe_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int stream = substream->stream, i; + + dev_dbg(dai->dev,"%s: frontend %s \n", __func__, rtd->dai_link->name); + /* only shutdown backends that are either sinks or sources to this frontend DAI */ + + mutex_lock(&fe_mutex); + + for (i = 0; i < rtd->num_be[stream]; i++) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + /* close backend stream if inactive */ + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + snd_soc_pcm_close(be_substream); + + dev_dbg(&rtd->dev,"%s: close %s:%d at %d act %d\n", __func__, + rtd->be_rtd[i][stream]->dai_link->name, + rtd->be_rtd[i][stream]->dai_link->be_id, i, + abe_data.be_active[rtd->be_rtd[i][stream]->dai_link->be_id][stream]); + } + + be_dec_active(rtd->be_rtd[i][stream], stream); + } + + /* now shutdown the frontend */ + abe_fe_shutdown(substream, dai); + + abe_be_dapm(rtd, dai->id, stream, SND_SOC_DAPM_STREAM_STOP); + dev_dbg(dai->dev,"%s: frontend %s completed !\n", __func__, rtd->dai_link->name); + mutex_unlock(&fe_mutex); +} + +static int omap_abe_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int stream = substream->stream, i, ret = 0; + struct snd_pcm_hw_params *params_fe; + + params_fe = kzalloc(sizeof(struct snd_pcm_hw_params), GFP_KERNEL); + dev_dbg(dai->dev,"%s: frontend %s \n", __func__, rtd->dai_link->name); + + memcpy(params_fe, params, sizeof(struct snd_pcm_hw_params)); + + mutex_lock(&fe_mutex); + + for (i = 0; i < rtd->num_be[stream]; i++) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + if (be_rtd->dai_link->be_hw_params_fixup) + ret = be_rtd->dai_link->be_hw_params_fixup(be_rtd, params); + if (ret < 0) { + dev_err(&rtd->dev, "%s: backend hw_params fixup failed %d\n", + __func__, ret); + goto out; + } + + ret = snd_soc_pcm_hw_params(be_substream, params); + if (ret < 0) { + dev_err(&rtd->dev, "%s: backend hw_params failed %d\n", + __func__, ret); + goto out; + } + } + } + + /* call hw_params on the frontend */ + memcpy(params, params_fe, sizeof(struct snd_pcm_hw_params)); + ret = abe_fe_hw_params(substream, params, dai); + if (ret < 0) + dev_err(dai->dev,"%s: frontend hw_params failed\n", __func__); + +out: + mutex_unlock(&fe_mutex); + kfree(params_fe); + return ret; +} + +static int omap_abe_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int ret; + + dev_dbg(dai->dev,"%s: frontend %s \n", __func__, rtd->dai_link->name); + + /* call prepare on the frontend. TODO: do we handle MODEM as sequence */ + ret = abe_fe_trigger(substream, cmd, dai); + if (ret < 0) { + dev_err(dai->dev,"%s: frontend trigger failed\n", __func__); + return ret; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + playback_trigger(substream, cmd); + else + capture_trigger(substream, cmd); + + return 0; +} + +static int omap_abe_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int stream = substream->stream, ret = 0, i; + + dev_dbg(dai->dev,"%s: frontend %s \n", __func__, rtd->dai_link->name); + /* only prepare backends that are either sinks or sources to + * this frontend DAI */ + + mutex_lock(&fe_mutex); + + for (i = 0; i < rtd->num_be[stream]; i++) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + /* prepare backend stream */ + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + snd_soc_pcm_prepare(be_substream); + } + } + + /* call prepare on the frontend */ + ret = abe_fe_prepare(substream, dai); + if (ret < 0) + dev_err(dai->dev,"%s: frontend prepare failed\n", __func__); + + abe_be_dapm(rtd, dai->id, stream, SND_SOC_DAPM_STREAM_START); + + mutex_unlock(&fe_mutex); + return ret; +} + +static int omap_abe_dai_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int stream = substream->stream, ret = 0, i; + + dev_dbg(dai->dev,"%s: frontend %s \n", __func__, rtd->dai_link->name); + + mutex_lock(&fe_mutex); + + /* call hw_free on the frontend */ + ret = abe_fe_hw_free(substream, dai); + if (ret < 0) + dev_err(dai->dev,"%s: frontend hw_free failed\n", __func__); + + /* only hw_params backends that are either sinks or sources + * to this frontend DAI */ + for (i = 0; i < rtd->num_be[stream]; i++) { + struct snd_soc_pcm_runtime *be_rtd = rtd->be_rtd[i][stream]; + struct snd_pcm_substream *be_substream = + be_rtd->pcm->streams[stream].substream; + + if (be_substream == NULL) + continue; + + if (be_is_pending(rtd->be_rtd[i][stream], stream)) { + be_rtd->current_fe = dai->id; + snd_soc_pcm_hw_free(be_substream); + } + } + + mutex_unlock(&fe_mutex); + return ret; +} + +/* ABE Frontend PCM OPS */ +static struct snd_soc_dai_ops omap_abe_dai_ops = { + .startup = omap_abe_dai_startup, + .shutdown = omap_abe_dai_shutdown, + .hw_params = omap_abe_dai_hw_params, + .prepare = omap_abe_dai_prepare, + .hw_free = omap_abe_dai_hw_free, + .trigger = omap_abe_dai_trigger, +}; + +// TODO: finish this +static void mute_be_capture(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i; + + for (i = 0; i < rtd->num_be[SNDRV_PCM_STREAM_CAPTURE]; i++) { + be_rtd = rtd->be_rtd[i][SNDRV_PCM_STREAM_CAPTURE]; + + dev_dbg(&rtd->dev, "%s: be ID=%d\n", __func__, be_rtd->dai_link->be_id); + + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_UL: + abe_mute_gain(GAINS_AMIC, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_AMIC, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_BT_VX: + case OMAP_ABE_DAI_MM_FM: + case OMAP_ABE_DAI_MODEM: + break; + case OMAP_ABE_DAI_DMIC0: + abe_mute_gain(GAINS_DMIC1, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC1, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_DMIC1: + abe_mute_gain(GAINS_DMIC2, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC2, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_DMIC2: + abe_mute_gain(GAINS_DMIC3, GAIN_LEFT_OFFSET); + abe_mute_gain(GAINS_DMIC3, GAIN_RIGHT_OFFSET); + break; + } + } +} + +// TODO: finish this and restore correct volume levels +static void unmute_be_capture(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i; + + for (i = 0; i < rtd->num_be[SNDRV_PCM_STREAM_CAPTURE]; i++) { + be_rtd = rtd->be_rtd[i][SNDRV_PCM_STREAM_CAPTURE]; + + dev_dbg(&rtd->dev, "%s: be ID=%d\n", __func__, be_rtd->dai_link->be_id); + + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_UL: + abe_unmute_gain(GAINS_AMIC, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_AMIC, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_BT_VX: + case OMAP_ABE_DAI_MM_FM: + case OMAP_ABE_DAI_MODEM: + break; + case OMAP_ABE_DAI_DMIC0: + abe_unmute_gain(GAINS_DMIC1, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC1, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_DMIC1: + abe_unmute_gain(GAINS_DMIC2, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC2, GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_DMIC2: + abe_unmute_gain(GAINS_DMIC3, GAIN_LEFT_OFFSET); + abe_unmute_gain(GAINS_DMIC3, GAIN_RIGHT_OFFSET); + break; + } + } +} +#if 0 +static void mute_fe_playback(struct abe_frontend_dai *fe, + struct snd_soc_pcm_runtime *be_rtd, int mixer, int *volume) +{ + struct snd_soc_pcm_runtime *rtd = fe->substream->private_data; + + switch (rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + case ABE_FRONTEND_DAI_LP_MEDIA: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_read_mixer(mixer, volume, MIX_DL1_INPUT_MM_DL); + abe_write_mixer(mixer, MUTE_GAIN, RAMP_0MS, + MIX_DL1_INPUT_MM_DL); + } + break; + case ABE_FRONTEND_DAI_MODEM: + case ABE_FRONTEND_DAI_VOICE: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_read_mixer(mixer, volume, MIX_DL1_INPUT_VX_DL); + abe_write_mixer(mixer, MUTE_GAIN, RAMP_0MS, + MIX_DL1_INPUT_VX_DL); + } + break; + case ABE_FRONTEND_DAI_TONES: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_read_mixer(mixer, volume, MIX_DL1_INPUT_TONES); + abe_write_mixer(mixer, MUTE_GAIN, RAMP_0MS, + MIX_DL1_INPUT_TONES); + } + break; + default: + break; + } +} + +static void unmute_fe_playback(struct abe_frontend_dai *fe, + struct snd_soc_pcm_runtime *be_rtd, int mixer, int volume) +{ + struct snd_soc_pcm_runtime *rtd = fe->substream->private_data; + + switch (rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + case ABE_FRONTEND_DAI_LP_MEDIA: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_write_mixer(mixer, volume, RAMP_5MS, + MIX_DL1_INPUT_MM_DL); + } + break; + case ABE_FRONTEND_DAI_MODEM: + case ABE_FRONTEND_DAI_VOICE: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_write_mixer(mixer, volume, RAMP_5MS, + MIX_DL1_INPUT_VX_DL); + } + break; + case ABE_FRONTEND_DAI_TONES: + if (be_is_pending(be_rtd, SNDRV_PCM_STREAM_PLAYBACK)) { + abe_write_mixer(mixer, volume, RAMP_5MS, + MIX_DL1_INPUT_TONES); + } + break; + default: + break; + } +} +#endif +static void mute_be_playback(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i; + + for (i = 0; i < rtd->num_be[SNDRV_PCM_STREAM_PLAYBACK]; i++) { + be_rtd = rtd->be_rtd[i][SNDRV_PCM_STREAM_PLAYBACK]; + + dev_dbg(&rtd->dev, "%s: be ID=%d\n", __func__, be_rtd->dai_link->be_id); + + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_DL1: + abe_write_gain(GAINS_DL1, MUTE_GAIN, RAMP_5MS, + GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL1, MUTE_GAIN, RAMP_5MS, + GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_PDM_DL2: + abe_write_gain(GAINS_DL2, MUTE_GAIN, RAMP_5MS, + GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL2, MUTE_GAIN, RAMP_5MS, + GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_PDM_VIB: + case OMAP_ABE_DAI_BT_VX: + case OMAP_ABE_DAI_MM_FM: + case OMAP_ABE_DAI_MODEM: + break; + } + } +} + +static void unmute_be_playback(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i; + + for (i = 0; i < rtd->num_be[SNDRV_PCM_STREAM_PLAYBACK]; i++) { + be_rtd = rtd->be_rtd[i][SNDRV_PCM_STREAM_PLAYBACK]; + + dev_dbg(&rtd->dev, "%s: be ID=%d\n", __func__, be_rtd->dai_link->be_id); + + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_DL1: + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_5MS, + GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_5MS, + GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_PDM_DL2: + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_5MS, + GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_5MS, + GAIN_RIGHT_OFFSET); + break; + case OMAP_ABE_DAI_PDM_VIB: + case OMAP_ABE_DAI_BT_VX: + case OMAP_ABE_DAI_MM_FM: + case OMAP_ABE_DAI_MODEM: + break; + } + } +} + +static inline void abe_dai_enable_data_transfer(int port) +{ + pr_debug("%s : port %d\n", __func__, port); + if (port != PDM_DL_PORT) + abe_enable_data_transfer(port); +} + +static void enable_be_ports(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + abe_data_format_t format; + int i; + + for (i = 0; i < rtd->num_be[stream]; i++) { + be_rtd = rtd->be_rtd[i][stream]; + + dev_dbg(&rtd->dev, "%s: be ID=%d stream %d active %d\n", + __func__, be_rtd->dai_link->be_id, stream, + be_get_active(be_rtd, stream)); + + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_DL1: + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) + abe_dai_enable_data_transfer(PDM_DL_PORT); + abe_data.pdm_dl_status[0] = DAI_STARTED; + break; + case OMAP_ABE_DAI_PDM_DL2: + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) + abe_dai_enable_data_transfer(PDM_DL_PORT); + abe_data.pdm_dl_status[1] = DAI_STARTED; + break; + case OMAP_ABE_DAI_PDM_VIB: + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) + abe_dai_enable_data_transfer(PDM_DL_PORT); + abe_data.pdm_dl_status[2] = DAI_STARTED; + break; + case OMAP_ABE_DAI_PDM_UL: + if (be_is_pending(be_rtd, stream)) { + abe_dai_enable_data_transfer(PDM_UL_PORT); + } + abe_data.pdm_ul_status = DAI_STARTED; + break; + case OMAP_ABE_DAI_BT_VX: + if (be_is_pending(be_rtd, stream)) { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* BT_DL connection to McBSP 1 ports */ + format.f = 8000; + format.samp_format = MONO_RSHIFTED_16; + abe_connect_serial_port(BT_VX_DL_PORT, + &format, MCBSP1_TX); + abe_dai_enable_data_transfer(BT_VX_DL_PORT); + } else { + /* BT_UL connection to McBSP 1 ports */ + format.f = 8000; + format.samp_format = MONO_RSHIFTED_16; + abe_connect_serial_port(BT_VX_UL_PORT, + &format, MCBSP1_RX); + abe_dai_enable_data_transfer(BT_VX_UL_PORT); + } + } + break; + case OMAP_ABE_DAI_MM_FM: + if (be_is_pending(be_rtd, stream)) { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* MM_EXT connection to McBSP 2 ports */ + format.f = 48000; + format.samp_format = STEREO_RSHIFTED_16; + abe_connect_serial_port(MM_EXT_OUT_PORT, + &format, MCBSP2_TX); + abe_dai_enable_data_transfer(MM_EXT_OUT_PORT); + } else { + /* MM_EXT connection to McBSP 2 ports */ + format.f = 48000; + format.samp_format = STEREO_RSHIFTED_16; + abe_connect_serial_port(MM_EXT_IN_PORT, + &format, MCBSP2_RX); + abe_dai_enable_data_transfer(MM_EXT_IN_PORT); + } + } + break; + case OMAP_ABE_DAI_DMIC0: + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_enable_data_transfer(DMIC_PORT); + abe_data.dmic_status[0] = DAI_STARTED; + break; + case OMAP_ABE_DAI_DMIC1: + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_enable_data_transfer(DMIC_PORT1); + abe_data.dmic_status[1] = DAI_STARTED; + break; + case OMAP_ABE_DAI_DMIC2: + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_enable_data_transfer(DMIC_PORT2); + abe_data.dmic_status[2] = DAI_STARTED; + break; + } + } +} + +static void enable_fe_ports(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, stream); + + switch(rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_enable_data_transfer(MM_DL_PORT); + else + abe_enable_data_transfer(MM_UL_PORT); + break; + case ABE_FRONTEND_DAI_LP_MEDIA: + abe_enable_data_transfer(MM_DL_PORT); + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + if (stream == SNDRV_PCM_STREAM_CAPTURE) + abe_enable_data_transfer(MM_UL2_PORT); + break; + case ABE_FRONTEND_DAI_MODEM: + case ABE_FRONTEND_DAI_VOICE: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_enable_data_transfer(VX_DL_PORT); + else + abe_enable_data_transfer(VX_UL_PORT); + break; + case ABE_FRONTEND_DAI_TONES: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_enable_data_transfer(TONES_DL_PORT); + break; + case ABE_FRONTEND_DAI_VIBRA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_enable_data_transfer(VIB_DL_PORT); + break; + } +} + +static inline void abe_dai_disable_data_transfer(int port) +{ + pr_debug("%s : port %d\n", __func__, port); + if (port != PDM_DL_PORT) + abe_disable_data_transfer(port); +} + +static void disable_be_ports(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i; + + for (i = 0; i < rtd->num_be[stream]; i++) { + + be_rtd = rtd->be_rtd[i][stream]; + + dev_dbg(&rtd->dev, "%s: be ID=%d stream %d active %d\n", + __func__, be_rtd->dai_link->be_id, stream, + be_get_active(be_rtd, stream)); + + // TODO: main port active logic will be moved into HAL + switch (be_rtd->dai_link->be_id) { + case OMAP_ABE_DAI_PDM_DL1: + abe_data.pdm_dl_status[0] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) { + abe_dai_disable_data_transfer(PDM_DL_PORT); + } + break; + case OMAP_ABE_DAI_PDM_DL2: + abe_data.pdm_dl_status[1] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) { + abe_dai_disable_data_transfer(PDM_DL_PORT); + } + break; + case OMAP_ABE_DAI_PDM_VIB: + abe_data.pdm_dl_status[2] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && pdm_ready(&abe_data)) + abe_dai_disable_data_transfer(PDM_VIB_PORT); + break; + case OMAP_ABE_DAI_PDM_UL: + abe_data.pdm_ul_status = DAI_STOPPED; + if (be_is_pending(be_rtd, stream)) { + abe_dai_disable_data_transfer(PDM_UL_PORT); + } + break; + case OMAP_ABE_DAI_BT_VX: + if (be_is_pending(be_rtd, stream)) { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_dai_disable_data_transfer(BT_VX_DL_PORT); + else + abe_dai_disable_data_transfer(BT_VX_UL_PORT); + } + break; + case OMAP_ABE_DAI_MM_FM: + case OMAP_ABE_DAI_MODEM: + if (be_is_pending(be_rtd, stream)) { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_dai_disable_data_transfer(MM_EXT_OUT_PORT); + else + abe_dai_disable_data_transfer(MM_EXT_IN_PORT); + } + case OMAP_ABE_DAI_DMIC0: + abe_data.dmic_status[0] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_disable_data_transfer(DMIC_PORT); + break; + case OMAP_ABE_DAI_DMIC1: + abe_data.dmic_status[1] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_disable_data_transfer(DMIC_PORT1); + break; + case OMAP_ABE_DAI_DMIC2: + abe_data.dmic_status[2] = DAI_STOPPED; + if (be_is_pending(be_rtd, stream) && dmic_ready(&abe_data)) + abe_dai_disable_data_transfer(DMIC_PORT2); + break; + } + } +} + +static void disable_fe_ports(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, stream); + + switch(rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_disable_data_transfer(MM_DL_PORT); + else + abe_disable_data_transfer(MM_UL_PORT); + break; + case ABE_FRONTEND_DAI_LP_MEDIA: + abe_disable_data_transfer(MM_DL_PORT); + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + if (stream == SNDRV_PCM_STREAM_CAPTURE) + abe_disable_data_transfer(MM_UL2_PORT); + break; + case ABE_FRONTEND_DAI_MODEM: + case ABE_FRONTEND_DAI_VOICE: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_disable_data_transfer(VX_DL_PORT); + else + abe_disable_data_transfer(VX_UL_PORT); + break; + case ABE_FRONTEND_DAI_TONES: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_disable_data_transfer(TONES_DL_PORT); + break; + case ABE_FRONTEND_DAI_VIBRA: + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + abe_disable_data_transfer(VIB_DL_PORT); + break; + } +} + +/* TODO: finish this */ +static void mute_fe_port(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, stream); + + switch(rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + case ABE_FRONTEND_DAI_LP_MEDIA: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_MM_DL); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_MM_DL); + } + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + break; + case ABE_FRONTEND_DAI_VOICE: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_VX_DL); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_VX_DL); + } + break; + case ABE_FRONTEND_DAI_TONES: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL2, MIX_DL2_INPUT_TONES); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_mute_gain(MIXDL1, MIX_DL1_INPUT_TONES); + } + break; + case ABE_FRONTEND_DAI_VIBRA: + + break; + } +} + +/* TODO: finish this */ +static void unmute_fe_port(struct snd_pcm_substream *substream, int stream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, stream); + + switch(rtd->cpu_dai->id) { + case ABE_FRONTEND_DAI_MEDIA: + case ABE_FRONTEND_DAI_LP_MEDIA: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_MM_DL); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_MM_DL); + } + break; + case ABE_FRONTEND_DAI_MEDIA_CAPTURE: + break; + case ABE_FRONTEND_DAI_VOICE: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_VX_DL); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_VX_DL); + } + break; + case ABE_FRONTEND_DAI_TONES: + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL2][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL2, MIX_DL2_INPUT_TONES); + } + if (abe_data.be_active[OMAP_ABE_DAI_PDM_DL1][SNDRV_PCM_STREAM_PLAYBACK]) { + abe_unmute_gain(MIXDL1, MIX_DL1_INPUT_TONES); + } + break; + case ABE_FRONTEND_DAI_VIBRA: + + break; + } +} + +static void trigger_be_ports(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_pcm_runtime *be_rtd; + int i, stream = substream->stream; + + for (i = 0; i < rtd->num_be[stream]; i++) { + be_rtd = rtd->be_rtd[i][stream]; + + dev_dbg(&rtd->dev, "%s: be ID=%d cmd %d act %d\n", + __func__, be_rtd->dai_link->be_id, cmd, + abe_data.be_active[be_rtd->dai_link->be_id][stream]); + + if (be_is_pending(be_rtd, stream)) + snd_soc_dai_trigger(substream, cmd, be_rtd->cpu_dai); + } +} + +static void capture_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s-start: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, substream->stream); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* ALL BE GAINS set to mute */ + mute_be_capture(substream); + + /* Enable ALL ABE BE ports */ + enable_be_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + + /* DAI work must be started/stopped at least 250us after ABE */ + udelay(250); + + /* trigger ALL BE ports */ + trigger_be_ports(substream, cmd); + + /* Enable Frontend sDMA */ + enable_fe_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + + /* Restore ABE GAINS AMIC */ + unmute_be_capture(substream); + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + /* Enable sDMA / Enable ABE MM_UL2 */ + enable_fe_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + /* Disable sDMA / Enable ABE MM_UL2 */ + disable_fe_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + break; + case SNDRV_PCM_TRIGGER_STOP: + /* Disable sDMA */ + disable_fe_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + + disable_be_ports(substream, SNDRV_PCM_STREAM_CAPTURE); + + /* DAI work must be started/stopped at least 250us after ABE */ + udelay(250); + + /* trigger ALL BE ports */ + trigger_be_ports(substream, cmd); + break; + default: + break; + } + + dev_dbg(&rtd->dev, "%s - finish: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, substream->stream); +} + +static void playback_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + dev_dbg(&rtd->dev, "%s-start: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, substream->stream); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /* mute splayback */ + mute_be_playback(substream); + + /* enabled BE ports */ + enable_be_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* DAI work must be started/stopped at least 250us after ABE */ + udelay(250); + + /* trigger ALL BE ports */ + trigger_be_ports(substream, cmd); + + /* TODO: unmute DL1 */ + unmute_be_playback(substream); + + /* Enable Frontend sDMA */ + enable_fe_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* unmute ABE_MM_DL */ + unmute_fe_port(substream, SNDRV_PCM_STREAM_PLAYBACK); + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + /* Enable Frontend sDMA */ + enable_fe_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* unmute ABE_MM_DL */ + unmute_fe_port(substream, SNDRV_PCM_STREAM_PLAYBACK); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + /* Enable Frontend sDMA */ + disable_fe_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* mute ABE_MM_DL */ + mute_fe_port(substream, SNDRV_PCM_STREAM_PLAYBACK); + break; + case SNDRV_PCM_TRIGGER_STOP: + /* disable the transfer */ + disable_fe_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* mute ABE_MM_DL */ + mute_fe_port(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* TODO :mute Phoenix */ + + /* disable our backends */ + disable_be_ports(substream, SNDRV_PCM_STREAM_PLAYBACK); + + /* DAI work must be started/stopped at least 250us after ABE */ + udelay(250); + + /* trigger ALL BE ports */ + trigger_be_ports(substream, cmd); + break; + default: + break; + } + + dev_dbg(&rtd->dev, "%s - finish: fe ID=%d stream %d\n", + __func__, rtd->cpu_dai->id, substream->stream); +} + +static int omap_abe_dai_probe(struct snd_soc_dai *dai) +{ + snd_soc_dai_set_drvdata(dai, &abe_data); + + abe_data.workqueue = create_singlethread_workqueue("omap-abe"); + if (abe_data.workqueue == NULL) + return -ENOMEM; + return 0; +} + +static int omap_abe_dai_remove(struct snd_soc_dai *dai) +{ + destroy_workqueue(abe_data.workqueue); + return 0; +} + +static struct snd_soc_dai_driver omap_abe_dai[] = { + { /* Multimedia Playback and Capture */ + .name = "MultiMedia1", + .probe = omap_abe_dai_probe, + .remove = omap_abe_dai_remove, + .playback = { + .stream_name = "MultiMedia1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = OMAP_ABE_FORMATS, + }, + .capture = { + .stream_name = "MultiMedia1 Capture", + .channels_min = 2, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_48000, + .formats = OMAP_ABE_FORMATS, + }, + .ops = &omap_abe_dai_ops, + }, + { /* Multimedia Capture */ + .name = "MultiMedia2", + .capture = { + .stream_name = "MultiMedia2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = OMAP_ABE_FORMATS, + }, + .ops = &omap_abe_dai_ops, + }, + { /* Voice Playback and Capture */ + .name = "Voice", + .playback = { + .stream_name = "Voice Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = OMAP_ABE_FORMATS, + }, + .capture = { + .stream_name = "Voice Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = OMAP_ABE_FORMATS, + }, + .ops = &omap_abe_dai_ops, + }, + { /* Tones Playback */ + .name = "Tones", + .playback = { + .stream_name = "Tones Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = OMAP_ABE_FORMATS, + }, + .ops = &omap_abe_dai_ops, + }, + { /* Vibra */ + .name = "Vibra", + .playback = { + .stream_name = "Vibra Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .formats = OMAP_ABE_FORMATS, + }, + .ops = &omap_abe_dai_ops, + }, + { /* MODEM Voice Playback and Capture */ + .name = "MODEM", + .playback = { + .stream_name = "Voice Playback", + .channels_min = 1, + .channels_max = 1, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = OMAP_ABE_FORMATS | SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "Voice Capture", + .channels_min = 1, + .channels_max = 1, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, + .formats = OMAP_ABE_FORMATS | SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &omap_abe_dai_ops, + }, + { /* Low Power HiFi Playback */ + .name = "MultiMedia1 LP", + .playback = { + .stream_name = "MultiMedia1 LP Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, + .formats = OMAP_ABE_FORMATS | SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &omap_abe_dai_ops, + }, +}; + +static int __devinit omap_abe_probe(struct platform_device *pdev) +{ + return snd_soc_register_dais(&pdev->dev, omap_abe_dai, + ARRAY_SIZE(omap_abe_dai)); +} + +static int __devexit omap_abe_remove(struct platform_device *pdev) +{ + snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(omap_abe_dai)); + return 0; +} + +static struct platform_driver omap_abe_driver = { + .driver = { + .name = "omap-abe-dai", + .owner = THIS_MODULE, + }, + .probe = omap_abe_probe, + .remove = __devexit_p(omap_abe_remove), +}; + +static int __init omap_abe_init(void) +{ + return platform_driver_register(&omap_abe_driver); +} +module_init(omap_abe_init); + +static void __exit omap_abe_exit(void) +{ + platform_driver_unregister(&omap_abe_driver); +} +module_exit(omap_abe_exit); + +MODULE_AUTHOR("Liam Girdwood <lrg@slimlogic.co.uk>"); +MODULE_DESCRIPTION("OMAP ABE SoC Interface"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/omap-abe.h b/sound/soc/omap/omap-abe.h new file mode 100644 index 00000000000..bc33ad18818 --- /dev/null +++ b/sound/soc/omap/omap-abe.h @@ -0,0 +1,59 @@ +/* + * omap-abe.h + * + * Copyright (C) 2010 Texas Instruments + * + * Contact: Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __OMAP_ABE_H__ +#define __OMAP_ABE_H__ + +#define ABE_FRONTEND_DAI_MEDIA 0 +#define ABE_FRONTEND_DAI_MEDIA_CAPTURE 1 +#define ABE_FRONTEND_DAI_VOICE 2 +#define ABE_FRONTEND_DAI_TONES 3 +#define ABE_FRONTEND_DAI_VIBRA 4 +#define ABE_FRONTEND_DAI_MODEM 5 +#define ABE_FRONTEND_DAI_LP_MEDIA 6 + +/* This must currently match the BE order in DSP */ +#define OMAP_ABE_DAI_PDM_UL 0 +#define OMAP_ABE_DAI_PDM_DL1 1 +#define OMAP_ABE_DAI_PDM_DL2 2 +#define OMAP_ABE_DAI_PDM_VIB 3 +#define OMAP_ABE_DAI_BT_VX 4 +#define OMAP_ABE_DAI_MM_FM 5 +#define OMAP_ABE_DAI_MODEM 6 +#define OMAP_ABE_DAI_DMIC0 7 +#define OMAP_ABE_DAI_DMIC1 8 +#define OMAP_ABE_DAI_DMIC2 9 + +#define OMAP_ABE_BE_PDM_DL1 "(Backend) PDM-DL1" +#define OMAP_ABE_BE_PDM_UL1 "(Backend) PDM-UL1" +#define OMAP_ABE_BE_PDM_DL2 "(Backend) PDM-DL2" +#define OMAP_ABE_BE_PDM_VIB "(Backend) PDM-VIB" +#define OMAP_ABE_BE_BT_VX "(Backend) BT-VX" +#define OMAP_ABE_BE_MM_EXT0 "(Backend) FM-EXT" +#define OMAP_ABE_BE_MM_EXT1 "(Backend) MODEM-EXT" +#define OMAP_ABE_BE_DMIC0 "(Backend) DMIC0" +#define OMAP_ABE_BE_DMIC1 "(Backend) DMIC1" +#define OMAP_ABE_BE_DMIC2 "(Backend) DMIC2" + + +#endif /* End of __OMAP_MCPDM_H__ */ diff --git a/sound/soc/omap/omap-dmic.c b/sound/soc/omap/omap-dmic.c new file mode 100644 index 00000000000..886ca9bfb29 --- /dev/null +++ b/sound/soc/omap/omap-dmic.c @@ -0,0 +1,668 @@ +/* + * omap-dmic.c -- OMAP ASoC DMIC DAI driver + * + * Copyright (C) 2010 Texas Instruments + * + * Author: Liam Girdwood <lrg@slimlogic.co.uk> + * David Lambert <dlambert@ti.com> + * Misael Lopez Cruz <misael.lopez@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#undef DEBUG + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/wait.h> +#include <linux/interrupt.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> + +#include <plat/dma.h> +#include <plat/omap_hwmod.h> + +#include <sound/control.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> + +#include "omap-dmic.h" +#include "omap-pcm.h" + +#define OMAP_DMIC_RATES (SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) +#define OMAP_DMIC_FORMATS SNDRV_PCM_FMTBIT_S32_LE + +struct omap_dmic { + struct device *dev; + void __iomem *io_base; + int irq; + int clk_freq; + int sysclk; + int active; + spinlock_t lock; + struct omap_dmic_link *link; +}; + +static struct omap_dmic_link omap_dmic_link = { + .irq_mask = DMIC_IRQ_EMPTY | DMIC_IRQ_FULL, + .threshold = 2, + .format = DMICOUTFORMAT_LJUST, + .polar = DMIC_POLAR1 | DMIC_POLAR2 | DMIC_POLAR3, +}; + +/* + * Stream DMA parameters + */ +static struct omap_pcm_dma_data omap_dmic_dai_dma_params = { + .name = "DMIC capture", + .data_type = OMAP_DMA_DATA_TYPE_S32, + .sync_mode = OMAP_DMA_SYNC_PACKET, + .packet_size = 2, + .port_addr = OMAP44XX_DMIC_L3_BASE + DMIC_DATA, +}; + + +static inline void omap_dmic_write(struct omap_dmic *dmic, + u16 reg, u32 val) +{ + __raw_writel(val, dmic->io_base + reg); +} + +static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg) +{ + return __raw_readl(dmic->io_base + reg); +} + +#ifdef DEBUG +static void omap_dmic_reg_dump(struct omap_dmic *dmic) +{ + dev_dbg(dmic->dev, "***********************\n"); + dev_dbg(dmic->dev, "DMIC_IRQSTATUS_RAW: 0x%04x\n", + omap_dmic_read(dmic, DMIC_IRQSTATUS_RAW)); + dev_dbg(dmic->dev, "DMIC_IRQSTATUS: 0x%04x\n", + omap_dmic_read(dmic, DMIC_IRQSTATUS)); + dev_dbg(dmic->dev, "DMIC_IRQENABLE_SET: 0x%04x\n", + omap_dmic_read(dmic, DMIC_IRQENABLE_SET)); + dev_dbg(dmic->dev, "DMIC_IRQENABLE_CLR: 0x%04x\n", + omap_dmic_read(dmic, DMIC_IRQENABLE_CLR)); + dev_dbg(dmic->dev, "DMIC_IRQWAKE_EN: 0x%04x\n", + omap_dmic_read(dmic, DMIC_IRQWAKE_EN)); + dev_dbg(dmic->dev, "DMIC_DMAENABLE_SET: 0x%04x\n", + omap_dmic_read(dmic, DMIC_DMAENABLE_SET)); + dev_dbg(dmic->dev, "DMIC_DMAENABLE_CLR: 0x%04x\n", + omap_dmic_read(dmic, DMIC_DMAENABLE_CLR)); + dev_dbg(dmic->dev, "DMIC_DMAWAKEEN: 0x%04x\n", + omap_dmic_read(dmic, DMIC_DMAWAKEEN)); + dev_dbg(dmic->dev, "DMIC_CTRL: 0x%04x\n", + omap_dmic_read(dmic, DMIC_CTRL)); + dev_dbg(dmic->dev, "DMIC_DATA: 0x%04x\n", + omap_dmic_read(dmic, DMIC_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_CTRL: 0x%04x\n", + omap_dmic_read(dmic, DMIC_FIFO_CTRL)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC1R_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC1R_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC1L_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC1L_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC2R_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC2R_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC2L_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC2L_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC3R_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC3R_DATA)); + dev_dbg(dmic->dev, "DMIC_FIFO_DMIC3L_DATA: 0x%08x\n", + omap_dmic_read(dmic, DMIC_FIFO_DMIC3L_DATA)); + dev_dbg(dmic->dev, "***********************\n"); +} +#else +static void omap_dmic_reg_dump(struct omap_dmic *dmic) {} +#endif + +/* + * Enables the transfer through the DMIC interface + */ +static void omap_dmic_start(struct omap_dmic *dmic, int channels) +{ + int ctrl = omap_dmic_read(dmic, DMIC_CTRL); + omap_dmic_write(dmic, DMIC_CTRL, ctrl | channels); +} + +/* + * Disables the transfer through the DMIC interface + */ +static void omap_dmic_stop(struct omap_dmic *dmic, int channels) +{ + int ctrl = omap_dmic_read(dmic, DMIC_CTRL); + omap_dmic_write(dmic, DMIC_CTRL, ctrl & ~channels); +} + +/* + * Configures DMIC for audio recording. + * This function should be called before omap_dmic_start. + */ +static int omap_dmic_open(struct omap_dmic *dmic) +{ + struct omap_dmic_link *link = dmic->link; + int ctrl; + + /* Enable irq request generation */ + omap_dmic_write(dmic, DMIC_IRQENABLE_SET, + link->irq_mask & DMIC_IRQ_MASK); + + /* Configure uplink threshold */ + if (link->threshold > DMIC_THRES_MAX) + link->threshold = DMIC_THRES_MAX; + + omap_dmic_write(dmic, DMIC_FIFO_CTRL, link->threshold); + + /* Configure DMA controller */ + omap_dmic_write(dmic, DMIC_DMAENABLE_SET, DMIC_DMA_ENABLE); + + /* Set dmic out format */ + ctrl = omap_dmic_read(dmic, DMIC_CTRL) + & ~(DMIC_FORMAT | DMIC_POLAR_MASK); + omap_dmic_write(dmic, DMIC_CTRL, + ctrl | link->format | link->polar); + + return 0; +} + +/* + * Cleans DMIC uplink configuration. + * This function should be called when the stream is closed. + */ +static int omap_dmic_close(struct omap_dmic *dmic) +{ + struct omap_dmic_link *link = dmic->link; + + /* Disable irq request generation */ + omap_dmic_write(dmic, DMIC_IRQENABLE_CLR, + link->irq_mask & DMIC_IRQ_MASK); + + /* Disable DMA request generation */ + omap_dmic_write(dmic, DMIC_DMAENABLE_CLR, DMIC_DMA_ENABLE); + + return 0; +} + +static irqreturn_t omap_dmic_irq_handler(int irq, void *dev_id) +{ + struct omap_dmic *dmic = dev_id; + int irq_status; + + irq_status = omap_dmic_read(dmic, DMIC_IRQSTATUS); + + /* Acknowledge irq event */ + omap_dmic_write(dmic, DMIC_IRQSTATUS, irq_status); + if (irq_status & DMIC_IRQ_FULL) + dev_dbg(dmic->dev, "DMIC FIFO error %x\n", irq_status); + + if (irq_status & DMIC_IRQ_EMPTY) + dev_dbg(dmic->dev, "DMIC FIFO error %x\n", irq_status); + + if (irq_status & DMIC_IRQ) + dev_dbg(dmic->dev, "DMIC write request\n"); + + return IRQ_HANDLED; +} + +static int omap_dmic_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + + if (!dmic->active++) + pm_runtime_get_sync(dmic->dev); + + return 0; +} + +static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + + if (!--dmic->active) + pm_runtime_put_sync(dmic->dev); +} + +static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + struct omap_dmic_link *link = dmic->link; + int channels; + int ret = 0; + + channels = params_channels(params); + switch (channels) { + case 1: + case 2: + link->channels = 2; + break; + default: + dev_err(dmic->dev, "invalid number of channels\n"); + return -EINVAL; + } + + omap_dmic_dai_dma_params.packet_size = link->threshold * link->channels; + snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params); + + if (dmic->active == 1) + ret = omap_dmic_open(dmic); + + return ret; +} + +static int omap_dmic_dai_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + struct omap_dmic_link *link = dmic->link; + int ret = 0; + + if (dmic->active == 1) { + ret = omap_dmic_close(dmic); + link->channels = 0; + } + + return ret; +} + +static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + int dmic_id = 1 << dai->id; + + omap_dmic_reg_dump(dmic); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + omap_dmic_start(dmic, dmic_id); + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + case SNDRV_PCM_TRIGGER_STOP: + omap_dmic_stop(dmic, dmic_id); + break; + default: + break; + } + + return 0; +} + +static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, + int dir) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + struct clk *dmic_clk, *parent_clk; + int ret = 0; + + dmic_clk = clk_get(NULL, "dmic_fck"); + if (IS_ERR(dmic_clk)) + return -ENODEV; + + switch (clk_id) { + case OMAP_DMIC_SYSCLK_PAD_CLKS: + parent_clk = clk_get(NULL, "pad_clks_ck"); + if (IS_ERR(parent_clk)) { + ret = -ENODEV; + goto err_par; + } + break; + case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS: + parent_clk = clk_get(NULL, "slimbus_clk"); + if (IS_ERR(parent_clk)) { + ret = -ENODEV; + goto err_par; + } + break; + case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS: + parent_clk = clk_get(NULL, "dmic_sync_mux_ck"); + if (IS_ERR(parent_clk)) { + ret = -ENODEV; + goto err_par; + } + break; + default: + dev_err(dai->dev, "clk_id not supported %d\n", clk_id); + ret = -EINVAL; + goto err_par; + } + + switch (freq) { + case 19200000: + case 24000000: + case 24576000: + case 12000000: + dmic->clk_freq = freq; + break; + default: + dev_err(dai->dev, "clk freq not supported %d\n", freq); + ret = -EINVAL; + goto err_freq; + } + + if (dmic->sysclk != clk_id) { + /* reparent not allowed if a stream is ongoing */ + if (dmic->active > 1) + return -EBUSY; + + /* disable clock while reparenting */ + if (dmic->active == 1) + pm_runtime_put_sync(dmic->dev); + + ret = clk_set_parent(dmic_clk, parent_clk); + + if (dmic->active == 1) + pm_runtime_get_sync(dmic->dev); + + dmic->sysclk = clk_id; + } + +err_freq: + clk_put(parent_clk); +err_par: + clk_put(dmic_clk); + + return ret; +} + +static int omap_dmic_set_clkdiv(struct snd_soc_dai *dai, + int div_id, int div) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + int ctrl, div_sel = -EINVAL; + + if (div_id != OMAP_DMIC_CLKDIV) + return -ENODEV; + + switch (dmic->clk_freq) { + case 19200000: + if (div == 5) + div_sel = 0x1; + else if (div == 8) + div_sel = 0x0; + break; + case 24000000: + if (div == 10) + div_sel = 0x2; + break; + case 24576000: + if (div == 8) + div_sel = 0x3; + else if (div == 16) + div_sel = 0x4; + break; + case 12000000: + if (div == 5) + div_sel = 0x5; + break; + default: + dev_err(dai->dev, "invalid freq %d\n", dmic->clk_freq); + return -EINVAL; + } + + if (div_sel < 0) { + dev_err(dai->dev, "divider not supported %d\n", div); + return -EINVAL; + } + + ctrl = omap_dmic_read(dmic, DMIC_CTRL) & ~DMIC_CLK_DIV_MASK; + omap_dmic_write(dmic, DMIC_CTRL, + ctrl | (div_sel << DMIC_CLK_DIV_SHIFT)); + + return 0; +} + +static struct snd_soc_dai_ops omap_dmic_dai_ops = { + .startup = omap_dmic_dai_startup, + .shutdown = omap_dmic_dai_shutdown, + .hw_params = omap_dmic_dai_hw_params, + .trigger = omap_dmic_dai_trigger, + .hw_free = omap_dmic_dai_hw_free, + .set_sysclk = omap_dmic_set_dai_sysclk, + .set_clkdiv = omap_dmic_set_clkdiv, +}; + +#if defined(CONFIG_SND_OMAP_SOC_ABE_DSP) || \ + defined(CONFIG_SND_OMAP_SOC_ABE_DSP_MODULE) +static int omap_dmic_abe_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai); + int dmic_id = DMIC_UP1_ENABLE | DMIC_UP2_ENABLE | DMIC_UP3_ENABLE; + + omap_dmic_reg_dump(dmic); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (dmic->active == 1) + omap_dmic_start(dmic, dmic_id); + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + case SNDRV_PCM_TRIGGER_STOP: + if (dmic->active == 1) + omap_dmic_stop(dmic, dmic_id); + break; + default: + break; + } + + return 0; +} + +static struct snd_soc_dai_ops omap_dmic_abe_dai_ops = { + .startup = omap_dmic_dai_startup, + .shutdown = omap_dmic_dai_shutdown, + .hw_params = omap_dmic_dai_hw_params, + .trigger = omap_dmic_abe_dai_trigger, + .hw_free = omap_dmic_dai_hw_free, + .set_sysclk = omap_dmic_set_dai_sysclk, + .set_clkdiv = omap_dmic_set_clkdiv, +}; +#endif + +static struct snd_soc_dai_driver omap_dmic_dai[] = { +{ + .name = "omap-dmic-dai-0", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_dai_ops, +}, +{ + .name = "omap-dmic-dai-1", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_abe_dai_ops, +}, +{ + .name = "omap-dmic-dai-2", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_abe_dai_ops, +}, +#if defined(CONFIG_SND_OMAP_SOC_ABE_DSP) || \ + defined(CONFIG_SND_OMAP_SOC_ABE_DSP_MODULE) +{ + .name = "omap-dmic-abe-dai-0", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_abe_dai_ops, +}, +{ + .name = "omap-dmic-abe-dai-1", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_abe_dai_ops, +}, +{ + .name = "omap-dmic-abe-dai-2", + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_DMIC_RATES, + .formats = OMAP_DMIC_FORMATS, + }, + .ops = &omap_dmic_abe_dai_ops, +}, +#endif +}; + +static __devinit int asoc_dmic_probe(struct platform_device *pdev) +{ + struct omap_dmic *dmic; + struct resource *res; + int ret; + + dmic = kzalloc(sizeof(struct omap_dmic), GFP_KERNEL); + if (!dmic) + return -ENOMEM; + + platform_set_drvdata(pdev, dmic); + dmic->dev = &pdev->dev; + dmic->link = &omap_dmic_link; + + spin_lock_init(&dmic->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dmic->dev, "invalid memory resource\n"); + ret = -ENODEV; + goto err_res; + } + + dmic->io_base = ioremap(res->start, resource_size(res)); + if (!dmic->io_base) { + ret = -ENOMEM; + goto err_res; + } + + dmic->irq = platform_get_irq(pdev, 0); + if (dmic->irq < 0) { + ret = dmic->irq; + goto err_irq; + } + + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!res) { + dev_err(dmic->dev, "invalid dma resource\n"); + ret = -ENODEV; + goto err_irq; + } + omap_dmic_dai_dma_params.dma_req = res->start; + + pm_runtime_enable(dmic->dev); + + /* Disable lines while request is ongoing */ + omap_dmic_write(dmic, DMIC_CTRL, 0x00); + + ret = request_threaded_irq(dmic->irq, NULL, omap_dmic_irq_handler, + IRQF_ONESHOT, "DMIC", (void *)dmic); + if (ret) { + dev_err(dmic->dev, "irq request failed\n"); + goto err_irq; + } + + ret = snd_soc_register_dais(&pdev->dev, omap_dmic_dai, + ARRAY_SIZE(omap_dmic_dai)); + if (ret) + goto err_dai; + + return 0; + +err_dai: + free_irq(dmic->irq, (void *)dmic); +err_irq: + iounmap(dmic->io_base); +err_res: + kfree(dmic); + return ret; +} + +static int __devexit asoc_dmic_remove(struct platform_device *pdev) +{ + struct omap_dmic *dmic = platform_get_drvdata(pdev); + + snd_soc_unregister_dai(&pdev->dev); + iounmap(dmic->io_base); + free_irq(dmic->irq, (void *)dmic); + kfree(dmic); + + return 0; +} + +static struct platform_driver asoc_dmic_driver = { + .driver = { + .name = "omap-dmic-dai", + .owner = THIS_MODULE, + }, + .probe = asoc_dmic_probe, + .remove = __devexit_p(asoc_dmic_remove), +}; + +static int __init snd_omap_dmic_init(void) +{ + return platform_driver_register(&asoc_dmic_driver); +} +module_init(snd_omap_dmic_init); + +static void __exit snd_omap_dmic_exit(void) +{ + platform_driver_unregister(&asoc_dmic_driver); +} +module_exit(snd_omap_dmic_exit); + +MODULE_AUTHOR("David Lambert <dlambert@ti.com>"); +MODULE_DESCRIPTION("OMAP DMIC SoC Interface"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/omap-dmic.h b/sound/soc/omap/omap-dmic.h new file mode 100644 index 00000000000..4f86371f80f --- /dev/null +++ b/sound/soc/omap/omap-dmic.h @@ -0,0 +1,103 @@ +/* + * omap-dmic.h -- OMAP Digital Microphone Controller + * + * Author: Liam Girdwood <lrg@slimlogic.co.uk> + * David Lambert <dlambert@ti.com> + * Misael Lopez Cruz <misael.lopez@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _OMAP_DMIC_H +#define _OMAP_DMIC_H + +#include <sound/soc.h> + +#define OMAP44XX_DMIC_L3_BASE 0x4902e000 + +#define DMIC_REVISION 0x00 +#define DMIC_SYSCONFIG 0x10 +#define DMIC_IRQSTATUS_RAW 0x24 +#define DMIC_IRQSTATUS 0x28 +#define DMIC_IRQENABLE_SET 0x2C +#define DMIC_IRQENABLE_CLR 0x30 +#define DMIC_IRQWAKE_EN 0x34 +#define DMIC_DMAENABLE_SET 0x38 +#define DMIC_DMAENABLE_CLR 0x3C +#define DMIC_DMAWAKEEN 0x40 +#define DMIC_CTRL 0x44 +#define DMIC_DATA 0x48 +#define DMIC_FIFO_CTRL 0x4C +#define DMIC_FIFO_DMIC1R_DATA 0x50 +#define DMIC_FIFO_DMIC1L_DATA 0x54 +#define DMIC_FIFO_DMIC2R_DATA 0x58 +#define DMIC_FIFO_DMIC2L_DATA 0x5C +#define DMIC_FIFO_DMIC3R_DATA 0x60 +#define DMIC_FIFO_DMIC3L_DATA 0x64 + +/* + * DMIC_IRQ bit fields + * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR + */ + +#define DMIC_IRQ (1 << 0) +#define DMIC_IRQ_FULL (1 << 1) +#define DMIC_IRQ_ALMST_EMPTY (1 << 2) +#define DMIC_IRQ_EMPTY (1 << 3) +#define DMIC_IRQ_MASK 0x07 + +/* + * DMIC_DMAENABLE bit fields + */ + +#define DMIC_DMA_ENABLE 0x1 + +/* + * DMIC_CTRL bit fields + */ + +#define DMIC_UP1_ENABLE 0x0001 +#define DMIC_UP2_ENABLE 0x0002 +#define DMIC_UP3_ENABLE 0x0004 +#define DMIC_FORMAT 0x0008 +#define DMIC_POLAR1 0x0010 +#define DMIC_POLAR2 0x0020 +#define DMIC_POLAR3 0x0040 +#define DMIC_POLAR_MASK 0x0070 +#define DMIC_CLK_DIV_SHIFT 7 +#define DMIC_CLK_DIV_MASK 0x0380 +#define DMIC_RESET 0x0400 + +#define DMIC_ENABLE_MASK 0x007 + +#define DMICOUTFORMAT_LJUST (0 << 3) +#define DMICOUTFORMAT_RJUST (1 << 3) + +/* + * DMIC_FIFO_CTRL bit fields + */ + +#define DMIC_THRES_MAX 0xF + +enum omap_dmic_clk { + OMAP_DMIC_SYSCLK_PAD_CLKS, /* PAD_CLKS */ + OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS, /* SLIMBUS_CLK */ + OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS, /* DMIC_SYNC_MUX_CLK */ +}; + +/* DMIC dividers */ +enum omap_dmic_div { + OMAP_DMIC_CLKDIV, +}; + +struct omap_dmic_link { + int irq_mask; + int threshold; + int format; + int channels; + int polar; +}; + +#endif diff --git a/sound/soc/omap/omap-hdmi.c b/sound/soc/omap/omap-hdmi.c new file mode 100644 index 00000000000..e19f062788c --- /dev/null +++ b/sound/soc/omap/omap-hdmi.c @@ -0,0 +1,150 @@ +/* + * omap-hdmi.c + * + * OMAP ALSA SoC DAI driver for HDMI audio on OMAP4 processors. + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Authors: Jorge Candelaria <jorge.candelaria@gmail.com> + * Ricardo Neri <ricardo.neri@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/initval.h> +#include <sound/soc.h> + +#include <plat/dma.h> +#include <plat/display.h> +#include <plat/omap44xx.h> +#include "omap-pcm.h" +#include "omap-hdmi.h" + +static struct omap_pcm_dma_data omap_hdmi_dai_dma_params = { + .name = "HDMI playback", + .dma_req = OMAP44XX_DMA_DSS_HDMI_REQ, + .port_addr = OMAP44XX_DSS_HDMI_L3_BASE + OMAP44XX_HDMI_AUDIO_DMA_PORT, + .sync_mode = OMAP_DMA_SYNC_PACKET, +}; + +static int omap_hdmi_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int err = 0, i; + struct omap_overlay *ovl = NULL; + + /* + * Make sure that the period bytes are multiple of the DMA packet size. + * Largest packet size we use is 32 32-bit words = 128 bytes + */ + err = snd_pcm_hw_constraint_step(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 128); + if (err < 0) + return err; + + /* find DSS HDMI device */ + for (i = 0; i < omap_dss_get_num_overlays(); i++) { + ovl = omap_dss_get_overlay(i); + if (strcmp(ovl->manager->device->name, "hdmi") == 0) + break; + } + if (ovl->manager->device->state != OMAP_DSS_DISPLAY_ACTIVE) { + printk(KERN_ERR "HDMI display is not active!"); + return -EIO; + } + return err; +} + +static int omap_hdmi_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + int err = 0; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + omap_hdmi_dai_dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; + omap_hdmi_dai_dma_params.packet_size = 16; + break; + case SNDRV_PCM_FORMAT_S24_LE: + omap_hdmi_dai_dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; + omap_hdmi_dai_dma_params.packet_size = 32; + break; + default: + err = -EINVAL; + } + + snd_soc_dai_set_dma_data(dai, substream, + &omap_hdmi_dai_dma_params); + + return err; +} + +static struct snd_soc_dai_ops omap_hdmi_dai_ops = { + .startup = omap_hdmi_dai_startup, + .hw_params = omap_hdmi_dai_hw_params, +}; + +static struct snd_soc_dai_driver omap_hdmi_dai = { + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = OMAP_HDMI_RATES, + .formats = OMAP_HDMI_FORMATS, + }, + .ops = &omap_hdmi_dai_ops, +}; + +static __devinit int omap_hdmi_probe(struct platform_device *pdev) +{ + return snd_soc_register_dai(&pdev->dev, &omap_hdmi_dai); +} + +static int __devexit omap_hdmi_remove(struct platform_device *pdev) +{ + snd_soc_unregister_dai(&pdev->dev); + return 0; +} + +static struct platform_driver hdmi_dai_driver = { + .driver = { + .name = "hdmi-audio-dai", + .owner = THIS_MODULE, + }, + .probe = omap_hdmi_probe, + .remove = __devexit_p(omap_hdmi_remove), +}; + +static int __init hdmi_dai_init(void) +{ + return platform_driver_register(&hdmi_dai_driver); +} +module_init(hdmi_dai_init); + +static void __exit hdmi_dai_exit(void) +{ + platform_driver_unregister(&hdmi_dai_driver); +} +module_exit(hdmi_dai_exit); + +MODULE_AUTHOR("Jorge Candelaria <jorge.candelaria@gmail.com>"); +MODULE_AUTHOR("Ricardo Neri <ricardo.neri@ti.com>"); +MODULE_DESCRIPTION("OMAP HDMI SoC Interface"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/omap-hdmi.h b/sound/soc/omap/omap-hdmi.h new file mode 100644 index 00000000000..77bc7851f37 --- /dev/null +++ b/sound/soc/omap/omap-hdmi.h @@ -0,0 +1,36 @@ +/* + * omap-hdmi.h + * + * Definitions for OMAP ALSA SoC DAI driver for HDMI audio on OMAP4 processors. + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Autors: Jorge Candelaria <jorge.candelaria@gmail.com> + * Ricardo Neri <ricardo.neri@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __OMAP_HDMI_H__ +#define __OMAP_HDMI_H__ + +#define OMAP44XX_HDMI_AUDIO_DMA_PORT 0x8c + +#define OMAP_HDMI_RATES (SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) + +#define OMAP_HDMI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +#endif diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index 2175f09e57b..a7f6ece85eb 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -102,6 +102,7 @@ static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words); } +#if 0 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { @@ -120,6 +121,7 @@ static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, frames.integer = 1; return snd_interval_refine(buffer_size, &frames); } +#endif static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) @@ -151,6 +153,7 @@ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, * Rule for the buffer size. We should not allow * smaller buffer than the FIFO size to avoid underruns */ +#if 0 // FIXME: All BE must support hw_rules and constraints */ snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, omap_mcbsp_hwrule_min_buffersize, @@ -160,6 +163,7 @@ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, /* Make sure, that the period size is always even */ snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); +#endif } return err; diff --git a/sound/soc/omap/omap-mcpdm.c b/sound/soc/omap/omap-mcpdm.c index bed09c27e44..a68546d228a 100644 --- a/sound/soc/omap/omap-mcpdm.c +++ b/sound/soc/omap/omap-mcpdm.c @@ -25,7 +25,17 @@ #include <linux/init.h> #include <linux/module.h> -#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/wait.h> +#include <linux/interrupt.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/pm_runtime.h> +#include <linux/workqueue.h> + #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> @@ -33,35 +43,62 @@ #include <sound/soc.h> #include <plat/dma.h> +#include <plat/mcpdm.h> #include <plat/mcbsp.h> -#include "mcpdm.h" +#include <plat/omap_hwmod.h> +#include "omap-mcpdm.h" #include "omap-pcm.h" +#ifdef CONFIG_SND_OMAP_SOC_ABE_DSP +#include "omap-abe-dsp.h" +#include "abe/abe_main.h" +#endif struct omap_mcpdm_data { struct omap_mcpdm_link *links; - int active; +}; + +struct omap_mcpdm { + struct device *dev; + unsigned long phys_base; + void __iomem *io_base; + u8 free; + int irq; + struct delayed_work delayed_work; +#ifdef CONFIG_SND_OMAP_SOC_ABE_DSP + struct delayed_work delayed_abe_work; +#endif + + struct mutex mutex; + struct omap_mcpdm_platform_data *pdata; + struct omap_mcpdm_link *downlink; + struct omap_mcpdm_link *uplink; + struct completion irq_completion; + + int dn_channels; + int up_channels; + int dl_active; + int ul_active; + + /* DC offset */ + int dl1_offset; + int dl2_offset; }; static struct omap_mcpdm_link omap_mcpdm_links[] = { /* downlink */ { .irq_mask = MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL, - .threshold = 1, + .threshold = 2, .format = PDMOUTFORMAT_LJUST, }, /* uplink */ { .irq_mask = MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL, - .threshold = 1, + .threshold = 2, .format = PDMOUTFORMAT_LJUST, }, }; -static struct omap_mcpdm_data mcpdm_data = { - .links = omap_mcpdm_links, - .active = 0, -}; - /* * Stream DMA parameters */ @@ -84,13 +121,413 @@ static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = { }, }; +static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, + u16 reg, u32 val) +{ + __raw_writel(val, mcpdm->io_base + reg); +} + +static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg) +{ + return __raw_readl(mcpdm->io_base + reg); +} + +#ifdef DEBUG +static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) +{ + dev_dbg(mcpdm->dev, "***********************\n"); + dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_IRQSTATUS_RAW)); + dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_IRQSTATUS)); + dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_IRQENABLE_SET)); + dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_IRQENABLE_CLR)); + dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_IRQWAKE_EN)); + dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_DMAENABLE_SET)); + dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_DMAENABLE_CLR)); + dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_DMAWAKEEN)); + dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_CTRL)); + dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_DN_DATA)); + dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_UP_DATA)); + dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_FIFO_CTRL_DN)); + dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_FIFO_CTRL_UP)); + dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n", + omap_mcpdm_read(mcpdm, MCPDM_DN_OFFSET)); + dev_dbg(mcpdm->dev, "***********************\n"); +} +#else +static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {} +#endif + +/* + * Takes the McPDM module in and out of reset state. + * Uplink and downlink can be reset individually. + */ +static void omap_mcpdm_reset_capture(struct omap_mcpdm * mcpdm, + int reset) +{ + int ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + + if (reset) + ctrl |= SW_UP_RST; + else + ctrl &= ~SW_UP_RST; + + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); +} + +static void omap_mcpdm_reset_playback(struct omap_mcpdm * mcpdm, + int reset) +{ + int ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + + if (reset) + ctrl |= SW_DN_RST; + else + ctrl &= ~SW_DN_RST; + + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); +} + +/* + * Enables the transfer through the PDM interface to/from the Phoenix + * codec by enabling the corresponding UP or DN channels. + */ +static void omap_mcpdm_start(struct omap_mcpdm *mcpdm, int stream) +{ + int ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + + if (stream) { + ctrl |= SW_UP_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl |= mcpdm->up_channels; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~SW_UP_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + } else { + ctrl |= SW_DN_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl |= mcpdm->dn_channels; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~SW_DN_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + } +} + +/* + * Disables the transfer through the PDM interface to/from the Phoenix + * codec by disabling the corresponding UP or DN channels. + */ +static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm, int stream) +{ + int ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + + if (stream) { + ctrl |= SW_UP_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~mcpdm->up_channels; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~SW_UP_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + } else { + ctrl |= SW_DN_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~mcpdm->dn_channels; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + ctrl &= ~SW_DN_RST; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + } +} + +/* + * Configures McPDM uplink for audio recording. + * This function should be called before omap_mcpdm_start. + */ +static int omap_mcpdm_capture_open(struct omap_mcpdm *mcpdm, + struct omap_mcpdm_link *uplink) +{ + int irq_mask = 0; + int ctrl; + + /* Enable irq request generation */ + irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; + omap_mcpdm_write(mcpdm, MCPDM_IRQENABLE_SET, irq_mask); + + /* Configure uplink threshold */ + if (uplink->threshold > UP_THRES_MAX) + uplink->threshold = UP_THRES_MAX; + + omap_mcpdm_write(mcpdm, MCPDM_FIFO_CTRL_UP, uplink->threshold); + + /* Configure DMA controller */ + omap_mcpdm_write(mcpdm, MCPDM_DMAENABLE_SET, DMA_UP_ENABLE); + + /* Set pdm out format */ + ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + ctrl &= ~PDMOUTFORMAT; + ctrl |= uplink->format & PDMOUTFORMAT; + + /* Uplink channels */ + mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK); + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + + return 0; +} + +/* + * Configures McPDM downlink for audio playback. + * This function should be called before omap_mcpdm_start. + */ +static int omap_mcpdm_playback_open(struct omap_mcpdm *mcpdm, + struct omap_mcpdm_link *downlink) +{ + int irq_mask = 0; + int ctrl; + + /* Enable irq request generation */ + irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; + omap_mcpdm_write(mcpdm, MCPDM_IRQENABLE_SET, irq_mask); + + /* Configure uplink threshold */ + if (downlink->threshold > DN_THRES_MAX) + downlink->threshold = DN_THRES_MAX; + + omap_mcpdm_write(mcpdm, MCPDM_FIFO_CTRL_DN, downlink->threshold); + + /* Enable DMA request generation */ + omap_mcpdm_write(mcpdm, MCPDM_DMAENABLE_SET, DMA_DN_ENABLE); + + /* Set pdm out format */ + ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + ctrl &= ~PDMOUTFORMAT; + ctrl |= downlink->format & PDMOUTFORMAT; + + /* Downlink channels */ + mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK); + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + + return 0; +} + +/* + * Cleans McPDM uplink configuration. + * This function should be called when the stream is closed. + */ +static int omap_mcpdm_capture_close(struct omap_mcpdm *mcpdm, + struct omap_mcpdm_link *uplink) +{ + int irq_mask = 0; + + /* Disable irq request generation */ + irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK; + omap_mcpdm_write(mcpdm, MCPDM_IRQENABLE_CLR, irq_mask); + + /* Disable DMA request generation */ + omap_mcpdm_write(mcpdm, MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE); + + /* Clear Downlink channels */ + mcpdm->up_channels = 0; + + return 0; +} + +/* + * Cleans McPDM downlink configuration. + * This function should be called when the stream is closed. + */ +static int omap_mcpdm_playback_close(struct omap_mcpdm *mcpdm, + struct omap_mcpdm_link *downlink) +{ + int irq_mask = 0; + + /* Disable irq request generation */ + irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK; + omap_mcpdm_write(mcpdm, MCPDM_IRQENABLE_CLR, irq_mask); + + /* Disable DMA request generation */ + omap_mcpdm_write(mcpdm, MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE); + + /* clear Downlink channels */ + mcpdm->dn_channels = 0; + + return 0; +} + +static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id) +{ + struct omap_mcpdm *mcpdm = dev_id; + int irq_status; + + irq_status = omap_mcpdm_read(mcpdm, MCPDM_IRQSTATUS); + + /* Acknowledge irq event */ + omap_mcpdm_write(mcpdm, MCPDM_IRQSTATUS, irq_status); + + if (irq & MCPDM_DN_IRQ_FULL) { + dev_err(mcpdm->dev, "DN FIFO error %x\n", irq_status); + omap_mcpdm_reset_playback(mcpdm, 1); + omap_mcpdm_playback_open(mcpdm, mcpdm->downlink); + omap_mcpdm_reset_playback(mcpdm, 0); + } + + if (irq & MCPDM_DN_IRQ_EMPTY) { + dev_err(mcpdm->dev, "DN FIFO error %x\n", irq_status); + omap_mcpdm_reset_playback(mcpdm, 1); + omap_mcpdm_playback_open(mcpdm, mcpdm->downlink); + omap_mcpdm_reset_playback(mcpdm, 0); + } + + if (irq & MCPDM_DN_IRQ) { + dev_dbg(mcpdm->dev, "DN write request\n"); + } + + if (irq & MCPDM_UP_IRQ_FULL) { + dev_err(mcpdm->dev, "UP FIFO error %x\n", irq_status); + omap_mcpdm_reset_capture(mcpdm, 1); + omap_mcpdm_capture_open(mcpdm, mcpdm->uplink); + omap_mcpdm_reset_capture(mcpdm, 0); + } + + if (irq & MCPDM_UP_IRQ_EMPTY) { + dev_err(mcpdm->dev, "UP FIFO error %x\n", irq_status); + omap_mcpdm_reset_capture(mcpdm, 1); + omap_mcpdm_capture_open(mcpdm, mcpdm->uplink); + omap_mcpdm_reset_capture(mcpdm, 0); + } + + if (irq & MCPDM_UP_IRQ) { + dev_dbg(mcpdm->dev, "UP write request\n"); + } + + return IRQ_HANDLED; +} + +static int omap_mcpdm_request(struct omap_mcpdm *mcpdm) +{ + struct platform_device *pdev; + struct omap_mcpdm_platform_data *pdata; + int ctrl; + int attemps = 0; + + pdev = to_platform_device(mcpdm->dev); + pdata = pdev->dev.platform_data; + + if (!mcpdm->free) { + dev_err(mcpdm->dev, "McPDM interface is in use\n"); + return -EBUSY; + } + mcpdm->free = 0; + + pm_runtime_get_sync(&pdev->dev); + + /* Perform SW RESET of McPDM IP */ + ctrl = omap_mcpdm_read(mcpdm, MCPDM_SYSCONFIG); + ctrl |= MCPDM_SOFTRESET; + omap_mcpdm_write(mcpdm, MCPDM_SYSCONFIG, ctrl); + /* Wait completion of SW RESET */ + while ((omap_mcpdm_read(mcpdm, MCPDM_SYSCONFIG) & MCPDM_SOFTRESET)) { + if (attemps++ > 10000) { + udelay(10); + dev_err(mcpdm->dev, "Could not RESET McPDM\n"); + } + } + + /* Disable lines while request is ongoing */ + omap_mcpdm_write(mcpdm, MCPDM_CTRL, 0x00); + + if (omap_rev() != OMAP4430_REV_ES1_0) { + /* Enable McPDM watch dog for ES above ES 1.0 to avoid saturation */ + ctrl = omap_mcpdm_read(mcpdm, MCPDM_CTRL); + ctrl |= WD_EN; + omap_mcpdm_write(mcpdm, MCPDM_CTRL, ctrl); + } + + return 0; +} + +static void omap_mcpdm_free(struct omap_mcpdm *mcpdm) +{ + struct platform_device *pdev; + struct omap_mcpdm_platform_data *pdata; + + pdev = to_platform_device(mcpdm->dev); + pdata = pdev->dev.platform_data; + + if (mcpdm->free) { + dev_err(mcpdm->dev, "McPDM interface is already free\n"); + return; + } + mcpdm->free = 1; + + pm_runtime_put_sync(&pdev->dev); +} + +/* Enable/disable DC offset cancelation for the analog + * headset path (PDM channels 1 and 2). + */ +static int omap_mcpdm_set_offset(struct omap_mcpdm *mcpdm) +{ + int offset; + + if ((mcpdm->dl1_offset > DN_OFST_MAX) || + (mcpdm->dl2_offset > DN_OFST_MAX)) + return -EINVAL; + + offset = (mcpdm->dl1_offset << DN_OFST_RX1) | + (mcpdm->dl2_offset << DN_OFST_RX2); + + /* offset cancellation for channel 1 */ + if (mcpdm->dl1_offset) + offset |= DN_OFST_RX1_EN; + else + offset &= ~DN_OFST_RX1_EN; + + /* offset cancellation for channel 2 */ + if (mcpdm->dl2_offset) + offset |= DN_OFST_RX2_EN; + else + offset &= ~DN_OFST_RX2_EN; + + omap_mcpdm_write(mcpdm, MCPDM_DN_OFFSET, offset); + + return 0; +} + static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); int err = 0; - if (!dai->active) - err = omap_mcpdm_request(); + dev_dbg(dai->dev, "%s: active %d\n", __func__, dai->active); + + mutex_lock(&mcpdm->mutex); + + /* make sure we stop any pre-existing shutdown */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + cancel_delayed_work(&mcpdm->delayed_work); + + if (!dai->active && mcpdm->free) { + err = omap_mcpdm_request(mcpdm); + if (err) { + mutex_unlock(&mcpdm->mutex); + return err; + } + omap_mcpdm_set_offset(mcpdm); + } + + mutex_unlock(&mcpdm->mutex); return err; } @@ -98,44 +535,45 @@ static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream, static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { - if (!dai->active) - omap_mcpdm_free(); + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + + dev_dbg(dai->dev, "%s: active %d\n", __func__, dai->active); + + mutex_lock(&mcpdm->mutex); + + if (!dai->active) { + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + omap_mcpdm_capture_close(mcpdm, mcpdm->uplink); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + schedule_delayed_work(&mcpdm->delayed_work, + msecs_to_jiffies(1000)); /* TODO: pdata ? */ + } + + mutex_unlock(&mcpdm->mutex); } -static int omap_mcpdm_dai_trigger(struct snd_pcm_substream *substream, int cmd, - struct snd_soc_dai *dai) +/* work to delay McPDM shutdown */ +static void playback_work(struct work_struct *work) { - struct omap_mcpdm_data *mcpdm_priv = snd_soc_dai_get_drvdata(dai); - int stream = substream->stream; - int err = 0; + struct omap_mcpdm *mcpdm = + container_of(work, struct omap_mcpdm, delayed_work.work); - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - if (!mcpdm_priv->active++) - omap_mcpdm_start(stream); - break; + mutex_lock(&mcpdm->mutex); - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - if (!--mcpdm_priv->active) - omap_mcpdm_stop(stream); - break; - default: - err = -EINVAL; - } + if (!mcpdm->dl_active) + omap_mcpdm_playback_close(mcpdm, mcpdm->downlink); - return err; + if (!mcpdm->free && !mcpdm->dl_active && !mcpdm->ul_active) + omap_mcpdm_free(mcpdm); + + mutex_unlock(&mcpdm->mutex); } static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { - struct omap_mcpdm_data *mcpdm_priv = snd_soc_dai_get_drvdata(dai); - struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links; + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); int stream = substream->stream; int channels, err, link_mask = 0; @@ -165,57 +603,250 @@ static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream, } if (stream == SNDRV_PCM_STREAM_PLAYBACK) { - mcpdm_links[stream].channels = link_mask << 3; - err = omap_mcpdm_playback_open(&mcpdm_links[stream]); + mcpdm->downlink->channels = link_mask << 3; + err = omap_mcpdm_playback_open(mcpdm, &omap_mcpdm_links[0]); } else { - mcpdm_links[stream].channels = link_mask << 0; - err = omap_mcpdm_capture_open(&mcpdm_links[stream]); + mcpdm->uplink->channels = link_mask << 0; + err = omap_mcpdm_capture_open(mcpdm, &omap_mcpdm_links[1]); } return err; } -static int omap_mcpdm_dai_hw_free(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) +static int omap_mcpdm_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) { - struct omap_mcpdm_data *mcpdm_priv = snd_soc_dai_get_drvdata(dai); - struct omap_mcpdm_link *mcpdm_links = mcpdm_priv->links; + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); int stream = substream->stream; - int err; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - err = omap_mcpdm_playback_close(&mcpdm_links[stream]); - else - err = omap_mcpdm_capture_close(&mcpdm_links[stream]); + dev_dbg(dai->dev, "cmd %d\n", cmd); + omap_mcpdm_reg_dump(mcpdm); - return err; + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + omap_mcpdm_start(mcpdm, stream); + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + case SNDRV_PCM_TRIGGER_STOP: + omap_mcpdm_stop(mcpdm, stream); + break; + default: + break; + } + return 0; } static struct snd_soc_dai_ops omap_mcpdm_dai_ops = { .startup = omap_mcpdm_dai_startup, .shutdown = omap_mcpdm_dai_shutdown, - .trigger = omap_mcpdm_dai_trigger, .hw_params = omap_mcpdm_dai_hw_params, - .hw_free = omap_mcpdm_dai_hw_free, + .trigger = omap_mcpdm_dai_trigger, }; -#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) -#define OMAP_MCPDM_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) +#ifdef CONFIG_SND_OMAP_SOC_ABE_DSP +static int omap_mcpdm_abe_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + int ret = 0; + + mutex_lock(&mcpdm->mutex); + + /* make sure we stop any pre-existing shutdown */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + cancel_delayed_work(&mcpdm->delayed_abe_work); + } + + if (!dai->active && mcpdm->free) { + ret = omap_mcpdm_request(mcpdm); + if (ret) { + mutex_unlock(&mcpdm->mutex); + return ret; + } + omap_mcpdm_set_offset(mcpdm); + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcpdm->dl_active++; + else + mcpdm->ul_active++; + + mutex_unlock(&mcpdm->mutex); + + return ret; +} + +static void omap_mcpdm_abe_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + + dev_dbg(dai->dev, "%s: active %d\n", __func__, dai->active); + + mutex_lock(&mcpdm->mutex); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + mcpdm->dl_active--; + else + mcpdm->ul_active--; + + if (!dai->active) { + if (!mcpdm->ul_active && substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + omap_mcpdm_capture_close(mcpdm, mcpdm->uplink); + if (!mcpdm->free && !mcpdm->dn_channels && + !mcpdm->dl_active) + omap_mcpdm_free(mcpdm); + } + if (!mcpdm->dl_active && substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + schedule_delayed_work(&mcpdm->delayed_abe_work, + msecs_to_jiffies(1000)); /* TODO: pdata ? */ + } + + mutex_unlock(&mcpdm->mutex); + +} + +/* work to delay McPDM shutdown */ +static void playback_abe_work(struct work_struct *work) +{ + struct omap_mcpdm *mcpdm = + container_of(work, struct omap_mcpdm, delayed_abe_work.work); + + mutex_lock(&mcpdm->mutex); + if (!mcpdm->dl_active && mcpdm->dn_channels) { + abe_disable_data_transfer(PDM_DL_PORT); + udelay(250); + omap_mcpdm_stop(mcpdm, SNDRV_PCM_STREAM_PLAYBACK); + omap_mcpdm_playback_close(mcpdm, mcpdm->downlink); + abe_dsp_mcpdm_shutdown(); + abe_dsp_pm_put(); + } + mutex_unlock(&mcpdm->mutex); + + if (!mcpdm->free && !mcpdm->ul_active && !mcpdm->dl_active) + omap_mcpdm_free(mcpdm); -static int omap_mcpdm_dai_probe(struct snd_soc_dai *dai) +} + +static int omap_mcpdm_abe_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) { - snd_soc_dai_set_drvdata(dai, &mcpdm_data); + struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); + int stream = substream->stream; + int ret = 0; + + snd_soc_dai_set_dma_data(dai, substream, + &omap_mcpdm_dai_dma_params[stream]); + + mutex_lock(&mcpdm->mutex); + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* Check if McPDM is already started */ + if (!mcpdm->dn_channels) { + abe_dsp_pm_get(); + /* start ATC before McPDM IP */ + abe_enable_data_transfer(PDM_DL_PORT); + udelay(250); + mcpdm->downlink->channels = (PDM_DN_MASK | PDM_CMD_MASK); + ret = omap_mcpdm_playback_open(mcpdm, &omap_mcpdm_links[0]); + if (ret < 0) { + mutex_unlock(&mcpdm->mutex); + return ret; + } + + omap_mcpdm_start(mcpdm, stream); + } + } else { + mcpdm->uplink->channels = PDM_UP1_EN | PDM_UP2_EN; + ret = omap_mcpdm_capture_open(mcpdm, &omap_mcpdm_links[1]); + } + + mutex_unlock(&mcpdm->mutex); + + return ret; +} + + +static int omap_mcpdm_abe_dai_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + omap_mcpdm_dai_trigger(substream, cmd, dai); + } + return 0; } -static struct snd_soc_dai_driver omap_mcpdm_dai = { - .probe = omap_mcpdm_dai_probe, +static struct snd_soc_dai_ops omap_mcpdm_abe_dai_ops = { + .startup = omap_mcpdm_abe_dai_startup, + .shutdown = omap_mcpdm_abe_dai_shutdown, + .hw_params = omap_mcpdm_abe_dai_hw_params, + .trigger = omap_mcpdm_abe_dai_trigger, +}; +#endif + +#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) +#define OMAP_MCPDM_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver omap_mcpdm_dai[] = { +#ifdef CONFIG_SND_OMAP_SOC_ABE_DSP +{ + .name = "mcpdm-dl1", + .playback = { + .channels_min = 1, + .channels_max = 2, + .rates = OMAP_MCPDM_RATES, + .formats = OMAP_MCPDM_FORMATS, + }, + .ops = &omap_mcpdm_abe_dai_ops, +}, +{ + .name = "mcpdm-dl2", + .playback = { + .channels_min = 1, + .channels_max = 2, + .rates = OMAP_MCPDM_RATES, + .formats = OMAP_MCPDM_FORMATS, + }, + .ops = &omap_mcpdm_abe_dai_ops, +}, +{ + .name = "mcpdm-vib", + .playback = { + .channels_min = 1, + .channels_max = 2, + .rates = OMAP_MCPDM_RATES, + .formats = OMAP_MCPDM_FORMATS, + }, + .ops = &omap_mcpdm_abe_dai_ops, +}, +{ + .name = "mcpdm-ul1", + .capture = { + .channels_min = 1, + .channels_max = 2, + .rates = OMAP_MCPDM_RATES, + .formats = OMAP_MCPDM_FORMATS, + }, + .ops = &omap_mcpdm_abe_dai_ops, +}, +#endif +{ + .name = "mcpdm-dl", .playback = { .channels_min = 1, .channels_max = 4, .rates = OMAP_MCPDM_RATES, .formats = OMAP_MCPDM_FORMATS, }, + .ops = &omap_mcpdm_dai_ops, +}, +{ + .name = "mcpdm-ul", .capture = { .channels_min = 1, .channels_max = 2, @@ -223,25 +854,88 @@ static struct snd_soc_dai_driver omap_mcpdm_dai = { .formats = OMAP_MCPDM_FORMATS, }, .ops = &omap_mcpdm_dai_ops, -}; +}, }; static __devinit int asoc_mcpdm_probe(struct platform_device *pdev) { - int ret; + struct omap_mcpdm *mcpdm; + struct resource *res; + int ret = 0; + + mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL); + if (!mcpdm) + return -ENOMEM; + + platform_set_drvdata(pdev, mcpdm); + mcpdm->downlink = &omap_mcpdm_links[0]; + mcpdm->uplink = &omap_mcpdm_links[1]; + + mutex_init(&mcpdm->mutex); + mcpdm->free = 1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no resource\n"); + ret = -EINVAL; + goto err; + } - ret = omap_mcpdm_probe(pdev); - if (ret < 0) - return ret; - ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai); + mcpdm->io_base = ioremap(res->start, resource_size(res)); + if (!mcpdm->io_base) { + ret = -ENOMEM; + goto err; + } + + mcpdm->irq = platform_get_irq(pdev, 0); + if (mcpdm->irq < 0) { + ret = mcpdm->irq; + goto err_irq; + } + + ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, + 0, "McPDM", mcpdm); + if (ret) { + dev_err(mcpdm->dev, "Request for McPDM IRQ failed: %d\n", ret); + goto err_irq; + } + + pm_runtime_enable(&pdev->dev); + + mcpdm->dev = &pdev->dev; + + /* TODO: values will be different per device, read from FS */ + mcpdm->dl1_offset = 0x1F; + mcpdm->dl2_offset = 0x1F; + + INIT_DELAYED_WORK(&mcpdm->delayed_work, playback_work); +#ifdef CONFIG_SND_OMAP_SOC_ABE_DSP + INIT_DELAYED_WORK(&mcpdm->delayed_abe_work, playback_abe_work); +#endif + + ret = snd_soc_register_dais(&pdev->dev, omap_mcpdm_dai, + ARRAY_SIZE(omap_mcpdm_dai)); if (ret < 0) - omap_mcpdm_remove(pdev); + goto err_dai; + + return 0; + +err_dai: + free_irq(mcpdm->irq, mcpdm); +err_irq: + iounmap(mcpdm->io_base); +err: + kfree(mcpdm); return ret; } static int __devexit asoc_mcpdm_remove(struct platform_device *pdev) { - snd_soc_unregister_dai(&pdev->dev); - omap_mcpdm_remove(pdev); + struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev); + + snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(omap_mcpdm_dai)); + iounmap(mcpdm->io_base); + free_irq(mcpdm->irq, mcpdm); + kfree(mcpdm); return 0; } diff --git a/sound/soc/omap/omap-mcpdm.h b/sound/soc/omap/omap-mcpdm.h new file mode 100644 index 00000000000..2c69956e99e --- /dev/null +++ b/sound/soc/omap/omap-mcpdm.h @@ -0,0 +1,131 @@ +/* + * omap-mcpdm.h + * + * Copyright (C) 2009 Texas Instruments + * + * Contact: Misael Lopez Cruz <x0052729@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __OMAP_MCPDM_H__ +#define __OMAP_MCPDM_H__ + +#include <linux/platform_device.h> + +#define MCPDM_REVISION 0x00 +#define MCPDM_SYSCONFIG 0x10 +#define MCPDM_IRQSTATUS_RAW 0x24 +#define MCPDM_IRQSTATUS 0x28 +#define MCPDM_IRQENABLE_SET 0x2C +#define MCPDM_IRQENABLE_CLR 0x30 +#define MCPDM_IRQWAKE_EN 0x34 +#define MCPDM_DMAENABLE_SET 0x38 +#define MCPDM_DMAENABLE_CLR 0x3C +#define MCPDM_DMAWAKEEN 0x40 +#define MCPDM_CTRL 0x44 +#define MCPDM_DN_DATA 0x48 +#define MCPDM_UP_DATA 0x4C +#define MCPDM_FIFO_CTRL_DN 0x50 +#define MCPDM_FIFO_CTRL_UP 0x54 +#define MCPDM_DN_OFFSET 0x58 + +/* + * MCPDM_IRQ bit fields + * IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR + */ + +#define MCPDM_DN_IRQ (1 << 0) +#define MCPDM_DN_IRQ_EMPTY (1 << 1) +#define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2) +#define MCPDM_DN_IRQ_FULL (1 << 3) + +#define MCPDM_UP_IRQ (1 << 8) +#define MCPDM_UP_IRQ_EMPTY (1 << 9) +#define MCPDM_UP_IRQ_ALMST_FULL (1 << 10) +#define MCPDM_UP_IRQ_FULL (1 << 11) + +#define MCPDM_DOWNLINK_IRQ_MASK 0x00F +#define MCPDM_UPLINK_IRQ_MASK 0xF00 + +/* + * MCPDM_DMAENABLE bit fields + */ + +#define DMA_DN_ENABLE 0x1 +#define DMA_UP_ENABLE 0x2 + +/* + * MCPDM_SYSCONFIG bit fields + */ +#define MCPDM_SOFTRESET 0x1 + +/* + * MCPDM_CTRL bit fields + */ + +#define PDM_UP1_EN 0x0001 +#define PDM_UP2_EN 0x0002 +#define PDM_UP3_EN 0x0004 +#define PDM_DN1_EN 0x0008 +#define PDM_DN2_EN 0x0010 +#define PDM_DN3_EN 0x0020 +#define PDM_DN4_EN 0x0040 +#define PDM_DN5_EN 0x0080 +#define PDMOUTFORMAT 0x0100 +#define CMD_INT 0x0200 +#define STATUS_INT 0x0400 +#define SW_UP_RST 0x0800 +#define SW_DN_RST 0x1000 +#define WD_EN 0x4000 +#define PDM_UP_MASK 0x007 +#define PDM_DN_MASK 0x0F8 +#define PDM_CMD_MASK 0x200 +#define PDM_STATUS_MASK 0x400 + + +#define PDMOUTFORMAT_LJUST (0 << 8) +#define PDMOUTFORMAT_RJUST (1 << 8) + +/* + * MCPDM_FIFO_CTRL bit fields + */ + +#define UP_THRES_MAX 0xF +#define DN_THRES_MAX 0xF + +/* + * MCPDM_DN_OFFSET bit fields + */ + +#define DN_OFST_RX1_EN 0x0001 +#define DN_OFST_RX2_EN 0x0100 + +#define DN_OFST_RX1 1 +#define DN_OFST_RX2 9 +#define DN_OFST_MAX 0x1F + +#define MCPDM_UPLINK 1 +#define MCPDM_DOWNLINK 2 + +struct omap_mcpdm_link { + int irq_mask; + int threshold; + int format; + int channels; +}; + +#endif /* End of __OMAP_MCPDM_H__ */ diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c index 8caeb8d305c..6ca5d611224 100644 --- a/sound/soc/omap/omap-pcm.c +++ b/sound/soc/omap/omap-pcm.c @@ -280,6 +280,16 @@ static int omap_pcm_open(struct snd_pcm_substream *substream) if (ret < 0) goto out; + if (cpu_is_omap44xx()) { + /* ABE needs a step of 24 * 4 data bits, and HDMI 32 * 4 + * Ensure buffer size satisfies both constraints. + */ + ret = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 384); + if (ret < 0) + goto out; + } + prtd = kzalloc(sizeof(*prtd), GFP_KERNEL); if (prtd == NULL) { ret = -ENOMEM; @@ -365,9 +375,10 @@ static void omap_pcm_free_dma_buffers(struct snd_pcm *pcm) } } -static int omap_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int omap_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) @@ -375,14 +386,14 @@ static int omap_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, if (!card->dev->coherent_dma_mask) card->dev->coherent_dma_mask = DMA_BIT_MASK(64); - if (dai->driver->playback.channels_min) { + if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { ret = omap_pcm_preallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK); if (ret) goto out; } - if (dai->driver->capture.channels_min) { + if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { ret = omap_pcm_preallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE); if (ret) diff --git a/sound/soc/omap/omap4-hdmi-card.c b/sound/soc/omap/omap4-hdmi-card.c new file mode 100644 index 00000000000..28644e1a37f --- /dev/null +++ b/sound/soc/omap/omap4-hdmi-card.c @@ -0,0 +1,89 @@ +/* + * sdp4430-hdmi.c + * + * OMAP ALSA SoC machine driver for TI OMAP4 HDMI + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Ricardo Neri <ricardo.neri@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include <sound/pcm.h> +#include <sound/soc.h> +#include <asm/mach-types.h> + +#define OMAP4_HDMI_SND_DEV_ID 1 + +static struct snd_soc_dai_link omap4_hdmi_dai = { + .name = "HDMI", + .stream_name = "HDMI", + .cpu_dai_name = "hdmi-audio-dai", + .platform_name = "omap-pcm-audio", + .codec_name = "omapdss_hdmi", + .codec_dai_name = "omap4-hdmi-audio-codec" +}; + +/* Audio machine driver */ +static struct snd_soc_card snd_soc_omap4_hdmi = { + .name = "SDP4430HDMI", + .long_name = "TI OMAP4 HDMI Board", + .dai_link = &omap4_hdmi_dai, + .num_links = 1, +}; + +static struct platform_device *omap4_hdmi_snd_device; + +static int __init omap4_hdmi_soc_init(void) +{ + int ret; + + if (!(machine_is_omap_4430sdp() || machine_is_omap4_panda())) + return -ENODEV; + printk(KERN_INFO "OMAP4 HDMI audio SoC init\n"); + + if (machine_is_omap4_panda()) + snd_soc_omap4_hdmi.name = "PandaHDMI"; + + omap4_hdmi_snd_device = platform_device_alloc("soc-audio", + OMAP4_HDMI_SND_DEV_ID); + if (!omap4_hdmi_snd_device) { + printk(KERN_ERR "Platform device allocation failed\n"); + return -ENOMEM; + } + + platform_set_drvdata(omap4_hdmi_snd_device, &snd_soc_omap4_hdmi); + + ret = platform_device_add(omap4_hdmi_snd_device); + if (ret) + goto err; + + return 0; +err: + printk(KERN_ERR "Unable to add platform device\n"); + platform_device_put(omap4_hdmi_snd_device); + return ret; +} +module_init(omap4_hdmi_soc_init); + +static void __exit omap4_hdmi_soc_exit(void) +{ + platform_device_unregister(omap4_hdmi_snd_device); +} +module_exit(omap4_hdmi_soc_exit); + +MODULE_AUTHOR("Ricardo Neri <ricardo.neri@ti.com>"); +MODULE_DESCRIPTION("ALSA SoC OMAP4 HDMI AUDIO"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/sdp4430.c b/sound/soc/omap/sdp4430.c index 189e0390063..d9a43867f7a 100644 --- a/sound/soc/omap/sdp4430.c +++ b/sound/soc/omap/sdp4430.c @@ -22,7 +22,9 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <sound/core.h> +#include <linux/i2c.h> #include <sound/pcm.h> +#include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/jack.h> @@ -30,19 +32,92 @@ #include <plat/hardware.h> #include <plat/mux.h> -#include "mcpdm.h" +#include "omap-mcpdm.h" +#include "omap-abe.h" #include "omap-pcm.h" +#include "omap-mcbsp.h" +#include "omap-dmic.h" #include "../codecs/twl6040.h" +#define SDP4430_SND_DEV_ID 0 + +#ifdef CONFIG_SND_OMAP_SOC_HDMI +#include "omap-hdmi.h" +#endif + static int twl6040_power_mode; +static int mcbsp_cfg; + +static struct i2c_client *tps6130x_client; +static struct i2c_board_info tps6130x_hwmon_info = { + I2C_BOARD_INFO("tps6130x", 0x33), +}; + +/* configure the TPS6130x Handsfree Boost Converter */ +static int sdp4430_tps6130x_configure(void) +{ + u8 data[2]; + + data[0] = 0x01; + data[1] = 0x60; + if (i2c_master_send(tps6130x_client, data, 2) != 2) + printk(KERN_ERR "I2C write to TPS6130x failed\n"); -static int sdp4430_hw_params(struct snd_pcm_substream *substream, + data[0] = 0x02; + if (i2c_master_send(tps6130x_client, data, 2) != 2) + printk(KERN_ERR "I2C write to TPS6130x failed\n"); + + return 0; +} + +static int sdp4430_modem_mcbsp_configure(struct snd_pcm_substream *substream, + int flag) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_pcm_substream *modem_substream; + struct snd_soc_pcm_runtime *modem_rtd; + int ret = 0; + + /* already configured, nothing to do */ + if (mcbsp_cfg == flag) + return ret; + + if (flag) { + modem_substream = snd_soc_get_dai_substream(rtd->card, + OMAP_ABE_BE_MM_EXT1, + substream->stream); + if (unlikely(modem_substream == NULL)) { + ret = -ENODEV; + goto exit; + } + + modem_rtd = modem_substream->private_data; + + /* Set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(modem_rtd->cpu_dai, + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + if (unlikely(ret < 0)) { + printk(KERN_ERR "can't set Modem cpu DAI configuration\n"); + goto exit; + } + mcbsp_cfg = 1; + } else { + mcbsp_cfg = 0; + } + +exit: + return ret; +} + +static int sdp4430_mcpdm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; int clk_id, freq; - int ret; + int ret = 0; if (twl6040_power_mode) { clk_id = TWL6040_SYSCLK_SEL_HPPLL; @@ -59,13 +134,155 @@ static int sdp4430_hw_params(struct snd_pcm_substream *substream, printk(KERN_ERR "can't set codec system clock\n"); return ret; } + + if (rtd->current_fe == ABE_FRONTEND_DAI_MODEM) { + /* set Modem McBSP configuration */ + ret = sdp4430_modem_mcbsp_configure(substream, 1); + } + return ret; } -static struct snd_soc_ops sdp4430_ops = { - .hw_params = sdp4430_hw_params, +static int sdp4430_mcpdm_hw_free(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + if (rtd->current_fe == ABE_FRONTEND_DAI_MODEM) { + /* freed Modem McBSP configuration */ + ret = sdp4430_modem_mcbsp_configure(substream, 0); + } + + return ret; +} + +static struct snd_soc_ops sdp4430_mcpdm_ops = { + .hw_params = sdp4430_mcpdm_hw_params, + .hw_free = sdp4430_mcpdm_hw_free, }; +static int sdp4430_mcbsp_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + unsigned int be_id; + + be_id = rtd->dai_link->be_id; + + if (be_id == OMAP_ABE_DAI_MM_FM) { + /* Set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + } else if (be_id == OMAP_ABE_DAI_BT_VX) { + ret = snd_soc_dai_set_fmt(cpu_dai, + SND_SOC_DAIFMT_DSP_B | + SND_SOC_DAIFMT_NB_IF | + SND_SOC_DAIFMT_CBM_CFM); + } + + if (ret < 0) { + printk(KERN_ERR "can't set cpu DAI configuration\n"); + return ret; + } + + /* + * TODO: where does this clock come from (external source??) - + * do we need to enable it. + */ + /* Set McBSP clock to external */ + ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_FCLK, + 64 * params_rate(params), + SND_SOC_CLOCK_IN); + if (ret < 0) { + printk(KERN_ERR "can't set cpu system clock\n"); + return ret; + } + return 0; +} + +static struct snd_soc_ops sdp4430_mcbsp_ops = { + .hw_params = sdp4430_mcbsp_hw_params, +}; + +static int sdp4430_dmic_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + + ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_DMIC_SYSCLK_PAD_CLKS, + 19200000, SND_SOC_CLOCK_IN); + if (ret < 0) { + printk(KERN_ERR "can't set DMIC cpu system clock\n"); + return ret; + } + + ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_DMIC_CLKDIV, 8); + if (ret < 0) { + printk(KERN_ERR "can't set DMIC cpu clock divider\n"); + return ret; + } + + if (rtd->current_fe == ABE_FRONTEND_DAI_MODEM) { + /* set Modem McBSP configuration */ + ret = sdp4430_modem_mcbsp_configure(substream, 1); + } + + return ret; +} + +static int sdp4430_dmic_hw_free(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + if (rtd->current_fe == ABE_FRONTEND_DAI_MODEM) { + /* freed Modem McBSP configuration */ + ret = sdp4430_modem_mcbsp_configure(substream, 0); + } + + return ret; +} + +static struct snd_soc_ops sdp4430_dmic_ops = { + .hw_params = sdp4430_dmic_hw_params, + .hw_free = sdp4430_dmic_hw_free, +}; + +static int mcbsp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + unsigned int be_id; + + be_id = rtd->dai_link->be_id; + + if (be_id == OMAP_ABE_DAI_MM_FM) + channels->min = 2; + else if (be_id == OMAP_ABE_DAI_BT_VX) + channels->min = 1; + + snd_mask_set(¶ms->masks[SNDRV_PCM_HW_PARAM_FORMAT - + SNDRV_PCM_HW_PARAM_FIRST_MASK], + SNDRV_PCM_FORMAT_S16_LE); + return 0; +} + +static int dmic_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + snd_mask_set(¶ms->masks[SNDRV_PCM_HW_PARAM_FORMAT - + SNDRV_PCM_HW_PARAM_FIRST_MASK], + SNDRV_PCM_FORMAT_S32_LE); + return 0; +} + /* Headset jack */ static struct snd_soc_jack hs_jack; @@ -113,6 +330,9 @@ static const struct snd_kcontrol_new sdp4430_controls[] = { /* SDP4430 machine DAPM */ static const struct snd_soc_dapm_widget sdp4430_twl6040_dapm_widgets[] = { SND_SOC_DAPM_MIC("Ext Mic", NULL), + SND_SOC_DAPM_MIC("Ext DMic0", NULL), + SND_SOC_DAPM_MIC("Ext DMic1", NULL), + SND_SOC_DAPM_MIC("Ext DMic2", NULL), SND_SOC_DAPM_SPK("Ext Spk", NULL), SND_SOC_DAPM_MIC("Headset Mic", NULL), SND_SOC_DAPM_HP("Headset Stereophone", NULL), @@ -121,11 +341,20 @@ static const struct snd_soc_dapm_widget sdp4430_twl6040_dapm_widgets[] = { }; static const struct snd_soc_dapm_route audio_map[] = { - /* External Mics: MAINMIC, SUBMIC with bias*/ + /* External Mics: MAINMIC, SUBMIC and DMICs with bias */ {"MAINMIC", NULL, "Main Mic Bias"}, {"SUBMIC", NULL, "Main Mic Bias"}, {"Main Mic Bias", NULL, "Ext Mic"}, + {"DMIC0", NULL, "Digital Mic1 Bias"}, + {"Digital Mic1 Bias", NULL, "Ext DMic0"}, + + {"DMIC1", NULL, "Digital Mic1 Bias"}, + {"Digital Mic1 Bias", NULL, "Ext DMic1"}, + + {"DMIC2", NULL, "Digital Mic1 Bias"}, + {"Digital Mic1 Bias", NULL, "Ext DMic2"}, + /* External Speakers: HFL, HFR */ {"Ext Spk", NULL, "HFL"}, {"Ext Spk", NULL, "HFR"}, @@ -146,7 +375,7 @@ static const struct snd_soc_dapm_route audio_map[] = { {"AFMR", NULL, "Aux/FM Stereo In"}, }; -static int sdp4430_twl6040_init(struct snd_soc_pcm_runtime *rtd) +static int sdp4430_twl6040_init_hs(struct snd_soc_pcm_runtime *rtd) { struct snd_soc_codec *codec = rtd->codec; struct snd_soc_dapm_context *dapm = &codec->dapm; @@ -169,11 +398,25 @@ static int sdp4430_twl6040_init(struct snd_soc_pcm_runtime *rtd) /* SDP4430 connected pins */ snd_soc_dapm_enable_pin(dapm, "Ext Mic"); + snd_soc_dapm_enable_pin(dapm, "Ext DMic0"); + snd_soc_dapm_enable_pin(dapm, "Ext DMic1"); + snd_soc_dapm_enable_pin(dapm, "Ext DMic2"); snd_soc_dapm_enable_pin(dapm, "Ext Spk"); snd_soc_dapm_enable_pin(dapm, "AFML"); snd_soc_dapm_enable_pin(dapm, "AFMR"); - snd_soc_dapm_enable_pin(dapm, "Headset Mic"); - snd_soc_dapm_enable_pin(dapm, "Headset Stereophone"); + snd_soc_dapm_disable_pin(dapm, "Headset Mic"); + snd_soc_dapm_disable_pin(dapm, "Headset Stereophone"); + + /* allow modem audio paths to run during suspend */ + snd_soc_dapm_ignore_suspend(dapm, "Ext Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Ext DMic0"); + snd_soc_dapm_ignore_suspend(dapm, "Ext DMic1"); + snd_soc_dapm_ignore_suspend(dapm, "Ext DMic2"); + snd_soc_dapm_ignore_suspend(dapm, "Ext Spk"); + snd_soc_dapm_ignore_suspend(dapm, "AFML"); + snd_soc_dapm_ignore_suspend(dapm, "AFMR"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Stereophone"); ret = snd_soc_dapm_sync(dapm); if (ret) @@ -193,52 +436,517 @@ static int sdp4430_twl6040_init(struct snd_soc_pcm_runtime *rtd) else snd_soc_jack_report(&hs_jack, SND_JACK_HEADSET, SND_JACK_HEADSET); + /* wait 500 ms before switching of HS power */ + rtd->pmdown_time = 500; + return ret; } +static int sdp4430_twl6040_init_hf(struct snd_soc_pcm_runtime *rtd) +{ + /* wait 500 ms before switching of HS power */ + rtd->pmdown_time = 500; + return 0; +} + +/* TODO: make this a separate BT CODEC driver or DUMMY */ +static struct snd_soc_dai_driver dai[] = { +{ + .name = "Bluetooth", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, +}, +/* TODO: make this a separate FM CODEC driver or DUMMY */ +{ + .name = "FM Digital", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, +}, +{ + .name = "HDMI", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, + }, +}, +}; + +static const char *mm1_be[] = { + OMAP_ABE_BE_PDM_DL1, + OMAP_ABE_BE_PDM_UL1, + OMAP_ABE_BE_PDM_DL2, + OMAP_ABE_BE_BT_VX, + OMAP_ABE_BE_MM_EXT0, + OMAP_ABE_BE_DMIC0, + OMAP_ABE_BE_DMIC1, + OMAP_ABE_BE_DMIC2, +}; + +static const char *mm2_be[] = { + OMAP_ABE_BE_PDM_UL1, + OMAP_ABE_BE_BT_VX, + OMAP_ABE_BE_MM_EXT0, + OMAP_ABE_BE_DMIC0, + OMAP_ABE_BE_DMIC1, + OMAP_ABE_BE_DMIC2, +}; + +static const char *tones_be[] = { + OMAP_ABE_BE_PDM_DL1, + OMAP_ABE_BE_PDM_DL2, + OMAP_ABE_BE_BT_VX, + OMAP_ABE_BE_MM_EXT0, +}; + +static const char *vib_be[] = { + OMAP_ABE_BE_PDM_VIB, +}; + +static const char *modem_be[] = { + OMAP_ABE_BE_PDM_DL1, + OMAP_ABE_BE_PDM_UL1, + OMAP_ABE_BE_PDM_DL2, + OMAP_ABE_BE_BT_VX, + OMAP_ABE_BE_DMIC0, + OMAP_ABE_BE_DMIC1, + OMAP_ABE_BE_DMIC2, +}; + +static const char *mm_lp_be[] = { + OMAP_ABE_BE_PDM_DL1, + OMAP_ABE_BE_PDM_DL2, + OMAP_ABE_BE_BT_VX, + OMAP_ABE_BE_MM_EXT0, +}; + /* Digital audio interface glue - connects codec <--> CPU */ -static struct snd_soc_dai_link sdp4430_dai = { - .name = "TWL6040", - .stream_name = "TWL6040", - .cpu_dai_name ="omap-mcpdm-dai", - .codec_dai_name = "twl6040-hifi", - .platform_name = "omap-pcm-audio", - .codec_name = "twl6040-codec", - .init = sdp4430_twl6040_init, - .ops = &sdp4430_ops, +static struct snd_soc_dai_link sdp4430_dai[] = { + +/* + * Frontend DAIs - i.e. userspace visible interfaces (ALSA PCMs) + */ + + { + .name = "SDP4430 Media", + .stream_name = "Multimedia", + + /* ABE components - MM-UL & MM_DL */ + .cpu_dai_name = "MultiMedia1", + .platform_name = "omap-pcm-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = mm1_be, + .num_be = ARRAY_SIZE(mm1_be), + .fe_playback_channels = 2, + .fe_capture_channels = 8, + .no_host_mode = SND_SOC_DAI_LINK_OPT_HOST, + }, + { + .name = "SDP4430 Media Capture", + .stream_name = "Multimedia Capture", + + /* ABE components - MM-UL2 */ + .cpu_dai_name = "MultiMedia2", + .platform_name = "omap-pcm-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = mm2_be, + .num_be = ARRAY_SIZE(mm2_be), + .fe_capture_channels = 2, + }, + { + .name = "SDP4430 Voice", + .stream_name = "Voice", + + /* ABE components - VX-UL & VX-DL */ + .cpu_dai_name = "Voice", + .platform_name = "omap-pcm-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = mm1_be, + .num_be = ARRAY_SIZE(mm1_be), + .fe_playback_channels = 2, + .fe_capture_channels = 2, + .no_host_mode = SND_SOC_DAI_LINK_OPT_HOST, + }, + { + .name = "SDP4430 Tones Playback", + .stream_name = "Tone Playback", + + /* ABE components - TONES_DL */ + .cpu_dai_name = "Tones", + .platform_name = "omap-pcm-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = tones_be, + .num_be = ARRAY_SIZE(tones_be), + .fe_playback_channels = 2, + }, + { + .name = "SDP4430 Vibra Playback", + .stream_name = "VIB-DL", + + .cpu_dai_name = "Vibra", + .platform_name = "omap-pcm-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = vib_be, + .num_be = ARRAY_SIZE(vib_be), + .fe_playback_channels = 2, + }, + { + .name = "SDP4430 MODEM", + .stream_name = "MODEM", + + /* ABE components - MODEM <-> McBSP2 */ + .cpu_dai_name = "MODEM", + .platform_name = "omap-aess-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = modem_be, + .num_be = ARRAY_SIZE(modem_be), + .fe_playback_channels = 2, + .fe_capture_channels = 2, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + }, + { + .name = "SDP4430 Media LP", + .stream_name = "Multimedia", + + /* ABE components - MM-DL (mmap) */ + .cpu_dai_name = "MultiMedia1 LP", + .platform_name = "omap-aess-audio", + + .dynamic = 1, /* BE is dynamic */ + .supported_be = mm_lp_be, + .num_be = ARRAY_SIZE(mm_lp_be), + .fe_playback_channels = 2, + .no_host_mode = SND_SOC_DAI_LINK_OPT_HOST, + }, +#ifdef CONFIG_SND_OMAP_SOC_HDMI + { + .name = "hdmi", + .stream_name = "HDMI", + + .cpu_dai_name = "hdmi-dai", + .platform_name = "omap-pcm-audio", + + /* HDMI*/ + .codec_dai_name = "HDMI", + + .no_codec = 1, + }, +#endif + { + .name = "Legacy McBSP", + .stream_name = "Multimedia", + + /* ABE components - MCBSP2 - MM-EXT */ + .cpu_dai_name = "omap-mcbsp-dai.1", + .platform_name = "omap-pcm-audio", + + /* FM */ + .codec_dai_name = "FM Digital", + + .no_codec = 1, /* TODO: have a dummy CODEC */ + .ops = &sdp4430_mcbsp_ops, + }, + { + .name = "Legacy McPDM", + .stream_name = "Headset Playback", + + /* ABE components - DL1 */ + .cpu_dai_name = "mcpdm-dl", + .platform_name = "omap-pcm-audio", + + /* Phoenix - DL1 DAC */ + .codec_dai_name = "twl6040-dl1", + .codec_name = "twl6040-codec", + + .ops = &sdp4430_mcpdm_ops, + .ignore_suspend = 1, + }, + { + .name = "Legacy DMIC", + .stream_name = "DMIC Capture", + + /* ABE components - DMIC0 */ + .cpu_dai_name = "omap-dmic-dai-0", + .platform_name = "omap-pcm-audio", + + /* DMIC codec */ + .codec_dai_name = "dmic-hifi", + .codec_name = "dmic-codec.0", + + .ops = &sdp4430_dmic_ops, + .ignore_suspend = 1, + }, + +/* + * Backend DAIs - i.e. dynamically matched interfaces, invisible to userspace. + * Matched to above interfaces at runtime, based upon use case. + */ + + { + .name = OMAP_ABE_BE_PDM_DL1, + .stream_name = "HS Playback", + + /* ABE components - DL1 */ + .cpu_dai_name = "mcpdm-dl1", + .platform_name = "omap-aess-audio", + + /* Phoenix - DL1 DAC */ + .codec_dai_name = "twl6040-dl1", + .codec_name = "twl6040-codec", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .init = sdp4430_twl6040_init_hs, + .ops = &sdp4430_mcpdm_ops, + .be_id = OMAP_ABE_DAI_PDM_DL1, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_PDM_UL1, + .stream_name = "Analog Capture", + + /* ABE components - UL1 */ + .cpu_dai_name = "mcpdm-ul1", + .platform_name = "omap-aess-audio", + + /* Phoenix - UL ADC */ + .codec_dai_name = "twl6040-ul", + .codec_name = "twl6040-codec", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .ops = &sdp4430_mcpdm_ops, + .be_id = OMAP_ABE_DAI_PDM_UL, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_PDM_DL2, + .stream_name = "HF Playback", + + /* ABE components - DL2 */ + .cpu_dai_name = "mcpdm-dl2", + .platform_name = "omap-aess-audio", + + /* Phoenix - DL2 DAC */ + .codec_dai_name = "twl6040-dl2", + .codec_name = "twl6040-codec", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .init = sdp4430_twl6040_init_hf, + .ops = &sdp4430_mcpdm_ops, + .be_id = OMAP_ABE_DAI_PDM_DL2, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_PDM_VIB, + .stream_name = "Vibra", + + /* ABE components - VIB1 DL */ + .cpu_dai_name = "mcpdm-vib", + .platform_name = "omap-aess-audio", + + /* Phoenix - PDM to PWM */ + .codec_dai_name = "twl6040-vib", + .codec_name = "twl6040-codec", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .ops = &sdp4430_mcpdm_ops, + .be_id = OMAP_ABE_DAI_PDM_VIB, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_BT_VX, + .stream_name = "BT", + + /* ABE components - MCBSP1 - BT-VX */ + .cpu_dai_name = "omap-mcbsp-dai.0", + .platform_name = "omap-aess-audio", + + /* Bluetooth */ + .codec_dai_name = "Bluetooth", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .no_codec = 1, /* TODO: have a dummy CODEC */ + .be_hw_params_fixup = mcbsp_be_hw_params_fixup, + .ops = &sdp4430_mcbsp_ops, + .be_id = OMAP_ABE_DAI_BT_VX, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_MM_EXT0, + .stream_name = "FM", + + /* ABE components - MCBSP2 - MM-EXT */ + .cpu_dai_name = "omap-mcbsp-dai.1", + .platform_name = "omap-aess-audio", + + /* FM */ + .codec_dai_name = "FM Digital", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .no_codec = 1, /* TODO: have a dummy CODEC */ + .be_hw_params_fixup = mcbsp_be_hw_params_fixup, + .ops = &sdp4430_mcbsp_ops, + .be_id = OMAP_ABE_DAI_MM_FM, + }, + { + .name = OMAP_ABE_BE_MM_EXT1, + .stream_name = "MODEM", + + /* ABE components - MCBSP2 - MM-EXT */ + .cpu_dai_name = "omap-mcbsp-dai.1", + .platform_name = "omap-aess-audio", + + /* MODEM */ + .codec_dai_name = "MODEM", + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .no_codec = 1, /* TODO: have a dummy CODEC */ + .be_hw_params_fixup = mcbsp_be_hw_params_fixup, + .ops = &sdp4430_mcbsp_ops, + .be_id = OMAP_ABE_DAI_MODEM, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_DMIC0, + .stream_name = "DMIC0", + + /* ABE components - DMIC UL 1 */ + .cpu_dai_name = "omap-dmic-abe-dai-0", + .platform_name = "omap-aess-audio", + + /* DMIC 0 */ + .codec_dai_name = "dmic-hifi", + .codec_name = "dmic-codec.0", + .ops = &sdp4430_dmic_ops, + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .be_hw_params_fixup = dmic_be_hw_params_fixup, + .be_id = OMAP_ABE_DAI_DMIC0, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_DMIC1, + .stream_name = "DMIC1", + + /* ABE components - DMIC UL 1 */ + .cpu_dai_name = "omap-dmic-abe-dai-1", + .platform_name = "omap-aess-audio", + + /* DMIC 1 */ + .codec_dai_name = "dmic-hifi", + .codec_name = "dmic-codec.1", + .ops = &sdp4430_dmic_ops, + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .be_hw_params_fixup = dmic_be_hw_params_fixup, + .be_id = OMAP_ABE_DAI_DMIC1, + .ignore_suspend = 1, + }, + { + .name = OMAP_ABE_BE_DMIC2, + .stream_name = "DMIC2", + + /* ABE components - DMIC UL 2 */ + .cpu_dai_name = "omap-dmic-abe-dai-2", + .platform_name = "omap-aess-audio", + + /* DMIC 2 */ + .codec_dai_name = "dmic-hifi", + .codec_name = "dmic-codec.2", + .ops = &sdp4430_dmic_ops, + + .no_pcm = 1, /* don't create ALSA pcm for this */ + .be_hw_params_fixup = dmic_be_hw_params_fixup, + .be_id = OMAP_ABE_DAI_DMIC2, + .ignore_suspend = 1, + }, }; /* Audio machine driver */ static struct snd_soc_card snd_soc_sdp4430 = { .name = "SDP4430", - .dai_link = &sdp4430_dai, - .num_links = 1, + .long_name = "TI OMAP4 SDP4430 Board", + .dai_link = sdp4430_dai, + .num_links = ARRAY_SIZE(sdp4430_dai), }; static struct platform_device *sdp4430_snd_device; static int __init sdp4430_soc_init(void) { + struct i2c_adapter *adapter; int ret; - if (!machine_is_omap_4430sdp()) + if (!machine_is_omap_4430sdp() && !machine_is_omap4_panda()) { + pr_debug("Not SDP4430 or PandaBoard!\n"); return -ENODEV; + } printk(KERN_INFO "SDP4430 SoC init\n"); - sdp4430_snd_device = platform_device_alloc("soc-audio", -1); + sdp4430_snd_device = platform_device_alloc("soc-audio", + SDP4430_SND_DEV_ID); if (!sdp4430_snd_device) { printk(KERN_ERR "Platform device allocation failed\n"); return -ENOMEM; } + snd_soc_register_dais(&sdp4430_snd_device->dev, dai, ARRAY_SIZE(dai)); + platform_set_drvdata(sdp4430_snd_device, &snd_soc_sdp4430); ret = platform_device_add(sdp4430_snd_device); if (ret) goto err; - /* Codec starts in HP mode */ - twl6040_power_mode = 1; + adapter = i2c_get_adapter(1); + if (!adapter) { + printk(KERN_ERR "can't get i2c adapter\n"); + return -ENODEV; + } + + tps6130x_client = i2c_new_device(adapter, &tps6130x_hwmon_info); + if (!tps6130x_client) { + printk(KERN_ERR "can't add i2c device\n"); + return -ENODEV; + } + + /* Only configure the TPS6130x on SDP4430 */ + if (machine_is_omap_4430sdp()) + sdp4430_tps6130x_configure(); return 0; @@ -252,6 +960,7 @@ module_init(sdp4430_soc_init); static void __exit sdp4430_soc_exit(void) { platform_device_unregister(sdp4430_snd_device); + i2c_unregister_device(tps6130x_client); } module_exit(sdp4430_soc_exit); diff --git a/sound/soc/pxa/pxa2xx-pcm.c b/sound/soc/pxa/pxa2xx-pcm.c index 02fb66416dd..7c13674110c 100644 --- a/sound/soc/pxa/pxa2xx-pcm.c +++ b/sound/soc/pxa/pxa2xx-pcm.c @@ -84,9 +84,10 @@ static struct snd_pcm_ops pxa2xx_pcm_ops = { static u64 pxa2xx_pcm_dmamask = DMA_BIT_MASK(32); -static int pxa2xx_soc_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int pxa2xx_soc_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; int ret = 0; if (!card->dev->dma_mask) diff --git a/sound/soc/s6000/s6000-pcm.c b/sound/soc/s6000/s6000-pcm.c index ab3ccaec72d..dc6c641ddd4 100644 --- a/sound/soc/s6000/s6000-pcm.c +++ b/sound/soc/s6000/s6000-pcm.c @@ -443,9 +443,10 @@ static void s6000_pcm_free(struct snd_pcm *pcm) static u64 s6000_pcm_dmamask = DMA_BIT_MASK(32); -static int s6000_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, struct snd_pcm *pcm) +static int s6000_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; struct snd_soc_pcm_runtime *runtime = pcm->private_data; struct s6000_pcm_dma_params *params; int res; diff --git a/sound/soc/sh/dma-sh7760.c b/sound/soc/sh/dma-sh7760.c index c326d29992f..f26d238d40e 100644 --- a/sound/soc/sh/dma-sh7760.c +++ b/sound/soc/sh/dma-sh7760.c @@ -327,10 +327,11 @@ static void camelot_pcm_free(struct snd_pcm *pcm) snd_pcm_lib_preallocate_free_for_all(pcm); } -static int camelot_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int camelot_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; + /* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel * in MMAP mode (i.e. aplay -M) */ diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c index 2b06402801e..c3362d9d3c6 100644 --- a/sound/soc/sh/fsi.c +++ b/sound/soc/sh/fsi.c @@ -1060,10 +1060,10 @@ static void fsi_pcm_free(struct snd_pcm *pcm) snd_pcm_lib_preallocate_free_for_all(pcm); } -static int fsi_pcm_new(struct snd_card *card, - struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; /* * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel * in MMAP mode (i.e. aplay -M) diff --git a/sound/soc/sh/siu_pcm.c b/sound/soc/sh/siu_pcm.c index a423babcf14..5a428dab2d5 100644 --- a/sound/soc/sh/siu_pcm.c +++ b/sound/soc/sh/siu_pcm.c @@ -527,9 +527,10 @@ static snd_pcm_uframes_t siu_pcm_pointer_dma(struct snd_pcm_substream *ss) return bytes_to_frames(ss->runtime, ptr); } -static int siu_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int siu_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; /* card->dev == socdev->dev, see snd_soc_new_pcms() */ struct siu_info *info = siu_i2s_data; struct platform_device *pdev = to_platform_device(card->dev); diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index c3f6f1e7279..0224b0cda3a 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -44,7 +44,6 @@ #define NAME_SIZE 32 -static DEFINE_MUTEX(pcm_mutex); static DECLARE_WAIT_QUEUE_HEAD(soc_pm_waitq); #ifdef CONFIG_DEBUG_FS @@ -70,6 +69,24 @@ static int pmdown_time = 5000; module_param(pmdown_time, int, 0); MODULE_PARM_DESC(pmdown_time, "DAPM stream powerdown time (msecs)"); +/* ASoC no host IO hardware. + * TODO: fine tune these values for all host less transfers. + */ +static const struct snd_pcm_hardware no_host_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .period_bytes_min = PAGE_SIZE >> 2, + .period_bytes_max = PAGE_SIZE >> 1, + .periods_min = 2, + .periods_max = 4, + .buffer_bytes_max = PAGE_SIZE, +}; + /* codec register dump */ static ssize_t soc_codec_reg_show(struct snd_soc_codec *codec, char *buf) { @@ -454,12 +471,116 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream) return 0; } +static int is_be_supported(struct snd_soc_pcm_runtime *rtd, const char *link) +{ + int i; + + for (i= 0; i < rtd->dai_link->num_be; i++) { + if(!strcmp(rtd->dai_link->supported_be[i], link)) + return 1; + } + return 0; +} + +int snd_soc_get_backend_dais(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_card *card = rtd->card; + int i, num; + const char *fe_aif = NULL, *be_aif; + enum snd_soc_dapm_type fe_type, be_type; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + fe_type = snd_soc_dapm_aif_in; + be_type = snd_soc_dapm_aif_out; + } else { + fe_type = snd_soc_dapm_aif_out; + be_type = snd_soc_dapm_aif_in; + } + + /* search card for valid frontend steams */ + for (i = 0; i < card->num_links; i++) { + + /* check for frontend */ + if (card->rtd[i].dai_link->dynamic) + continue; + + fe_aif = snd_soc_dapm_get_aif(&card->rtd[i].platform->dapm, + cpu_dai->driver->name, fe_type); + } + + if (fe_aif == NULL) { + dev_err(&rtd->dev, "no frontend widgets for stream %s\n", + cpu_dai->driver->name); + return 0; + } else + dev_dbg(&rtd->dev, "got fe %s\n", fe_aif); + + /* search card for valid backends */ + for (i = 0; i < card->num_links; i++) { + + /* check for frontend */ + if (card->rtd[i].dai_link->dynamic) + continue; + + /* backends must belong to this frontend */ + if (card->rtd[i].dai_link->no_pcm) { + + if (!is_be_supported(rtd, card->rtd[i].dai_link->name)) + continue; + + be_aif = snd_soc_dapm_get_aif(&card->rtd[i].platform->dapm, + card->rtd[i].dai_link->stream_name, be_type); + if (be_aif == NULL) { + dev_dbg(&rtd->dev, "no backend widget for stream %s\n", + card->rtd[i].dai_link->stream_name); + continue; + } + dev_dbg(&rtd->dev, "got be %s for stream %s\n", be_aif, + card->rtd[i].dai_link->stream_name); + + /* check for valid path */ + num = snd_soc_scenario_set_path(&card->rtd[i].platform->dapm, + fe_aif, be_aif, substream->stream); + + /* add backend if we have space */ + if (num > 0) { + if (rtd->num_be[substream->stream] == SND_SOC_MAX_BE) + dev_dbg(&rtd->dev, "no more backends permitted\n"); + else { + dev_dbg(&rtd->dev, "** active path for %s to %s\n", fe_aif, be_aif); + rtd->be_rtd[rtd->num_be[substream->stream]++][substream->stream] = &card->rtd[i]; + card->rtd[i].fe_clients++; + } + } + } + } + + return rtd->num_be[substream->stream] ? rtd->num_be[substream->stream] : -EINVAL; +} +EXPORT_SYMBOL_GPL(snd_soc_get_backend_dais); + +void snd_soc_put_backend_dais(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int i; + + for (i = 0; i < rtd->num_be[substream->stream]; i++) { + rtd->be_rtd[i][substream->stream]->fe_clients--; + rtd->be_rtd[i][substream->stream] = NULL; + } + rtd->num_be[substream->stream] = 0; +} +EXPORT_SYMBOL_GPL(snd_soc_put_backend_dais); + /* * Called by ALSA when a PCM substream is opened, the runtime->hw record is * then initialized and any private data can be allocated. This also calls * startup for the cpu DAI, platform, machine and codec DAI. */ -static int soc_pcm_open(struct snd_pcm_substream *substream) + +int snd_soc_pcm_open(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_pcm_runtime *runtime = substream->runtime; @@ -470,7 +591,33 @@ static int soc_pcm_open(struct snd_pcm_substream *substream) struct snd_soc_dai_driver *codec_dai_drv = codec_dai->driver; int ret = 0; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); + + /* Work out backend DAI's if we are a frontend */ + if (rtd->dai_link->dynamic) { + ret = snd_soc_get_backend_dais(substream); + if (ret < 0) { + printk(KERN_ERR "asoc: no valid backend routes for PCM: %s\n", + dev_name(&rtd->dev)); + goto out; + } + } + + /* Are we the backend and already enabled */ + if (rtd->dai_link->no_pcm) { + + if (rtd->fe_clients == 0) { + dev_err(&rtd->dev, "operations not permitted on backend DAI\n"); + ret = -ENODEV; + goto out; + } + + if (rtd->be_active++) + goto no_pcm; + } + + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) + snd_soc_set_runtime_hwparams(substream, &no_host_hardware); /* startup the audio subsystem */ if (cpu_dai->driver->ops->startup) { @@ -507,6 +654,9 @@ static int soc_pcm_open(struct snd_pcm_substream *substream) } } + if (rtd->dai_link->no_pcm) + goto no_pcm; + /* Check that the codec and cpu DAIs are compatible */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { runtime->hw.rate_min = @@ -587,7 +737,7 @@ static int soc_pcm_open(struct snd_pcm_substream *substream) runtime->hw.channels_max); pr_debug("asoc: min rate %d max rate %d\n", runtime->hw.rate_min, runtime->hw.rate_max); - +no_pcm: if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { cpu_dai->playback_active++; codec_dai->playback_active++; @@ -598,7 +748,9 @@ static int soc_pcm_open(struct snd_pcm_substream *substream) cpu_dai->active++; codec_dai->active++; rtd->codec->active++; - mutex_unlock(&pcm_mutex); + + mutex_unlock(&rtd->pcm_mutex); + return 0; config_err: @@ -617,9 +769,14 @@ platform_err: if (cpu_dai->driver->ops->shutdown) cpu_dai->driver->ops->shutdown(substream, cpu_dai); out: - mutex_unlock(&pcm_mutex); + if (rtd->dai_link->dynamic) + snd_soc_put_backend_dais(substream); + + mutex_unlock(&rtd->pcm_mutex); + return ret; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_open); /* * Power down the audio subsystem pmdown_time msecs after close is called. @@ -631,8 +788,9 @@ static void close_delayed_work(struct work_struct *work) struct snd_soc_pcm_runtime *rtd = container_of(work, struct snd_soc_pcm_runtime, delayed_work.work); struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); pr_debug("pop wq checking: %s status: %s waiting: %s\n", codec_dai->driver->playback.stream_name, @@ -642,12 +800,17 @@ static void close_delayed_work(struct work_struct *work) /* are we waiting on this codec DAI stream */ if (codec_dai->pop_wait == 1) { codec_dai->pop_wait = 0; - snd_soc_dapm_stream_event(rtd, - codec_dai->driver->playback.stream_name, - SND_SOC_DAPM_STREAM_STOP); + if (rtd->dai_link->dynamic) + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK, + cpu_dai->driver->playback.stream_name, + SND_SOC_DAPM_STREAM_STOP); + else + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK, + codec_dai->driver->playback.stream_name, + SND_SOC_DAPM_STREAM_STOP); } - mutex_unlock(&pcm_mutex); + mutex_unlock(&rtd->pcm_mutex); } /* @@ -655,7 +818,7 @@ static void close_delayed_work(struct work_struct *work) * freed here. The cpu DAI, codec DAI, machine and platform are also * shutdown. */ -static int soc_codec_close(struct snd_pcm_substream *substream) +int snd_soc_pcm_close(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_platform *platform = rtd->platform; @@ -663,7 +826,7 @@ static int soc_codec_close(struct snd_pcm_substream *substream) struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_codec *codec = rtd->codec; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { cpu_dai->playback_active--; @@ -677,6 +840,9 @@ static int soc_codec_close(struct snd_pcm_substream *substream) codec_dai->active--; codec->active--; + if (rtd->dai_link->no_pcm) + rtd->be_active--; + /* Muting the DAC suppresses artifacts caused during digital * shutdown, for example from stopping clocks. */ @@ -703,21 +869,30 @@ static int soc_codec_close(struct snd_pcm_substream *substream) msecs_to_jiffies(rtd->pmdown_time)); } else { /* capture streams can be powered down now */ - snd_soc_dapm_stream_event(rtd, - codec_dai->driver->capture.stream_name, - SND_SOC_DAPM_STREAM_STOP); + if (rtd->dai_link->dynamic) + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE, + cpu_dai->driver->capture.stream_name, + SND_SOC_DAPM_STREAM_STOP); + else + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE, + codec_dai->driver->capture.stream_name, + SND_SOC_DAPM_STREAM_STOP); } - mutex_unlock(&pcm_mutex); + if (rtd->dai_link->dynamic) + snd_soc_put_backend_dais(substream); + + mutex_unlock(&rtd->pcm_mutex); return 0; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_close); /* * Called by ALSA when the PCM substream is prepared, can set format, sample * rate, etc. This function is non atomic and can be called multiple times, * it can refer to the runtime info. */ -static int soc_pcm_prepare(struct snd_pcm_substream *substream) +int snd_soc_pcm_prepare(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_platform *platform = rtd->platform; @@ -725,7 +900,7 @@ static int soc_pcm_prepare(struct snd_pcm_substream *substream) struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret = 0; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); if (rtd->dai_link->ops && rtd->dai_link->ops->prepare) { ret = rtd->dai_link->ops->prepare(substream); @@ -766,28 +941,39 @@ static int soc_pcm_prepare(struct snd_pcm_substream *substream) cancel_delayed_work(&rtd->delayed_work); } - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - snd_soc_dapm_stream_event(rtd, + if (rtd->dai_link->dynamic) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK, + cpu_dai->driver->playback.stream_name, + SND_SOC_DAPM_STREAM_START); + else + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE, + cpu_dai->driver->capture.stream_name, + SND_SOC_DAPM_STREAM_START); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_PLAYBACK, codec_dai->driver->playback.stream_name, SND_SOC_DAPM_STREAM_START); - else - snd_soc_dapm_stream_event(rtd, + else + snd_soc_dapm_stream_event(rtd, SNDRV_PCM_STREAM_CAPTURE, codec_dai->driver->capture.stream_name, SND_SOC_DAPM_STREAM_START); - + } snd_soc_dai_digital_mute(codec_dai, 0); out: - mutex_unlock(&pcm_mutex); + mutex_unlock(&rtd->pcm_mutex); return ret; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_prepare); /* * Called by ALSA when the hardware params are set by application. This * function can also be called multiple times and can allocate buffers * (using snd_pcm_lib_* ). It's non-atomic. */ -static int soc_pcm_hw_params(struct snd_pcm_substream *substream, +int snd_soc_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; @@ -796,7 +982,7 @@ static int soc_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret = 0; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); if (rtd->dai_link->ops && rtd->dai_link->ops->hw_params) { ret = rtd->dai_link->ops->hw_params(substream, params); @@ -835,8 +1021,21 @@ static int soc_pcm_hw_params(struct snd_pcm_substream *substream, rtd->rate = params_rate(params); + /* malloc a page for hostless IO. + * FIXME: rework with alsa-lib changes so that this malloc is not required. + */ + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) { + substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV; + substream->dma_buffer.dev.dev = &rtd->dev; + substream->dma_buffer.private_data = NULL; + + ret = snd_pcm_lib_malloc_pages(substream, PAGE_SIZE); + if (ret < 0) + goto platform_err; + } + out: - mutex_unlock(&pcm_mutex); + mutex_unlock(&rtd->pcm_mutex); return ret; platform_err: @@ -851,14 +1050,15 @@ codec_err: if (rtd->dai_link->ops && rtd->dai_link->ops->hw_free) rtd->dai_link->ops->hw_free(substream); - mutex_unlock(&pcm_mutex); + mutex_unlock(&rtd->pcm_mutex);; return ret; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_hw_params); /* * Frees resources allocated by hw_params, can be called multiple times */ -static int soc_pcm_hw_free(struct snd_pcm_substream *substream) +int snd_soc_pcm_hw_free(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_platform *platform = rtd->platform; @@ -866,7 +1066,7 @@ static int soc_pcm_hw_free(struct snd_pcm_substream *substream) struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_codec *codec = rtd->codec; - mutex_lock(&pcm_mutex); + mutex_lock(&rtd->pcm_mutex); /* apply codec digital mute */ if (!codec->active) @@ -887,11 +1087,15 @@ static int soc_pcm_hw_free(struct snd_pcm_substream *substream) if (cpu_dai->driver->ops->hw_free) cpu_dai->driver->ops->hw_free(substream, cpu_dai); - mutex_unlock(&pcm_mutex); + if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) + snd_pcm_lib_free_pages(substream); + + mutex_unlock(&rtd->pcm_mutex); return 0; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_hw_free); -static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +int snd_soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_platform *platform = rtd->platform; @@ -918,13 +1122,14 @@ static int soc_pcm_trigger(struct snd_pcm_substream *substream, int cmd) } return 0; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_trigger); /* * soc level wrapper for pointer callback * If cpu_dai, codec_dai, platform driver has the delay callback, than * the runtime->delay will be updated accordingly. */ -static snd_pcm_uframes_t soc_pcm_pointer(struct snd_pcm_substream *substream) +snd_pcm_uframes_t snd_soc_pcm_pointer(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_platform *platform = rtd->platform; @@ -950,17 +1155,48 @@ static snd_pcm_uframes_t soc_pcm_pointer(struct snd_pcm_substream *substream) return offset; } +EXPORT_SYMBOL_GPL(snd_soc_pcm_pointer); -/* ASoC PCM operations */ -static struct snd_pcm_ops soc_pcm_ops = { - .open = soc_pcm_open, - .close = soc_codec_close, - .hw_params = soc_pcm_hw_params, - .hw_free = soc_pcm_hw_free, - .prepare = soc_pcm_prepare, - .trigger = soc_pcm_trigger, - .pointer = soc_pcm_pointer, -}; + +int snd_soc_pcm_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_platform *platform = rtd->platform; + + if (platform->driver->ops->ioctl) + return platform->driver->ops->ioctl(substream, cmd, arg); + return snd_pcm_lib_ioctl(substream, cmd, arg); +} + +struct snd_pcm_substream *snd_soc_get_dai_substream(struct snd_soc_card *card, + const char *dai_link, int stream) +{ + int i; + + for (i = 0; i < card->num_links; i++) { + if (card->rtd[i].dai_link->no_pcm && + !strcmp(card->rtd[i].dai_link->name, dai_link)) + return card->rtd[i].pcm->streams[stream].substream; + } + dev_dbg(card->dev, "failed to find dai link %s\n", dai_link); + return NULL; +} +EXPORT_SYMBOL_GPL(snd_soc_get_dai_substream); + +struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card, + const char *dai_link) +{ + int i; + + for (i = 0; i < card->num_links; i++) { + if (!strcmp(card->rtd[i].dai_link->name, dai_link)) + return &card->rtd[i]; + } + dev_dbg(card->dev, "failed to find rtd %s\n", dai_link); + return NULL; +} +EXPORT_SYMBOL_GPL(snd_soc_get_pcm_runtime); #ifdef CONFIG_PM /* powers down audio subsystem for suspend */ @@ -1038,12 +1274,12 @@ static int soc_suspend(struct device *dev) continue; if (driver->playback.stream_name != NULL) - snd_soc_dapm_stream_event(&card->rtd[i], driver->playback.stream_name, - SND_SOC_DAPM_STREAM_SUSPEND); + snd_soc_dapm_stream_event(&card->rtd[i], SNDRV_PCM_STREAM_PLAYBACK, + driver->playback.stream_name, SND_SOC_DAPM_STREAM_SUSPEND); if (driver->capture.stream_name != NULL) - snd_soc_dapm_stream_event(&card->rtd[i], driver->capture.stream_name, - SND_SOC_DAPM_STREAM_SUSPEND); + snd_soc_dapm_stream_event(&card->rtd[i], SNDRV_PCM_STREAM_CAPTURE, + driver->capture.stream_name, SND_SOC_DAPM_STREAM_SUSPEND); } /* suspend all CODECs */ @@ -1140,12 +1376,12 @@ static void soc_resume_deferred(struct work_struct *work) continue; if (driver->playback.stream_name != NULL) - snd_soc_dapm_stream_event(&card->rtd[i], driver->playback.stream_name, - SND_SOC_DAPM_STREAM_RESUME); + snd_soc_dapm_stream_event(&card->rtd[i], SNDRV_PCM_STREAM_PLAYBACK, + driver->playback.stream_name, SND_SOC_DAPM_STREAM_RESUME); if (driver->capture.stream_name != NULL) - snd_soc_dapm_stream_event(&card->rtd[i], driver->capture.stream_name, - SND_SOC_DAPM_STREAM_RESUME); + snd_soc_dapm_stream_event(&card->rtd[i], SNDRV_PCM_STREAM_CAPTURE, + driver->capture.stream_name, SND_SOC_DAPM_STREAM_RESUME); } /* unmute any active DACs */ @@ -1201,12 +1437,12 @@ static int soc_resume(struct device *dev) if (cpu_dai->driver->ac97_control) { dev_dbg(dev, "Resuming AC97 immediately\n"); soc_resume_deferred(&card->deferred_resume_work); - } else { - dev_dbg(dev, "Scheduling resume work\n"); - if (!schedule_work(&card->deferred_resume_work)) - dev_err(dev, "resume work item may be lost\n"); + return 0; } } + dev_dbg(dev, "Scheduling resume work\n"); + if (!schedule_work(&card->deferred_resume_work)) + dev_err(dev, "resume work item may be lost\n"); return 0; } @@ -1215,9 +1451,32 @@ static int soc_resume(struct device *dev) #define soc_resume NULL #endif +#define NULL_FORMATS \ + (SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_U16 |\ + SNDRV_PCM_FMTBIT_S24 | SNDRV_PCM_FMTBIT_U24 |\ + SNDRV_PCM_FMTBIT_S32 | SNDRV_PCM_FMTBIT_U32) + static struct snd_soc_dai_ops null_dai_ops = { }; +static struct snd_soc_dai_driver null_codec_dai_drv = { + .name = "null-codec-dai", + .ops = &null_dai_ops, + .capture = { + .channels_min = 1 , + .channels_max = 16, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .formats = NULL_FORMATS, + }, + .playback = { + .channels_min = 1 , + .channels_max = 16, + .rates = SNDRV_PCM_RATE_CONTINUOUS, + .formats = NULL_FORMATS, + }, +}; +static struct snd_soc_codec_driver null_codec_drv = {}; + static int soc_bind_dai_link(struct snd_soc_card *card, int num) { struct snd_soc_dai_link *dai_link = &card->dai_link[num]; @@ -1261,7 +1520,7 @@ find_codec: /* CODEC found, so find CODEC DAI from registered DAIs from this CODEC*/ list_for_each_entry(codec_dai, &dai_list, list) { - if (codec->dev == codec_dai->dev && + if ((codec->dev == codec_dai->dev || codec->driver == &null_codec_drv) && !strcmp(codec_dai->name, dai_link->codec_dai_name)) { rtd->codec_dai = codec_dai; goto find_platform; @@ -1357,6 +1616,10 @@ static void soc_remove_dai_link(struct snd_soc_card *card, int num) if (err < 0) printk(KERN_ERR "asoc: failed to remove %s\n", platform->name); } + + /* Make sure all DAPM widgets are freed */ + snd_soc_dapm_free(&platform->dapm); + platform->probed = 0; list_del(&platform->card_list); module_put(platform->dev->driver->owner); @@ -1512,9 +1775,14 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) /* config components */ codec_dai->codec = codec; + platform->card = card; cpu_dai->platform = platform; codec_dai->card = card; cpu_dai->card = card; + codec->card = card; + platform->dapm.card = card; + rtd->card = card; + rtd->dev.parent = card->dev; /* set default power off timeout */ rtd->pmdown_time = pmdown_time; @@ -1529,6 +1797,9 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) return ret; } } + /* Make sure all DAPM widgets are instantiated */ + snd_soc_dapm_new_widgets(&platform->dapm); + cpu_dai->probed = 1; /* mark cpu_dai as probed and add to card cpu_dai list */ list_add(&cpu_dai->card_list, &card->dai_dev_list); @@ -1558,6 +1829,7 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) platform->probed = 1; list_add(&platform->card_list, &card->platform_dev_list); + INIT_LIST_HEAD(&platform->dapm.list); } /* probe the CODEC DAI */ @@ -1578,6 +1850,7 @@ static int soc_probe_dai_link(struct snd_soc_card *card, int num) /* DAPM dai link stream work */ INIT_DELAYED_WORK(&rtd->delayed_work, close_delayed_work); + mutex_init(&rtd->pcm_mutex); ret = soc_post_component_init(card, codec, num, 0); if (ret) @@ -1811,8 +2084,10 @@ static void snd_soc_instantiate_card(struct snd_soc_card *card) } snprintf(card->snd_card->shortname, sizeof(card->snd_card->shortname), - "%s", card->name); + "%s", card->name); snprintf(card->snd_card->longname, sizeof(card->snd_card->longname), + "%s", card->long_name); + snprintf(card->snd_card->driver, sizeof(card->snd_card->driver), "%s", card->name); ret = snd_card_register(card->snd_card); @@ -1972,6 +2247,7 @@ static int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num) struct snd_soc_platform *platform = rtd->platform; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_pcm_substream *substream[2]; struct snd_pcm *pcm; char new_name[64]; int ret = 0, playback = 0, capture = 0; @@ -1980,10 +2256,17 @@ static int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num) snprintf(new_name, sizeof(new_name), "%s %s-%d", rtd->dai_link->stream_name, codec_dai->name, num); - if (codec_dai->driver->playback.channels_min) - playback = 1; - if (codec_dai->driver->capture.channels_min) - capture = 1; + if (rtd->dai_link->dynamic) { + if (rtd->dai_link->fe_playback_channels) + playback = 1; + if (rtd->dai_link->fe_capture_channels) + capture = 1; + } else { + if (codec_dai->driver->playback.channels_min) + playback = 1; + if (codec_dai->driver->capture.channels_min) + capture = 1; + } dev_dbg(rtd->card->dev, "registered pcm #%d %s\n",num,new_name); ret = snd_pcm_new(rtd->card->snd_card, new_name, @@ -1995,26 +2278,64 @@ static int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num) rtd->pcm = pcm; pcm->private_data = rtd; - soc_pcm_ops.mmap = platform->driver->ops->mmap; - soc_pcm_ops.pointer = platform->driver->ops->pointer; - soc_pcm_ops.ioctl = platform->driver->ops->ioctl; - soc_pcm_ops.copy = platform->driver->ops->copy; - soc_pcm_ops.silence = platform->driver->ops->silence; - soc_pcm_ops.ack = platform->driver->ops->ack; - soc_pcm_ops.page = platform->driver->ops->page; + substream[SNDRV_PCM_STREAM_PLAYBACK] = + pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + substream[SNDRV_PCM_STREAM_CAPTURE] = + pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; + + if (rtd->dai_link->no_pcm) { + if (playback) + substream[SNDRV_PCM_STREAM_PLAYBACK]->private_data = rtd; + if (capture) + substream[SNDRV_PCM_STREAM_CAPTURE]->private_data = rtd; + goto out; + } + + /* setup any hostless PCMs - i.e. no host IO is performed */ + if (rtd->dai_link->no_host_mode) { + if (substream[SNDRV_PCM_STREAM_PLAYBACK]) { + substream[SNDRV_PCM_STREAM_PLAYBACK]->hw_no_buffer = 1; + snd_soc_set_runtime_hwparams(substream[SNDRV_PCM_STREAM_PLAYBACK], + &no_host_hardware); + } + if (substream[SNDRV_PCM_STREAM_CAPTURE]) { + substream[SNDRV_PCM_STREAM_CAPTURE]->hw_no_buffer = 1; + snd_soc_set_runtime_hwparams(substream[SNDRV_PCM_STREAM_CAPTURE], + &no_host_hardware); + } + } + + /* ASoC PCM operations */ + rtd->ops.open = snd_soc_pcm_open; + rtd->ops.hw_params = snd_soc_pcm_hw_params; + rtd->ops.prepare = snd_soc_pcm_prepare; + rtd->ops.trigger = snd_soc_pcm_trigger; + rtd->ops.hw_free = snd_soc_pcm_hw_free; + rtd->ops.close = snd_soc_pcm_close; + rtd->ops.pointer = snd_soc_pcm_pointer; + rtd->ops.ioctl = snd_soc_pcm_ioctl; + rtd->ops.ack = platform->driver->ops->ack; + rtd->ops.copy = platform->driver->ops->copy; + rtd->ops.silence = platform->driver->ops->silence; + rtd->ops.page = platform->driver->ops->page; + rtd->ops.mmap = platform->driver->ops->mmap; if (playback) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &soc_pcm_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &rtd->ops); if (capture) - snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &soc_pcm_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &rtd->ops); - ret = platform->driver->pcm_new(rtd->card->snd_card, codec_dai, pcm); + if (!platform->driver->pcm_new) + goto out; + ret = platform->driver->pcm_new(rtd); if (ret < 0) { printk(KERN_ERR "asoc: platform pcm constructor failed\n"); return ret; } +out: + pcm->private_free = platform->driver->pcm_free; printk(KERN_INFO "asoc: %s <-> %s mapping ok\n", codec_dai->name, cpu_dai->name); @@ -2209,6 +2530,10 @@ int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream, const struct snd_pcm_hardware *hw) { struct snd_pcm_runtime *runtime = substream->runtime; + + if (!runtime) + return 0; + runtime->hw.info = hw->info; runtime->hw.formats = hw->formats; runtime->hw.period_bytes_min = hw->period_bytes_min; @@ -2285,6 +2610,35 @@ int snd_soc_add_controls(struct snd_soc_codec *codec, EXPORT_SYMBOL_GPL(snd_soc_add_controls); /** + * snd_soc_add_platform_controls - add an array of controls to a platform. + * Convienience function to add a list of controls. + * + * @platform: platform to add controls to + * @controls: array of controls to add + * @num_controls: number of elements in the array + * + * Return 0 for success, else error. + */ +int snd_soc_add_platform_controls(struct snd_soc_platform *platform, + const struct snd_kcontrol_new *controls, int num_controls) +{ + struct snd_card *card = platform->card->snd_card; + int err, i; + + for (i = 0; i < num_controls; i++) { + const struct snd_kcontrol_new *control = &controls[i]; + err = snd_ctl_add(card, snd_soc_cnew(control, platform, NULL)); + if (err < 0) { + dev_err(platform->dev, "Failed to add %s %d\n", control->name, err); + return err; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(snd_soc_add_platform_controls); + +/** * snd_soc_info_enum_double - enumerated double mixer info callback * @kcontrol: mixer control * @uinfo: control element information @@ -3107,7 +3461,7 @@ EXPORT_SYMBOL_GPL(snd_soc_dai_digital_mute); */ static int snd_soc_register_card(struct snd_soc_card *card) { - int i; + int i, ret = 0; if (!card->name || !card->dev) return -EINVAL; @@ -3119,12 +3473,41 @@ static int snd_soc_register_card(struct snd_soc_card *card) return -ENOMEM; card->rtd_aux = &card->rtd[card->num_links]; - for (i = 0; i < card->num_links; i++) + for (i = 0; i < card->num_links; i++) { + /* create virtual CODEC for dynamic links */ + dev_dbg(card->dev, "DAI create runtime %s\n", card->dai_link[i].name); card->rtd[i].dai_link = &card->dai_link[i]; + if (card->rtd[i].dai_link->dynamic) { + + card->rtd[i].dai_link->codec_name = "null-codec"; + card->rtd[i].dai_link->codec_dai_name = "null-codec-dai"; + ret = snd_soc_register_codec(card->dev, &null_codec_drv, + &null_codec_dai_drv, 1); + if (ret < 0) { + printk(KERN_ERR "%s: failed to register dynamic DAI link %d\n", + __func__, ret); + goto out; + } + continue; + } + if (card->rtd[i].dai_link->no_codec) { + card->rtd[i].dai_link->codec_name = "null-codec"; + + ret = snd_soc_register_codec(card->dev, &null_codec_drv, + &null_codec_dai_drv, 1); + if (ret < 0) { + printk(KERN_ERR "%s: failed to register dynamic DAI link %d\n", + __func__, ret); + goto out; + } + continue; + } + } INIT_LIST_HEAD(&card->list); card->instantiated = 0; mutex_init(&card->mutex); + mutex_init(&card->dapm_mutex); mutex_lock(&client_mutex); list_add(&card->list, &card_list); @@ -3132,8 +3515,8 @@ static int snd_soc_register_card(struct snd_soc_card *card) mutex_unlock(&client_mutex); dev_dbg(card->dev, "Registered card '%s'\n", card->name); - - return 0; +out: + return ret; } /** @@ -3376,6 +3759,10 @@ int snd_soc_register_platform(struct device *dev, return -ENOMEM; } + platform->dapm.bias_level = SND_SOC_BIAS_OFF; + platform->dapm.dev = dev; + platform->dapm.platform = platform; + platform->dapm.stream_event = platform_drv->stream_event; platform->dev = dev; platform->driver = platform_drv; @@ -3470,7 +3857,11 @@ int snd_soc_register_codec(struct device *dev, return -ENOMEM; /* create CODEC component name */ - codec->name = fmt_single_name(dev, &codec->id); + if (codec_drv == &null_codec_drv) + codec->name = kstrdup("null-codec", GFP_KERNEL); + else + codec->name = fmt_single_name(dev, &codec->id); + if (codec->name == NULL) { kfree(codec); return -ENOMEM; @@ -3489,6 +3880,7 @@ int snd_soc_register_codec(struct device *dev, codec->dev = dev; codec->driver = codec_drv; codec->num_dai = num_dai; + codec->dapm.stream_event = codec_drv->stream_event; mutex_init(&codec->mutex); /* allocate CODEC register cache */ diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index 1790f83ee66..4f69ef40f07 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -47,6 +47,8 @@ #include <trace/events/asoc.h> +static inline void dapm_clear_walk(struct snd_soc_dapm_context *dapm); + /* dapm power sequences - make this per codec in the future */ static int dapm_up_seq[] = { [snd_soc_dapm_pre] = 0, @@ -123,6 +125,243 @@ static inline struct snd_soc_dapm_widget *dapm_cnew_widget( return kmemdup(_widget, sizeof(*_widget), GFP_KERNEL); } +static int soc_widget_read(struct snd_soc_dapm_widget *w, int reg) +{ + if (w->codec) + return snd_soc_read(w->codec, reg); + else if (w->platform) + return snd_soc_platform_read(w->platform, reg); + return 0; +} + +static int soc_widget_write(struct snd_soc_dapm_widget *w, int reg, int val) +{ + if (w->codec) + return snd_soc_write(w->codec, reg, val); + else if (w->platform) + return snd_soc_platform_write(w->platform, reg, val); + return 0; +} + +int soc_widget_update_bits(struct snd_soc_dapm_widget *w, unsigned short reg, + unsigned int mask, unsigned int value) +{ + int change; + unsigned int old, new; + + old = soc_widget_read(w, reg); + new = (old & ~mask) | value; + change = old != new; +// if (change) + soc_widget_write(w, reg, new); + + return change; +} + +int soc_widget_test_bits(struct snd_soc_dapm_widget *w, unsigned short reg, + unsigned int mask, unsigned int value) +{ + int change; + unsigned int old, new; + + old = soc_widget_read(w, reg); + new = (old & ~mask) | value; + change = old != new; + + return change; +} + +#define MAX_HOPS 16 + +static void scenario_clear_paths(struct snd_soc_dapm_context *dapm) +{ + struct snd_soc_dapm_path *p; + struct snd_soc_dapm_widget *w; + struct list_head *l; + + list_for_each(l, &dapm->card->paths) { + p = list_entry(l, struct snd_soc_dapm_path, list); + p->length = 0; + } + list_for_each(l, &dapm->card->widgets) { + w = list_entry(l, struct snd_soc_dapm_widget, list); + w->hops = 0; + } + dapm_clear_walk(dapm); +} + +/* + * find all the paths between source and sink + */ +static int scenario_find_playback_paths(struct snd_soc_dapm_context *dapm, + struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink, + int hops) +{ + struct list_head *lp; + struct snd_soc_dapm_path *path; + int dist = 0; + + if (hops > MAX_HOPS) + return 0; + + if (source == sink) { + dev_dbg(dapm->dev,"** found route with length %d\n", hops); + dapm->num_valid_paths++; + return 1; + } + + if (source->hops && source->hops <= hops) + return 0; + source->hops = hops; + + /* + * check all the output paths on this source widget + * by walking from source to sink + */ + list_for_each(lp, &source->sinks) { + path = list_entry(lp, struct snd_soc_dapm_path, list_source); + + dev_dbg(dapm->dev,"%d:try source %s path %s to %s len %d connect %d\n", + hops, source->name, path->name, path->sink->name, + path->length, path->connect); + + /* been here before ? */ + if (path->length && path->length <= hops) + continue; + + /* check down the next path if connected */ + if (path->sink && path->connect && + scenario_find_playback_paths(dapm, path->sink, sink, hops + 1)) { + path->length = hops; + if (!dist || dist > path->length) + dist = path->length; + } + } + + return dist; +} + +static int scenario_find_capture_paths (struct snd_soc_dapm_context *dapm, + struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink, + int hops) +{ + struct list_head *lp; + struct snd_soc_dapm_path *path; + int dist = 0; + + if (hops > MAX_HOPS) + return 0; + + if (source == sink) { + dev_dbg(dapm->dev,"** found route with length %d\n", hops); + dapm->num_valid_paths++; + return 1; + } + + if (sink->hops && sink->hops <= hops) + return 0; + sink->hops = hops; + + /* + * check all the output paths on this source widget + * by walking from sink to source + */ + list_for_each(lp, &sink->sources) { + path = list_entry(lp, struct snd_soc_dapm_path, list_sink); + + dev_dbg(dapm->dev,"%d:try sink %s path %s to %s len %d connect %d\n", + hops, sink->name, path->name, path->source->name, + path->length, path->connect); + + /* been here before ? */ + if (path->length && path->length <= hops) + continue; + + /* check down the next path if connected */ + if (path->source && path->connect && + scenario_find_capture_paths(dapm, source, path->source, hops + 1)) { + path->length = hops; + if (!dist || dist > path->length) + dist = path->length; + } + } + + return dist; +} + +/* + * traverse the tree from sink to source via the shortest path + */ +static int scenario_get_playback_paths(struct snd_soc_dapm_context *dapm, + struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink) +{ + dapm->num_valid_paths = 0; + + dev_dbg(dapm->dev, "check playback path from %s to %s\n", + source->name, sink->name); + scenario_find_playback_paths(dapm, source, sink, 1); + return dapm->num_valid_paths; +} + +static int scenario_get_capture_paths(struct snd_soc_dapm_context *dapm, + struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink) +{ + dapm->num_valid_paths = 0; + dev_dbg(dapm->dev, "check capture path to %s from %s\n", + source->name, sink->name); + scenario_find_capture_paths(dapm, sink, source, 1); + return dapm->num_valid_paths; +} + +/** + * snd_soc_scenario_set_path - set new scenario path + * @codec: the soc codec + * @scenario: the sceanrio path + * + * Sets up a new audio path within the audio susbsytem. + * + * Returns 0 for success. + */ +int snd_soc_scenario_set_path(struct snd_soc_dapm_context *dapm, + const char *source_name, const char *sink_name, int stream) +{ + struct snd_soc_dapm_widget *sink = NULL, *source = NULL; + struct list_head *l = NULL; + int routes; + + /* find source */ + list_for_each(l, &dapm->card->widgets) { + struct snd_soc_dapm_widget *w; + w = list_entry(l, struct snd_soc_dapm_widget, list); + + if(!source && !strncmp(w->name, source_name, 16)) { + source = w; + continue; + } + if(!sink && !strncmp(w->name, sink_name, 16)) { + sink = w; + } + } + + if(!source) { + printk(KERN_ERR "soc: invalid scenario source %s\n", source_name); + return -EINVAL; + } + if(!sink) { + printk(KERN_ERR "soc: invalid scenario sink %s\n", sink_name); + return -EINVAL; + } + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + routes = scenario_get_playback_paths(dapm, source, sink); + else + routes = scenario_get_capture_paths(dapm, source, sink); + scenario_clear_paths(dapm); + + return routes; +} +EXPORT_SYMBOL_GPL(snd_soc_scenario_set_path); + /** * snd_soc_dapm_set_bias_level - set the bias level for the system * @card: audio device @@ -193,7 +432,7 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, unsigned int mask = (1 << fls(max)) - 1; unsigned int invert = mc->invert; - val = snd_soc_read(w->codec, reg); + val = soc_widget_read(w, reg); val = (val >> shift) & mask; if ((invert && !val) || (!invert && val)) @@ -208,7 +447,7 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, for (bitmask = 1; bitmask < e->max; bitmask <<= 1) ; - val = snd_soc_read(w->codec, e->reg); + val = soc_widget_read(w, e->reg); item = (val >> e->shift_l) & (bitmask - 1); p->connect = 0; @@ -237,7 +476,7 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, w->kcontrols[i].private_value; int val, item; - val = snd_soc_read(w->codec, e->reg); + val = soc_widget_read(w, e->reg); val = (val >> e->shift_l) & e->mask; for (item = 0; item < e->max; item++) { if (val == e->values[item]) @@ -326,7 +565,6 @@ static int dapm_update_bits(struct snd_soc_dapm_widget *widget) { int change, power; unsigned int old, new; - struct snd_soc_codec *codec = widget->codec; struct snd_soc_dapm_context *dapm = widget->dapm; struct snd_soc_card *card = dapm->card; @@ -343,7 +581,7 @@ static int dapm_update_bits(struct snd_soc_dapm_widget *widget) if (widget->invert) power = (power ? 0:1); - old = snd_soc_read(codec, widget->reg); + old = soc_widget_read(widget, widget->reg); new = (old & ~(0x1 << widget->shift)) | (power << widget->shift); change = old != new; @@ -353,7 +591,7 @@ static int dapm_update_bits(struct snd_soc_dapm_widget *widget) widget->name, widget->power ? "on" : "off", card->pop_time); pop_wait(card->pop_time); - snd_soc_write(codec, widget->reg, new); + soc_widget_write(widget, widget->reg, new); } dev_dbg(dapm->dev, "reg %x old %x new %x change %d\n", widget->reg, old, new, change); @@ -367,7 +605,14 @@ static int dapm_new_mixer(struct snd_soc_dapm_context *dapm, int i, ret = 0; size_t name_len; struct snd_soc_dapm_path *path; - struct snd_card *card = dapm->codec->card->snd_card; + struct snd_card *card; + + if (dapm->codec) + card = dapm->codec->card->snd_card; + if (dapm->platform) + card = dapm->platform->card->snd_card; + if (!card) + return -ENODEV; /* add kcontrol */ for (i = 0; i < w->num_kcontrols; i++) { @@ -429,9 +674,16 @@ static int dapm_new_mux(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_path *path = NULL; struct snd_kcontrol *kcontrol; - struct snd_card *card = dapm->codec->card->snd_card; + struct snd_card *card; int ret = 0; + if (dapm->codec) + card = dapm->codec->card->snd_card; + if (dapm->platform) + card = dapm->platform->card->snd_card; + if (!card) + return -ENODEV; + if (!w->num_kcontrols) { dev_err(dapm->dev, "asoc: mux %s has no controls\n", w->name); return -EINVAL; @@ -479,7 +731,17 @@ static inline void dapm_clear_walk(struct snd_soc_dapm_context *dapm) */ static int snd_soc_dapm_suspend_check(struct snd_soc_dapm_widget *widget) { - int level = snd_power_get_state(widget->dapm->codec->card->snd_card); + struct snd_card *card; + int level; + + if (widget->codec) + card = widget->codec->card->snd_card; + else if (widget->platform) + card = widget->platform->card->snd_card; + else + return 0; + + level = snd_power_get_state(card); switch (level) { case SNDRV_CTL_POWER_D3hot: @@ -601,7 +863,7 @@ int dapm_reg_event(struct snd_soc_dapm_widget *w, else val = w->off_val; - snd_soc_update_bits(w->codec, -(w->reg + 1), + soc_widget_update_bits(w, -(w->reg + 1), w->mask << w->shift, val << w->shift); return 0; @@ -811,7 +1073,7 @@ static void dapm_seq_run_coalesced(struct snd_soc_dapm_context *dapm, struct list_head *pending) { struct snd_soc_card *card = dapm->card; - struct snd_soc_dapm_widget *w; + struct snd_soc_dapm_widget *w, *wf; int reg, power; unsigned int value = 0; unsigned int mask = 0; @@ -819,6 +1081,8 @@ static void dapm_seq_run_coalesced(struct snd_soc_dapm_context *dapm, reg = list_first_entry(pending, struct snd_soc_dapm_widget, power_list)->reg; + wf = list_first_entry(pending, struct snd_soc_dapm_widget, + power_list); list_for_each_entry(w, pending, power_list) { cur_mask = 1 << w->shift; @@ -847,7 +1111,7 @@ static void dapm_seq_run_coalesced(struct snd_soc_dapm_context *dapm, "pop test : Applying 0x%x/0x%x to %x in %dms\n", value, mask, reg, card->pop_time); pop_wait(card->pop_time); - snd_soc_update_bits(dapm->codec, reg, mask, value); + soc_widget_update_bits(wf, reg, mask, value); } list_for_each_entry(w, pending, power_list) { @@ -990,7 +1254,7 @@ static void dapm_widget_update(struct snd_soc_dapm_context *dapm) */ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) { - struct snd_soc_card *card = dapm->codec->card; + struct snd_soc_card *card = NULL; struct snd_soc_dapm_widget *w; struct snd_soc_dapm_context *d; LIST_HEAD(up_list); @@ -998,6 +1262,13 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) int ret = 0; int power; + if (dapm->codec) + card = dapm->codec->card; + if (dapm->platform) + card = dapm->platform->card; + if (!card) + return -ENODEV; + trace_snd_soc_dapm_start(card); list_for_each_entry(d, &card->dapm_list, list) @@ -1007,6 +1278,7 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) /* Check which widgets we need to power and store them in * lists indicating if they should be powered up or down. */ + mutex_lock(&card->dapm_mutex); list_for_each_entry(w, &card->widgets, list) { switch (w->id) { case snd_soc_dapm_pre: @@ -1041,6 +1313,7 @@ static int dapm_power_widgets(struct snd_soc_dapm_context *dapm, int event) break; } } + mutex_unlock(&card->dapm_mutex); /* If there are no DAPM widgets then try to figure out power from the * event type. @@ -1244,7 +1517,7 @@ void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm) #endif /* test and update the power status of a mux widget */ -static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, +int snd_soc_dapm_mux_update_power(struct snd_soc_dapm_widget *widget, struct snd_kcontrol *kcontrol, int change, int mux, struct soc_enum *e) { @@ -1280,10 +1553,11 @@ static int dapm_mux_update_power(struct snd_soc_dapm_widget *widget, return 0; } +EXPORT_SYMBOL_GPL(snd_soc_dapm_mux_update_power); /* test and update the power status of a mixer or switch widget */ -static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, - struct snd_kcontrol *kcontrol, int connect) +int snd_soc_dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, + struct snd_kcontrol *kcontrol, int connect) { struct snd_soc_dapm_path *path; int found = 0; @@ -1309,6 +1583,7 @@ static int dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, return 0; } +EXPORT_SYMBOL_GPL(snd_soc_dapm_mixer_update_power); /* show dapm widget status in sys fs */ static ssize_t dapm_widget_show(struct device *dev, @@ -1464,7 +1739,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, char prefixed_source[80]; int ret = 0; - if (dapm->codec->name_prefix) { + if (dapm->codec && dapm->codec->name_prefix) { snprintf(prefixed_sink, sizeof(prefixed_sink), "%s %s", dapm->codec->name_prefix, route->sink); sink = prefixed_sink; @@ -1686,7 +1961,7 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm) } /* Read the initial power state from the device */ - if (w->reg >= 0) { + if (w->reg >= 0 && w->codec) { val = snd_soc_read(w->codec, w->reg); val &= 1 << w->shift; if (w->invert) @@ -1704,6 +1979,23 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm) } EXPORT_SYMBOL_GPL(snd_soc_dapm_new_widgets); +const char *snd_soc_dapm_get_aif(struct snd_soc_dapm_context *dapm, + const char *stream_name, enum snd_soc_dapm_type type) +{ + struct snd_soc_dapm_widget *w; + + list_for_each_entry(w, &dapm->card->widgets, list) { + + if (!w->sname) + continue; + + if (w->id == type && strstr(w->sname, stream_name)) + return w->name; + } + return NULL; +} +EXPORT_SYMBOL_GPL(snd_soc_dapm_get_aif); + /** * snd_soc_dapm_get_volsw - dapm mixer get callback * @kcontrol: mixer control @@ -1727,10 +2019,10 @@ int snd_soc_dapm_get_volsw(struct snd_kcontrol *kcontrol, unsigned int mask = (1 << fls(max)) - 1; ucontrol->value.integer.value[0] = - (snd_soc_read(widget->codec, reg) >> shift) & mask; + (soc_widget_read(widget, reg) >> shift) & mask; if (shift != rshift) ucontrol->value.integer.value[1] = - (snd_soc_read(widget->codec, reg) >> rshift) & mask; + (soc_widget_read(widget, reg) >> rshift) & mask; if (invert) { ucontrol->value.integer.value[0] = max - ucontrol->value.integer.value[0]; @@ -1777,7 +2069,7 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; - change = snd_soc_test_bits(widget->codec, reg, mask, val); + change = soc_widget_test_bits(widget, reg, mask, val); if (change) { if (val) /* new connection */ @@ -1793,7 +2085,7 @@ int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, update.val = val; widget->dapm->update = &update; - dapm_mixer_update_power(widget, kcontrol, connect); + snd_soc_dapm_mixer_update_power(widget, kcontrol, connect); widget->dapm->update = NULL; } @@ -1821,7 +2113,7 @@ int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol, for (bitmask = 1; bitmask < e->max; bitmask <<= 1) ; - val = snd_soc_read(widget->codec, e->reg); + val = soc_widget_read(widget, e->reg); ucontrol->value.enumerated.item[0] = (val >> e->shift_l) & (bitmask - 1); if (e->shift_l != e->shift_r) ucontrol->value.enumerated.item[1] = @@ -1865,7 +2157,7 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; - change = snd_soc_test_bits(widget->codec, e->reg, mask, val); + change = soc_widget_test_bits(widget, e->reg, mask, val); update.kcontrol = kcontrol; update.widget = widget; @@ -1874,7 +2166,7 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, update.val = val; widget->dapm->update = &update; - dapm_mux_update_power(widget, kcontrol, change, mux, e); + snd_soc_dapm_mux_update_power(widget, kcontrol, change, mux, e); widget->dapm->update = NULL; @@ -1924,7 +2216,7 @@ int snd_soc_dapm_put_enum_virt(struct snd_kcontrol *kcontrol, change = widget->value != ucontrol->value.enumerated.item[0]; widget->value = ucontrol->value.enumerated.item[0]; - dapm_mux_update_power(widget, kcontrol, change, widget->value, e); + snd_soc_dapm_mux_update_power(widget, kcontrol, change, widget->value, e); mutex_unlock(&widget->codec->mutex); return ret; @@ -1951,7 +2243,7 @@ int snd_soc_dapm_get_value_enum_double(struct snd_kcontrol *kcontrol, struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; unsigned int reg_val, val, mux; - reg_val = snd_soc_read(widget->codec, e->reg); + reg_val = soc_widget_read(widget, e->reg); val = (reg_val >> e->shift_l) & e->mask; for (mux = 0; mux < e->max; mux++) { if (val == e->values[mux]) @@ -2007,7 +2299,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, mutex_lock(&widget->codec->mutex); widget->value = val; - change = snd_soc_test_bits(widget->codec, e->reg, mask, val); + change = soc_widget_test_bits(widget, e->reg, mask, val); update.kcontrol = kcontrol; update.widget = widget; @@ -2016,7 +2308,7 @@ int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol, update.val = val; widget->dapm->update = &update; - dapm_mux_update_power(widget, kcontrol, change, mux, e); + snd_soc_dapm_mux_update_power(widget, kcontrol, change, mux, e); widget->dapm->update = NULL; @@ -2114,14 +2406,14 @@ int snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, return -ENOMEM; name_len = strlen(widget->name) + 1; - if (dapm->codec->name_prefix) + if (dapm->codec && dapm->codec->name_prefix) name_len += 1 + strlen(dapm->codec->name_prefix); w->name = kmalloc(name_len, GFP_KERNEL); if (w->name == NULL) { kfree(w); return -ENOMEM; } - if (dapm->codec->name_prefix) + if (dapm->codec && dapm->codec->name_prefix) snprintf(w->name, name_len, "%s %s", dapm->codec->name_prefix, widget->name); else @@ -2130,6 +2422,7 @@ int snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, dapm->n_widgets++; w->dapm = dapm; w->codec = dapm->codec; + w->platform = dapm->platform; INIT_LIST_HEAD(&w->sources); INIT_LIST_HEAD(&w->sinks); INIT_LIST_HEAD(&w->list); @@ -2200,6 +2493,10 @@ static void soc_dapm_stream_event(struct snd_soc_dapm_context *dapm, } dapm_power_widgets(dapm, event); + + /* do we need to notify any clients that DAPM stream is complete */ + if (dapm->stream_event) + dapm->stream_event(dapm); } /** @@ -2214,16 +2511,27 @@ static void soc_dapm_stream_event(struct snd_soc_dapm_context *dapm, * Returns 0 for success else error. */ int snd_soc_dapm_stream_event(struct snd_soc_pcm_runtime *rtd, - const char *stream, int event) + int dir, const char *stream, int event) { - struct snd_soc_codec *codec = rtd->codec; + int i; if (stream == NULL) return 0; - mutex_lock(&codec->mutex); - soc_dapm_stream_event(&codec->dapm, stream, event); - mutex_unlock(&codec->mutex); + if (rtd->dai_link->dynamic) { + for (i = 0; i < rtd->num_be[dir]; i++) { + struct snd_soc_platform *platform = rtd->be_rtd[i][dir]->platform; + + soc_dapm_stream_event(&platform->dapm, stream, event); + } + } else { + struct snd_soc_codec *codec = rtd->codec; + + mutex_lock(&codec->mutex); + soc_dapm_stream_event(&(codec->dapm), stream, event); + mutex_unlock(&codec->mutex); + } + return 0; } EXPORT_SYMBOL_GPL(snd_soc_dapm_stream_event); diff --git a/sound/soc/txx9/txx9aclc.c b/sound/soc/txx9/txx9aclc.c index f4aa4e03c88..53ec40b356d 100644 --- a/sound/soc/txx9/txx9aclc.c +++ b/sound/soc/txx9/txx9aclc.c @@ -288,9 +288,10 @@ static void txx9aclc_pcm_free_dma_buffers(struct snd_pcm *pcm) snd_pcm_lib_preallocate_free_for_all(pcm); } -static int txx9aclc_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) +static int txx9aclc_pcm_new(struct snd_soc_pcm_runtime *rtd) { + struct snd_card *card = rtd->card->snd_card; + struct snd_pcm *pcm = rtd->pcm; struct platform_device *pdev = to_platform_device(dai->platform->dev); struct txx9aclc_soc_device *dev; struct resource *r; |