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This update the register initialization/reset values (aka initvals)
for ar9271 based on the last recommended values on 2009-06-04 by our
systems engineering team.
The changes account for:
* Supporting ar9271 1.0 and ar9271 1.1 together, the difference
is bb_spectral_scan_ena, for 1.0 we'll set this to 0x1.
* Ensuring we get the correct noise floor values -115 ~ -118
when we enable bb_enable_ant_div_lnadiv=0 and
mc_tx_def_ant_sel=1. Previous to this we would get noise
floor values in the range -50 ~ -80. To fix settings for
the registers:
- bb_ch1_xatten1_db
- bb_ch1_xatten2_db
- bb_ch1_xatten1_margin
- bb_ch1_xatten2_margin
- bb_ch1_gain_force
- bb_ch1_xatten2_hyst_margin
- bb_ch1_xatten1_hyst_margin
- bb_ch1_max_oc_gain
* 0x8120[2] mc_mic_new_location_enable is changed to 0x1. The MAC team
suggest to set this value.
* 0x9910[0] bb_spectral_scan_ena is changed to 0x0.
For ar9271 1.1 we don't need to enable this bit.
Cc: Stephen Chen <Stephen.Chen@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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* Move 0xa274 and 0xa27c to the top of tx_gain table.
* Update initvals to fix random failure of noise floor calibration.
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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If the current channel is between 2412 and 2472 MHz and if the channel is
changing to 2484 MHz, then the registers 0xa1f4, 0xa1f8 and 0xa1fc need to be
programmed to the "japan_2484" values. Conversely, if the current channel
is 2484 MHz and if the channel is changing to one between 2412 and 2472 MHz, then
the three registers need to be programmed to the "normal" values.
This is needed for compliance with Japanese regulatory requirements.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Cc: Stephen Chen <stephen.chen@atheros.com>
Cc: Zhifeng Cai <zhifeng.cai@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Running iperf along with p2p traffic on both TX and RX side then
stop one side, then stop the other side, then start it up again,
eventually the STA gets into a mode that it can not pass data at
all.
A hardware workaround for invalid RSSI can make FIFO write pointer
to jump over read pointer, causing RX data corruption and repeated
DMA. Both TX and RX works fine when the workaround is disabled.
To replace the original hardware work around, software looks for
frames with post delimiter CRC error and mark the RSSI invalid so
that the upperlayer will not use the RSSI associated with this
frame. So disable the hardware workaround by updating the appropriate
registers.
Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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